1 //===-- RegAllocBase.cpp - Register Allocator Base Class ------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the RegAllocBase class which provides common functionality
11 // for LiveIntervalUnion-based register allocators.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "RegAllocBase.h"
16 #include "Spiller.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/LiveRangeEdit.h"
20 #include "llvm/CodeGen/LiveRegMatrix.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/VirtRegMap.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #ifndef NDEBUG
26 #include "llvm/ADT/SparseBitVector.h"
27 #endif
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Support/Timer.h"
34
35 using namespace llvm;
36
37 #define DEBUG_TYPE "regalloc"
38
39 STATISTIC(NumNewQueued , "Number of new live ranges queued");
40
41 // Temporary verification option until we can put verification inside
42 // MachineVerifier.
43 static cl::opt<bool, true>
44 VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
45 cl::desc("Verify during register allocation"));
46
47 const char RegAllocBase::TimerGroupName[] = "Register Allocation";
48 bool RegAllocBase::VerifyEnabled = false;
49
50 //===----------------------------------------------------------------------===//
51 // RegAllocBase Implementation
52 //===----------------------------------------------------------------------===//
53
54 // Pin the vtable to this file.
anchor()55 void RegAllocBase::anchor() {}
56
init(VirtRegMap & vrm,LiveIntervals & lis,LiveRegMatrix & mat)57 void RegAllocBase::init(VirtRegMap &vrm,
58 LiveIntervals &lis,
59 LiveRegMatrix &mat) {
60 TRI = &vrm.getTargetRegInfo();
61 MRI = &vrm.getRegInfo();
62 VRM = &vrm;
63 LIS = &lis;
64 Matrix = &mat;
65 MRI->freezeReservedRegs(vrm.getMachineFunction());
66 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
67 }
68
69 // Visit all the live registers. If they are already assigned to a physical
70 // register, unify them with the corresponding LiveIntervalUnion, otherwise push
71 // them on the priority queue for later assignment.
seedLiveRegs()72 void RegAllocBase::seedLiveRegs() {
73 NamedRegionTimer T("Seed Live Regs", TimerGroupName, TimePassesIsEnabled);
74 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
75 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
76 if (MRI->reg_nodbg_empty(Reg))
77 continue;
78 enqueue(&LIS->getInterval(Reg));
79 }
80 }
81
82 // Top-level driver to manage the queue of unassigned VirtRegs and call the
83 // selectOrSplit implementation.
allocatePhysRegs()84 void RegAllocBase::allocatePhysRegs() {
85 seedLiveRegs();
86
87 // Continue assigning vregs one at a time to available physical registers.
88 while (LiveInterval *VirtReg = dequeue()) {
89 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
90
91 // Unused registers can appear when the spiller coalesces snippets.
92 if (MRI->reg_nodbg_empty(VirtReg->reg)) {
93 DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
94 aboutToRemoveInterval(*VirtReg);
95 LIS->removeInterval(VirtReg->reg);
96 continue;
97 }
98
99 // Invalidate all interference queries, live ranges could have changed.
100 Matrix->invalidateVirtRegs();
101
102 // selectOrSplit requests the allocator to return an available physical
103 // register if possible and populate a list of new live intervals that
104 // result from splitting.
105 DEBUG(dbgs() << "\nselectOrSplit "
106 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg))
107 << ':' << *VirtReg << " w=" << VirtReg->weight << '\n');
108 typedef SmallVector<unsigned, 4> VirtRegVec;
109 VirtRegVec SplitVRegs;
110 unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
111
112 if (AvailablePhysReg == ~0u) {
113 // selectOrSplit failed to find a register!
114 // Probably caused by an inline asm.
115 MachineInstr *MI = nullptr;
116 for (MachineRegisterInfo::reg_instr_iterator
117 I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end();
118 I != E; ) {
119 MachineInstr *TmpMI = &*(I++);
120 if (TmpMI->isInlineAsm()) {
121 MI = TmpMI;
122 break;
123 }
124 }
125 if (MI)
126 MI->emitError("inline assembly requires more registers than available");
127 else
128 report_fatal_error("ran out of registers during register allocation");
129 // Keep going after reporting the error.
130 VRM->assignVirt2Phys(VirtReg->reg,
131 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
132 continue;
133 }
134
135 if (AvailablePhysReg)
136 Matrix->assign(*VirtReg, AvailablePhysReg);
137
138 for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
139 I != E; ++I) {
140 LiveInterval *SplitVirtReg = &LIS->getInterval(*I);
141 assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
142 if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
143 DEBUG(dbgs() << "not queueing unused " << *SplitVirtReg << '\n');
144 aboutToRemoveInterval(*SplitVirtReg);
145 LIS->removeInterval(SplitVirtReg->reg);
146 continue;
147 }
148 DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
149 assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
150 "expect split value in virtual register");
151 enqueue(SplitVirtReg);
152 ++NumNewQueued;
153 }
154 }
155 }
156