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Searched defs:base (Results 1 – 25 of 53) sorted by relevance

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/art/compiler/utils/arm64/
Dassembler_arm64.cc96 XRegister base, int32_t offset) { in StoreWToOffset()
112 void Arm64Assembler::StoreToOffset(XRegister source, XRegister base, int32_t offset) { in StoreToOffset()
117 void Arm64Assembler::StoreSToOffset(SRegister source, XRegister base, int32_t offset) { in StoreSToOffset()
121 void Arm64Assembler::StoreDToOffset(DRegister source, XRegister base, int32_t offset) { in StoreDToOffset()
219 XRegister base, int32_t offset) { in LoadWFromOffset()
243 void Arm64Assembler::LoadFromOffset(XRegister dest, XRegister base, in LoadFromOffset()
249 void Arm64Assembler::LoadSFromOffset(SRegister dest, XRegister base, in LoadSFromOffset()
254 void Arm64Assembler::LoadDFromOffset(DRegister dest, XRegister base, in LoadDFromOffset()
259 void Arm64Assembler::Load(Arm64ManagedRegister dest, XRegister base, in Load()
299 Arm64ManagedRegister base = m_base.AsArm64(); in LoadRef() local
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/art/test/065-mismatched-implements/src/
DIndirect.java25 Base base = new Base(); in main() local
/art/test/066-mismatched-super/src/
DIndirect.java25 Base base = new Base(); in main() local
/art/test/106-exceptions2/src/
DMain.java134 Main base = new Main(); in nullCheckTestNoThrow() local
143 Main base = new Main(); in nullCheckTestThrow() local
/art/compiler/utils/
Dassembler_test.h186 std::string base = fmt; variable
353 std::string base = fmt; in RepeatTemplatedRegister() local
384 std::string base = fmt; in RepeatTemplatedRegisters() local
426 std::string base = fmt; in RepeatTemplatedRegistersImm() local
519 std::string base = fmt; in RepeatRegisterImm() local
/art/runtime/gc/space/
Ddlmalloc_space.h152 void* CreateAllocator(void* base, size_t morecore_start, size_t initial_size, in CreateAllocator()
Drosalloc_space.h158 void* CreateAllocator(void* base, size_t morecore_start, size_t initial_size, in CreateAllocator()
/art/compiler/utils/mips/
Dassembler_mips.cc478 void MipsAssembler::LoadFromOffset(LoadOperandType type, Register reg, Register base, in LoadFromOffset()
504 void MipsAssembler::LoadSFromOffset(FRegister reg, Register base, int32_t offset) { in LoadSFromOffset()
508 void MipsAssembler::LoadDFromOffset(DRegister reg, Register base, int32_t offset) { in LoadDFromOffset()
512 void MipsAssembler::StoreToOffset(StoreOperandType type, Register reg, Register base, in StoreToOffset()
532 void MipsAssembler::StoreFToOffset(FRegister reg, Register base, int32_t offset) { in StoreFToOffset()
536 void MipsAssembler::StoreDToOffset(DRegister reg, Register base, int32_t offset) { in StoreDToOffset()
699 void MipsAssembler::LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffset offs, in LoadRef()
710 void MipsAssembler::LoadRawPtr(ManagedRegister mdest, ManagedRegister base, in LoadRawPtr()
922 MipsManagedRegister base = mbase.AsMips(); in Call() local
932 void MipsAssembler::Call(FrameOffset base, Offset offset, ManagedRegister mscratch) { in Call()
/art/test/072-precise-gc/src/
DMain.java61 static String generateString(String base, int num) { in generateString()
/art/compiler/
Dcfi_test.h61 const uint8_t* base = actual_asm.data() + (isa == kThumb2 ? 1 : 0); in GenerateExpected() local
/art/test/003-omnibus-opcodes/src/
DMethodCall.java56 MethodCallBase base = inst; in run() local
/art/compiler/dex/quick/arm64/
Dint_arm64.cc484 uint64_t base = DecodeLogicalImmediate(/*is_wide*/true, magic_table[lit].magic64_base); in SmallLiteralDivRem64() local
1476 static void SpillCoreRegs(Arm64Mir2Lir* m2l, RegStorage base, int offset, uint32_t reg_mask) { in SpillCoreRegs()
1495 static void SpillFPRegs(Arm64Mir2Lir* m2l, RegStorage base, int offset, uint32_t reg_mask) { in SpillFPRegs()
1537 static int SpillRegsPreIndexed(Arm64Mir2Lir* m2l, RegStorage base, uint32_t core_reg_mask, in SpillRegsPreIndexed()
1674 int Arm64Mir2Lir::SpillRegs(RegStorage base, uint32_t core_reg_mask, uint32_t fp_reg_mask, in SpillRegs()
1689 static void UnSpillCoreRegs(Arm64Mir2Lir* m2l, RegStorage base, int offset, uint32_t reg_mask) { in UnSpillCoreRegs()
1708 static void UnSpillFPRegs(Arm64Mir2Lir* m2l, RegStorage base, int offset, uint32_t reg_mask) { in UnSpillFPRegs()
1727 void Arm64Mir2Lir::UnspillRegs(RegStorage base, uint32_t core_reg_mask, uint32_t fp_reg_mask, in UnspillRegs()
/art/compiler/dex/
Dlocal_value_numbering.h179 uint16_t base; // Or array. member
209 uint16_t base; member
Dlocal_value_numbering.cc73 uint16_t field_id, uint16_t base, uint16_t memory_version) { in LookupGlobalValue()
78 uint16_t field_id, uint16_t base) { in LookupMergeValue()
105 uint16_t field_id, uint16_t base) { in LookupMergeLocationValue()
1115 uint16_t base = GetOperandValue(mir->ssa_rep->uses[0]); in HandlePutObject() local
1125 void LocalValueNumbering::HandleEscapingRef(uint16_t base) { in HandleEscapingRef()
1297 uint16_t base = GetOperandValue(mir->ssa_rep->uses[0]); in HandleIGet() local
1334 uint16_t base = GetOperandValue(mir->ssa_rep->uses[base_reg]); in HandleIPut() local
Dglobal_value_numbering.cc149 uint16_t GlobalValueNumbering::GetArrayLocation(uint16_t base, uint16_t index) { in GetArrayLocation()
/art/runtime/
Dmonitor_pool.h126 uintptr_t base = *(monitor_chunks_.LoadRelaxed()+index); in LookupMonitor() local
Doat_file.h137 OatMethod(const uint8_t* base, const uint32_t code_offset) in OatMethod()
Dmem_map.cc72 void* base = it->first; in operator <<() local
691 void* base = it->first; in DumpMapsLocked() local
/art/compiler/utils/arm/
Dassembler_arm.cc531 void ArmAssembler::LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffset offs, in LoadRef()
548 void ArmAssembler::LoadRawPtr(ManagedRegister mdest, ManagedRegister base, in LoadRawPtr()
804 ArmManagedRegister base = mbase.AsArm(); in Call() local
814 void ArmAssembler::Call(FrameOffset base, Offset offset, in Call()
Dassembler_arm32.cc333 Register base, in ldm()
341 Register base, in stm()
670 Register base, in EmitMultiMemOp()
1437 Register base, in LoadFromOffset()
1477 Register base, in LoadSFromOffset()
1495 Register base, in LoadDFromOffset()
1514 Register base, in StoreToOffset()
1549 Register base, in StoreSToOffset()
1567 Register base, in StoreDToOffset()
/art/runtime/arch/x86/
Dthread_x86.cc47 const uintptr_t base = reinterpret_cast<uintptr_t>(this); in InitCpu() local
/art/compiler/dex/quick/mips/
Dfp_mips.cc186 static RegStorage GetWideArgFP(bool fpuIs32Bit, size_t base) { in GetWideArgFP()
/art/compiler/optimizing/
Dcommon_arm64.h154 static inline vixl::MemOperand HeapOperand(const vixl::Register& base, Offset offset) { in HeapOperand()
/art/compiler/jit/
Djit_compiler.cc217 const uint8_t* base = code_cache->CodeCachePtr(); in AddToCodeCache() local
/art/compiler/utils/mips64/
Dassembler_mips64.cc935 void Mips64Assembler::LoadFromOffset(LoadOperandType type, GpuRegister reg, GpuRegister base, in LoadFromOffset()
969 void Mips64Assembler::LoadFpuFromOffset(LoadOperandType type, FpuRegister reg, GpuRegister base, in LoadFpuFromOffset()
1017 void Mips64Assembler::StoreToOffset(StoreOperandType type, GpuRegister reg, GpuRegister base, in StoreToOffset()
1044 void Mips64Assembler::StoreFpuToOffset(StoreOperandType type, FpuRegister reg, GpuRegister base, in StoreFpuToOffset()
1244 void Mips64Assembler::LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffset offs, in LoadRef()
1259 void Mips64Assembler::LoadRawPtr(ManagedRegister mdest, ManagedRegister base, in LoadRawPtr()
1491 Mips64ManagedRegister base = mbase.AsMips64(); in Call() local
1501 void Mips64Assembler::Call(FrameOffset base, Offset offset, ManagedRegister mscratch) { in Call()

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