1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains code to lower X86 MachineInstrs to their corresponding
11 // MCInst records.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "X86AsmPrinter.h"
16 #include "X86RegisterInfo.h"
17 #include "InstPrinter/X86ATTInstPrinter.h"
18 #include "MCTargetDesc/X86BaseInfo.h"
19 #include "Utils/X86ShuffleDecode.h"
20 #include "llvm/ADT/SmallString.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
25 #include "llvm/CodeGen/StackMaps.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Mangler.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCCodeEmitter.h"
31 #include "llvm/MC/MCContext.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCInst.h"
34 #include "llvm/MC/MCInstBuilder.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/MC/MCSymbol.h"
37 #include "llvm/Support/TargetRegistry.h"
38 using namespace llvm;
39
40 namespace {
41
42 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
43 class X86MCInstLower {
44 MCContext &Ctx;
45 const MachineFunction &MF;
46 const TargetMachine &TM;
47 const MCAsmInfo &MAI;
48 X86AsmPrinter &AsmPrinter;
49 public:
50 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
51
52 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
53
54 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
55 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
56
57 private:
58 MachineModuleInfoMachO &getMachOMMI() const;
getMang() const59 Mangler *getMang() const {
60 return AsmPrinter.Mang;
61 }
62 };
63
64 } // end anonymous namespace
65
66 // Emit a minimal sequence of nops spanning NumBytes bytes.
67 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
68 const MCSubtargetInfo &STI);
69
70 namespace llvm {
StackMapShadowTracker(TargetMachine & TM)71 X86AsmPrinter::StackMapShadowTracker::StackMapShadowTracker(TargetMachine &TM)
72 : TM(TM), InShadow(false), RequiredShadowSize(0), CurrentShadowSize(0) {}
73
~StackMapShadowTracker()74 X86AsmPrinter::StackMapShadowTracker::~StackMapShadowTracker() {}
75
76 void
startFunction(MachineFunction & F)77 X86AsmPrinter::StackMapShadowTracker::startFunction(MachineFunction &F) {
78 MF = &F;
79 CodeEmitter.reset(TM.getTarget().createMCCodeEmitter(
80 *MF->getSubtarget().getInstrInfo(),
81 *MF->getSubtarget().getRegisterInfo(), MF->getContext()));
82 }
83
count(MCInst & Inst,const MCSubtargetInfo & STI)84 void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
85 const MCSubtargetInfo &STI) {
86 if (InShadow) {
87 SmallString<256> Code;
88 SmallVector<MCFixup, 4> Fixups;
89 raw_svector_ostream VecOS(Code);
90 CodeEmitter->EncodeInstruction(Inst, VecOS, Fixups, STI);
91 VecOS.flush();
92 CurrentShadowSize += Code.size();
93 if (CurrentShadowSize >= RequiredShadowSize)
94 InShadow = false; // The shadow is big enough. Stop counting.
95 }
96 }
97
emitShadowPadding(MCStreamer & OutStreamer,const MCSubtargetInfo & STI)98 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
99 MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
100 if (InShadow && CurrentShadowSize < RequiredShadowSize) {
101 InShadow = false;
102 EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
103 MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
104 }
105 }
106
EmitAndCountInstruction(MCInst & Inst)107 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
108 OutStreamer.EmitInstruction(Inst, getSubtargetInfo());
109 SMShadowTracker.count(Inst, getSubtargetInfo());
110 }
111 } // end llvm namespace
112
X86MCInstLower(const MachineFunction & mf,X86AsmPrinter & asmprinter)113 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
114 X86AsmPrinter &asmprinter)
115 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
116 AsmPrinter(asmprinter) {}
117
getMachOMMI() const118 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
119 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
120 }
121
122
123 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
124 /// operand to an MCSymbol.
125 MCSymbol *X86MCInstLower::
GetSymbolFromOperand(const MachineOperand & MO) const126 GetSymbolFromOperand(const MachineOperand &MO) const {
127 const DataLayout *DL = TM.getDataLayout();
128 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
129
130 SmallString<128> Name;
131 StringRef Suffix;
132
133 switch (MO.getTargetFlags()) {
134 case X86II::MO_DLLIMPORT:
135 // Handle dllimport linkage.
136 Name += "__imp_";
137 break;
138 case X86II::MO_DARWIN_STUB:
139 Suffix = "$stub";
140 break;
141 case X86II::MO_DARWIN_NONLAZY:
142 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
143 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
144 Suffix = "$non_lazy_ptr";
145 break;
146 }
147
148 if (!Suffix.empty())
149 Name += DL->getPrivateGlobalPrefix();
150
151 unsigned PrefixLen = Name.size();
152
153 if (MO.isGlobal()) {
154 const GlobalValue *GV = MO.getGlobal();
155 AsmPrinter.getNameWithPrefix(Name, GV);
156 } else if (MO.isSymbol()) {
157 getMang()->getNameWithPrefix(Name, MO.getSymbolName());
158 } else if (MO.isMBB()) {
159 Name += MO.getMBB()->getSymbol()->getName();
160 }
161 unsigned OrigLen = Name.size() - PrefixLen;
162
163 Name += Suffix;
164 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name);
165
166 StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen);
167
168 // If the target flags on the operand changes the name of the symbol, do that
169 // before we return the symbol.
170 switch (MO.getTargetFlags()) {
171 default: break;
172 case X86II::MO_DARWIN_NONLAZY:
173 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
174 MachineModuleInfoImpl::StubValueTy &StubSym =
175 getMachOMMI().getGVStubEntry(Sym);
176 if (!StubSym.getPointer()) {
177 assert(MO.isGlobal() && "Extern symbol not handled yet");
178 StubSym =
179 MachineModuleInfoImpl::
180 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
181 !MO.getGlobal()->hasInternalLinkage());
182 }
183 break;
184 }
185 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
186 MachineModuleInfoImpl::StubValueTy &StubSym =
187 getMachOMMI().getHiddenGVStubEntry(Sym);
188 if (!StubSym.getPointer()) {
189 assert(MO.isGlobal() && "Extern symbol not handled yet");
190 StubSym =
191 MachineModuleInfoImpl::
192 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
193 !MO.getGlobal()->hasInternalLinkage());
194 }
195 break;
196 }
197 case X86II::MO_DARWIN_STUB: {
198 MachineModuleInfoImpl::StubValueTy &StubSym =
199 getMachOMMI().getFnStubEntry(Sym);
200 if (StubSym.getPointer())
201 return Sym;
202
203 if (MO.isGlobal()) {
204 StubSym =
205 MachineModuleInfoImpl::
206 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
207 !MO.getGlobal()->hasInternalLinkage());
208 } else {
209 StubSym =
210 MachineModuleInfoImpl::
211 StubValueTy(Ctx.GetOrCreateSymbol(OrigName), false);
212 }
213 break;
214 }
215 }
216
217 return Sym;
218 }
219
LowerSymbolOperand(const MachineOperand & MO,MCSymbol * Sym) const220 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
221 MCSymbol *Sym) const {
222 // FIXME: We would like an efficient form for this, so we don't have to do a
223 // lot of extra uniquing.
224 const MCExpr *Expr = nullptr;
225 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
226
227 switch (MO.getTargetFlags()) {
228 default: llvm_unreachable("Unknown target flag on GV operand");
229 case X86II::MO_NO_FLAG: // No flag.
230 // These affect the name of the symbol, not any suffix.
231 case X86II::MO_DARWIN_NONLAZY:
232 case X86II::MO_DLLIMPORT:
233 case X86II::MO_DARWIN_STUB:
234 break;
235
236 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
237 case X86II::MO_TLVP_PIC_BASE:
238 Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
239 // Subtract the pic base.
240 Expr = MCBinaryExpr::CreateSub(Expr,
241 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(),
242 Ctx),
243 Ctx);
244 break;
245 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break;
246 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
247 case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break;
248 case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
249 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
250 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
251 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
252 case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
253 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
254 case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
255 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
256 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
257 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
258 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
259 case X86II::MO_PIC_BASE_OFFSET:
260 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
261 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
262 Expr = MCSymbolRefExpr::Create(Sym, Ctx);
263 // Subtract the pic base.
264 Expr = MCBinaryExpr::CreateSub(Expr,
265 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx),
266 Ctx);
267 if (MO.isJTI()) {
268 assert(MAI.doesSetDirectiveSuppressesReloc());
269 // If .set directive is supported, use it to reduce the number of
270 // relocations the assembler will generate for differences between
271 // local labels. This is only safe when the symbols are in the same
272 // section so we are restricting it to jumptable references.
273 MCSymbol *Label = Ctx.CreateTempSymbol();
274 AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
275 Expr = MCSymbolRefExpr::Create(Label, Ctx);
276 }
277 break;
278 }
279
280 if (!Expr)
281 Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
282
283 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
284 Expr = MCBinaryExpr::CreateAdd(Expr,
285 MCConstantExpr::Create(MO.getOffset(), Ctx),
286 Ctx);
287 return MCOperand::CreateExpr(Expr);
288 }
289
290
291 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
292 /// a short fixed-register form.
SimplifyShortImmForm(MCInst & Inst,unsigned Opcode)293 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
294 unsigned ImmOp = Inst.getNumOperands() - 1;
295 assert(Inst.getOperand(0).isReg() &&
296 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
297 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
298 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
299 Inst.getNumOperands() == 2) && "Unexpected instruction!");
300
301 // Check whether the destination register can be fixed.
302 unsigned Reg = Inst.getOperand(0).getReg();
303 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
304 return;
305
306 // If so, rewrite the instruction.
307 MCOperand Saved = Inst.getOperand(ImmOp);
308 Inst = MCInst();
309 Inst.setOpcode(Opcode);
310 Inst.addOperand(Saved);
311 }
312
313 /// \brief If a movsx instruction has a shorter encoding for the used register
314 /// simplify the instruction to use it instead.
SimplifyMOVSX(MCInst & Inst)315 static void SimplifyMOVSX(MCInst &Inst) {
316 unsigned NewOpcode = 0;
317 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
318 switch (Inst.getOpcode()) {
319 default:
320 llvm_unreachable("Unexpected instruction!");
321 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
322 if (Op0 == X86::AX && Op1 == X86::AL)
323 NewOpcode = X86::CBW;
324 break;
325 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl
326 if (Op0 == X86::EAX && Op1 == X86::AX)
327 NewOpcode = X86::CWDE;
328 break;
329 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
330 if (Op0 == X86::RAX && Op1 == X86::EAX)
331 NewOpcode = X86::CDQE;
332 break;
333 }
334
335 if (NewOpcode != 0) {
336 Inst = MCInst();
337 Inst.setOpcode(NewOpcode);
338 }
339 }
340
341 /// \brief Simplify things like MOV32rm to MOV32o32a.
SimplifyShortMoveForm(X86AsmPrinter & Printer,MCInst & Inst,unsigned Opcode)342 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
343 unsigned Opcode) {
344 // Don't make these simplifications in 64-bit mode; other assemblers don't
345 // perform them because they make the code larger.
346 if (Printer.getSubtarget().is64Bit())
347 return;
348
349 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
350 unsigned AddrBase = IsStore;
351 unsigned RegOp = IsStore ? 0 : 5;
352 unsigned AddrOp = AddrBase + 3;
353 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
354 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
355 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
356 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
357 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
358 (Inst.getOperand(AddrOp).isExpr() ||
359 Inst.getOperand(AddrOp).isImm()) &&
360 "Unexpected instruction!");
361
362 // Check whether the destination register can be fixed.
363 unsigned Reg = Inst.getOperand(RegOp).getReg();
364 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
365 return;
366
367 // Check whether this is an absolute address.
368 // FIXME: We know TLVP symbol refs aren't, but there should be a better way
369 // to do this here.
370 bool Absolute = true;
371 if (Inst.getOperand(AddrOp).isExpr()) {
372 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
373 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
374 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
375 Absolute = false;
376 }
377
378 if (Absolute &&
379 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
380 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
381 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
382 return;
383
384 // If so, rewrite the instruction.
385 MCOperand Saved = Inst.getOperand(AddrOp);
386 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
387 Inst = MCInst();
388 Inst.setOpcode(Opcode);
389 Inst.addOperand(Saved);
390 Inst.addOperand(Seg);
391 }
392
getRetOpcode(const X86Subtarget & Subtarget)393 static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
394 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
395 }
396
Lower(const MachineInstr * MI,MCInst & OutMI) const397 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
398 OutMI.setOpcode(MI->getOpcode());
399
400 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
401 const MachineOperand &MO = MI->getOperand(i);
402
403 MCOperand MCOp;
404 switch (MO.getType()) {
405 default:
406 MI->dump();
407 llvm_unreachable("unknown operand type");
408 case MachineOperand::MO_Register:
409 // Ignore all implicit register operands.
410 if (MO.isImplicit()) continue;
411 MCOp = MCOperand::CreateReg(MO.getReg());
412 break;
413 case MachineOperand::MO_Immediate:
414 MCOp = MCOperand::CreateImm(MO.getImm());
415 break;
416 case MachineOperand::MO_MachineBasicBlock:
417 case MachineOperand::MO_GlobalAddress:
418 case MachineOperand::MO_ExternalSymbol:
419 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
420 break;
421 case MachineOperand::MO_JumpTableIndex:
422 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
423 break;
424 case MachineOperand::MO_ConstantPoolIndex:
425 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
426 break;
427 case MachineOperand::MO_BlockAddress:
428 MCOp = LowerSymbolOperand(MO,
429 AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
430 break;
431 case MachineOperand::MO_RegisterMask:
432 // Ignore call clobbers.
433 continue;
434 }
435
436 OutMI.addOperand(MCOp);
437 }
438
439 // Handle a few special cases to eliminate operand modifiers.
440 ReSimplify:
441 switch (OutMI.getOpcode()) {
442 case X86::LEA64_32r:
443 case X86::LEA64r:
444 case X86::LEA16r:
445 case X86::LEA32r:
446 // LEA should have a segment register, but it must be empty.
447 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
448 "Unexpected # of LEA operands");
449 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
450 "LEA has segment specified!");
451 break;
452
453 case X86::MOV32ri64:
454 OutMI.setOpcode(X86::MOV32ri);
455 break;
456
457 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
458 // if one of the registers is extended, but other isn't.
459 case X86::VMOVAPDrr:
460 case X86::VMOVAPDYrr:
461 case X86::VMOVAPSrr:
462 case X86::VMOVAPSYrr:
463 case X86::VMOVDQArr:
464 case X86::VMOVDQAYrr:
465 case X86::VMOVDQUrr:
466 case X86::VMOVDQUYrr:
467 case X86::VMOVUPDrr:
468 case X86::VMOVUPDYrr:
469 case X86::VMOVUPSrr:
470 case X86::VMOVUPSYrr: {
471 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
472 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
473 unsigned NewOpc;
474 switch (OutMI.getOpcode()) {
475 default: llvm_unreachable("Invalid opcode");
476 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
477 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
478 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
479 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
480 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
481 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
482 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
483 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
484 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
485 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
486 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
487 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
488 }
489 OutMI.setOpcode(NewOpc);
490 }
491 break;
492 }
493 case X86::VMOVSDrr:
494 case X86::VMOVSSrr: {
495 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
496 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
497 unsigned NewOpc;
498 switch (OutMI.getOpcode()) {
499 default: llvm_unreachable("Invalid opcode");
500 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
501 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
502 }
503 OutMI.setOpcode(NewOpc);
504 }
505 break;
506 }
507
508 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
509 // inputs modeled as normal uses instead of implicit uses. As such, truncate
510 // off all but the first operand (the callee). FIXME: Change isel.
511 case X86::TAILJMPr64:
512 case X86::TAILJMPr64_REX:
513 case X86::CALL64r:
514 case X86::CALL64pcrel32: {
515 unsigned Opcode = OutMI.getOpcode();
516 MCOperand Saved = OutMI.getOperand(0);
517 OutMI = MCInst();
518 OutMI.setOpcode(Opcode);
519 OutMI.addOperand(Saved);
520 break;
521 }
522
523 case X86::EH_RETURN:
524 case X86::EH_RETURN64: {
525 OutMI = MCInst();
526 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
527 break;
528 }
529
530 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
531 case X86::TAILJMPr:
532 case X86::TAILJMPd:
533 case X86::TAILJMPd64: {
534 unsigned Opcode;
535 switch (OutMI.getOpcode()) {
536 default: llvm_unreachable("Invalid opcode");
537 case X86::TAILJMPr: Opcode = X86::JMP32r; break;
538 case X86::TAILJMPd:
539 case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
540 }
541
542 MCOperand Saved = OutMI.getOperand(0);
543 OutMI = MCInst();
544 OutMI.setOpcode(Opcode);
545 OutMI.addOperand(Saved);
546 break;
547 }
548
549 case X86::DEC16r:
550 case X86::DEC32r:
551 case X86::INC16r:
552 case X86::INC32r:
553 // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
554 if (!AsmPrinter.getSubtarget().is64Bit()) {
555 unsigned Opcode;
556 switch (OutMI.getOpcode()) {
557 default: llvm_unreachable("Invalid opcode");
558 case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
559 case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
560 case X86::INC16r: Opcode = X86::INC16r_alt; break;
561 case X86::INC32r: Opcode = X86::INC32r_alt; break;
562 }
563 OutMI.setOpcode(Opcode);
564 }
565 break;
566
567 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do
568 // this with an ugly goto in case the resultant OR uses EAX and needs the
569 // short form.
570 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
571 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
572 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
573 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
574 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
575 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
576 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
577 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
578 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
579
580 // Atomic load and store require a separate pseudo-inst because Acquire
581 // implies mayStore and Release implies mayLoad; fix these to regular MOV
582 // instructions here
583 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
584 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
585 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
586 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
587 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
588 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
589 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
590 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
591 case X86::RELEASE_MOV8mi: OutMI.setOpcode(X86::MOV8mi); goto ReSimplify;
592 case X86::RELEASE_MOV16mi: OutMI.setOpcode(X86::MOV16mi); goto ReSimplify;
593 case X86::RELEASE_MOV32mi: OutMI.setOpcode(X86::MOV32mi); goto ReSimplify;
594 case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify;
595 case X86::RELEASE_ADD8mi: OutMI.setOpcode(X86::ADD8mi); goto ReSimplify;
596 case X86::RELEASE_ADD32mi: OutMI.setOpcode(X86::ADD32mi); goto ReSimplify;
597 case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify;
598 case X86::RELEASE_AND8mi: OutMI.setOpcode(X86::AND8mi); goto ReSimplify;
599 case X86::RELEASE_AND32mi: OutMI.setOpcode(X86::AND32mi); goto ReSimplify;
600 case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify;
601 case X86::RELEASE_OR8mi: OutMI.setOpcode(X86::OR8mi); goto ReSimplify;
602 case X86::RELEASE_OR32mi: OutMI.setOpcode(X86::OR32mi); goto ReSimplify;
603 case X86::RELEASE_OR64mi32: OutMI.setOpcode(X86::OR64mi32); goto ReSimplify;
604 case X86::RELEASE_XOR8mi: OutMI.setOpcode(X86::XOR8mi); goto ReSimplify;
605 case X86::RELEASE_XOR32mi: OutMI.setOpcode(X86::XOR32mi); goto ReSimplify;
606 case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify;
607 case X86::RELEASE_INC8m: OutMI.setOpcode(X86::INC8m); goto ReSimplify;
608 case X86::RELEASE_INC16m: OutMI.setOpcode(X86::INC16m); goto ReSimplify;
609 case X86::RELEASE_INC32m: OutMI.setOpcode(X86::INC32m); goto ReSimplify;
610 case X86::RELEASE_INC64m: OutMI.setOpcode(X86::INC64m); goto ReSimplify;
611 case X86::RELEASE_DEC8m: OutMI.setOpcode(X86::DEC8m); goto ReSimplify;
612 case X86::RELEASE_DEC16m: OutMI.setOpcode(X86::DEC16m); goto ReSimplify;
613 case X86::RELEASE_DEC32m: OutMI.setOpcode(X86::DEC32m); goto ReSimplify;
614 case X86::RELEASE_DEC64m: OutMI.setOpcode(X86::DEC64m); goto ReSimplify;
615
616 // We don't currently select the correct instruction form for instructions
617 // which have a short %eax, etc. form. Handle this by custom lowering, for
618 // now.
619 //
620 // Note, we are currently not handling the following instructions:
621 // MOV64ao8, MOV64o8a
622 // XCHG16ar, XCHG32ar, XCHG64ar
623 case X86::MOV8mr_NOREX:
624 case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o32a); break;
625 case X86::MOV8rm_NOREX:
626 case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao32); break;
627 case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o32a); break;
628 case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao32); break;
629 case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
630 case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
631
632 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
633 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
634 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
635 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
636 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
637 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
638 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
639 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
640 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
641 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
642 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
643 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
644 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
645 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
646 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
647 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
648 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
649 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
650 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
651 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
652 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
653 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
654 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
655 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
656 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
657 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
658 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
659 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
660 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
661 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
662 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
663 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
664 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
665 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
666 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
667 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
668
669 // Try to shrink some forms of movsx.
670 case X86::MOVSX16rr8:
671 case X86::MOVSX32rr16:
672 case X86::MOVSX64rr32:
673 SimplifyMOVSX(OutMI);
674 break;
675 }
676 }
677
LowerTlsAddr(X86MCInstLower & MCInstLowering,const MachineInstr & MI)678 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
679 const MachineInstr &MI) {
680
681 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
682 MI.getOpcode() == X86::TLS_base_addr64;
683
684 bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
685
686 MCContext &context = OutStreamer.getContext();
687
688 if (needsPadding)
689 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
690
691 MCSymbolRefExpr::VariantKind SRVK;
692 switch (MI.getOpcode()) {
693 case X86::TLS_addr32:
694 case X86::TLS_addr64:
695 SRVK = MCSymbolRefExpr::VK_TLSGD;
696 break;
697 case X86::TLS_base_addr32:
698 SRVK = MCSymbolRefExpr::VK_TLSLDM;
699 break;
700 case X86::TLS_base_addr64:
701 SRVK = MCSymbolRefExpr::VK_TLSLD;
702 break;
703 default:
704 llvm_unreachable("unexpected opcode");
705 }
706
707 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
708 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context);
709
710 MCInst LEA;
711 if (is64Bits) {
712 LEA.setOpcode(X86::LEA64r);
713 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
714 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
715 LEA.addOperand(MCOperand::CreateImm(1)); // scale
716 LEA.addOperand(MCOperand::CreateReg(0)); // index
717 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
718 LEA.addOperand(MCOperand::CreateReg(0)); // seg
719 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
720 LEA.setOpcode(X86::LEA32r);
721 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
722 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
723 LEA.addOperand(MCOperand::CreateImm(1)); // scale
724 LEA.addOperand(MCOperand::CreateReg(0)); // index
725 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
726 LEA.addOperand(MCOperand::CreateReg(0)); // seg
727 } else {
728 LEA.setOpcode(X86::LEA32r);
729 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
730 LEA.addOperand(MCOperand::CreateReg(0)); // base
731 LEA.addOperand(MCOperand::CreateImm(1)); // scale
732 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
733 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
734 LEA.addOperand(MCOperand::CreateReg(0)); // seg
735 }
736 EmitAndCountInstruction(LEA);
737
738 if (needsPadding) {
739 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
740 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
741 EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
742 }
743
744 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
745 MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name);
746 const MCSymbolRefExpr *tlsRef =
747 MCSymbolRefExpr::Create(tlsGetAddr,
748 MCSymbolRefExpr::VK_PLT,
749 context);
750
751 EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
752 : X86::CALLpcrel32)
753 .addExpr(tlsRef));
754 }
755
756 /// \brief Emit the optimal amount of multi-byte nops on X86.
EmitNops(MCStreamer & OS,unsigned NumBytes,bool Is64Bit,const MCSubtargetInfo & STI)757 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) {
758 // This works only for 64bit. For 32bit we have to do additional checking if
759 // the CPU supports multi-byte nops.
760 assert(Is64Bit && "EmitNops only supports X86-64");
761 while (NumBytes) {
762 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
763 Opc = IndexReg = Displacement = SegmentReg = 0;
764 BaseReg = X86::RAX; ScaleVal = 1;
765 switch (NumBytes) {
766 case 0: llvm_unreachable("Zero nops?"); break;
767 case 1: NumBytes -= 1; Opc = X86::NOOP; break;
768 case 2: NumBytes -= 2; Opc = X86::XCHG16ar; break;
769 case 3: NumBytes -= 3; Opc = X86::NOOPL; break;
770 case 4: NumBytes -= 4; Opc = X86::NOOPL; Displacement = 8; break;
771 case 5: NumBytes -= 5; Opc = X86::NOOPL; Displacement = 8;
772 IndexReg = X86::RAX; break;
773 case 6: NumBytes -= 6; Opc = X86::NOOPW; Displacement = 8;
774 IndexReg = X86::RAX; break;
775 case 7: NumBytes -= 7; Opc = X86::NOOPL; Displacement = 512; break;
776 case 8: NumBytes -= 8; Opc = X86::NOOPL; Displacement = 512;
777 IndexReg = X86::RAX; break;
778 case 9: NumBytes -= 9; Opc = X86::NOOPW; Displacement = 512;
779 IndexReg = X86::RAX; break;
780 default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;
781 IndexReg = X86::RAX; SegmentReg = X86::CS; break;
782 }
783
784 unsigned NumPrefixes = std::min(NumBytes, 5U);
785 NumBytes -= NumPrefixes;
786 for (unsigned i = 0; i != NumPrefixes; ++i)
787 OS.EmitBytes("\x66");
788
789 switch (Opc) {
790 default: llvm_unreachable("Unexpected opcode"); break;
791 case X86::NOOP:
792 OS.EmitInstruction(MCInstBuilder(Opc), STI);
793 break;
794 case X86::XCHG16ar:
795 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
796 break;
797 case X86::NOOPL:
798 case X86::NOOPW:
799 OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg)
800 .addImm(ScaleVal).addReg(IndexReg)
801 .addImm(Displacement).addReg(SegmentReg), STI);
802 break;
803 }
804 } // while (NumBytes)
805 }
806
LowerSTATEPOINT(MCStreamer & OS,StackMaps & SM,const MachineInstr & MI,bool Is64Bit,const TargetMachine & TM,const MCSubtargetInfo & STI,X86MCInstLower & MCInstLowering)807 static void LowerSTATEPOINT(MCStreamer &OS, StackMaps &SM,
808 const MachineInstr &MI, bool Is64Bit,
809 const TargetMachine& TM,
810 const MCSubtargetInfo& STI,
811 X86MCInstLower &MCInstLowering) {
812 assert(Is64Bit && "Statepoint currently only supports X86-64");
813
814 // Lower call target and choose correct opcode
815 const MachineOperand &call_target = StatepointOpers(&MI).getCallTarget();
816 MCOperand call_target_mcop;
817 unsigned call_opcode;
818 switch (call_target.getType()) {
819 case MachineOperand::MO_GlobalAddress:
820 case MachineOperand::MO_ExternalSymbol:
821 call_target_mcop = MCInstLowering.LowerSymbolOperand(
822 call_target,
823 MCInstLowering.GetSymbolFromOperand(call_target));
824 call_opcode = X86::CALL64pcrel32;
825 // Currently, we only support relative addressing with statepoints.
826 // Otherwise, we'll need a scratch register to hold the target
827 // address. You'll fail asserts during load & relocation if this
828 // symbol is to far away. (TODO: support non-relative addressing)
829 break;
830 case MachineOperand::MO_Immediate:
831 call_target_mcop = MCOperand::CreateImm(call_target.getImm());
832 call_opcode = X86::CALL64pcrel32;
833 // Currently, we only support relative addressing with statepoints.
834 // Otherwise, we'll need a scratch register to hold the target
835 // immediate. You'll fail asserts during load & relocation if this
836 // address is to far away. (TODO: support non-relative addressing)
837 break;
838 case MachineOperand::MO_Register:
839 call_target_mcop = MCOperand::CreateReg(call_target.getReg());
840 call_opcode = X86::CALL64r;
841 break;
842 default:
843 llvm_unreachable("Unsupported operand type in statepoint call target");
844 break;
845 }
846
847 // Emit call
848 MCInst call_inst;
849 call_inst.setOpcode(call_opcode);
850 call_inst.addOperand(call_target_mcop);
851 OS.EmitInstruction(call_inst, STI);
852
853 // Record our statepoint node in the same section used by STACKMAP
854 // and PATCHPOINT
855 SM.recordStatepoint(MI);
856 }
857
858
859 // Lower a stackmap of the form:
860 // <id>, <shadowBytes>, ...
LowerSTACKMAP(const MachineInstr & MI)861 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
862 SMShadowTracker.emitShadowPadding(OutStreamer, getSubtargetInfo());
863 SM.recordStackMap(MI);
864 unsigned NumShadowBytes = MI.getOperand(1).getImm();
865 SMShadowTracker.reset(NumShadowBytes);
866 }
867
868 // Lower a patchpoint of the form:
869 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
LowerPATCHPOINT(const MachineInstr & MI)870 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI) {
871 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
872
873 SMShadowTracker.emitShadowPadding(OutStreamer, getSubtargetInfo());
874
875 SM.recordPatchPoint(MI);
876
877 PatchPointOpers opers(&MI);
878 unsigned ScratchIdx = opers.getNextScratchIdx();
879 unsigned EncodedBytes = 0;
880 int64_t CallTarget = opers.getMetaOper(PatchPointOpers::TargetPos).getImm();
881 if (CallTarget) {
882 // Emit MOV to materialize the target address and the CALL to target.
883 // This is encoded with 12-13 bytes, depending on which register is used.
884 unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
885 if (X86II::isX86_64ExtendedReg(ScratchReg))
886 EncodedBytes = 13;
887 else
888 EncodedBytes = 12;
889 EmitAndCountInstruction(MCInstBuilder(X86::MOV64ri).addReg(ScratchReg)
890 .addImm(CallTarget));
891 EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
892 }
893 // Emit padding.
894 unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
895 assert(NumBytes >= EncodedBytes &&
896 "Patchpoint can't request size less than the length of a call.");
897
898 EmitNops(OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
899 getSubtargetInfo());
900 }
901
902 // Returns instruction preceding MBBI in MachineFunction.
903 // If MBBI is the first instruction of the first basic block, returns null.
904 static MachineBasicBlock::const_iterator
PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI)905 PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) {
906 const MachineBasicBlock *MBB = MBBI->getParent();
907 while (MBBI == MBB->begin()) {
908 if (MBB == MBB->getParent()->begin())
909 return nullptr;
910 MBB = MBB->getPrevNode();
911 MBBI = MBB->end();
912 }
913 return --MBBI;
914 }
915
getConstantFromPool(const MachineInstr & MI,const MachineOperand & Op)916 static const Constant *getConstantFromPool(const MachineInstr &MI,
917 const MachineOperand &Op) {
918 if (!Op.isCPI())
919 return nullptr;
920
921 ArrayRef<MachineConstantPoolEntry> Constants =
922 MI.getParent()->getParent()->getConstantPool()->getConstants();
923 const MachineConstantPoolEntry &ConstantEntry =
924 Constants[Op.getIndex()];
925
926 // Bail if this is a machine constant pool entry, we won't be able to dig out
927 // anything useful.
928 if (ConstantEntry.isMachineConstantPoolEntry())
929 return nullptr;
930
931 auto *C = dyn_cast<Constant>(ConstantEntry.Val.ConstVal);
932 assert((!C || ConstantEntry.getType() == C->getType()) &&
933 "Expected a constant of the same type!");
934 return C;
935 }
936
getShuffleComment(const MachineOperand & DstOp,const MachineOperand & SrcOp,ArrayRef<int> Mask)937 static std::string getShuffleComment(const MachineOperand &DstOp,
938 const MachineOperand &SrcOp,
939 ArrayRef<int> Mask) {
940 std::string Comment;
941
942 // Compute the name for a register. This is really goofy because we have
943 // multiple instruction printers that could (in theory) use different
944 // names. Fortunately most people use the ATT style (outside of Windows)
945 // and they actually agree on register naming here. Ultimately, this is
946 // a comment, and so its OK if it isn't perfect.
947 auto GetRegisterName = [](unsigned RegNum) -> StringRef {
948 return X86ATTInstPrinter::getRegisterName(RegNum);
949 };
950
951 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
952 StringRef SrcName = SrcOp.isReg() ? GetRegisterName(SrcOp.getReg()) : "mem";
953
954 raw_string_ostream CS(Comment);
955 CS << DstName << " = ";
956 bool NeedComma = false;
957 bool InSrc = false;
958 for (int M : Mask) {
959 // Wrap up any prior entry...
960 if (M == SM_SentinelZero && InSrc) {
961 InSrc = false;
962 CS << "]";
963 }
964 if (NeedComma)
965 CS << ",";
966 else
967 NeedComma = true;
968
969 // Print this shuffle...
970 if (M == SM_SentinelZero) {
971 CS << "zero";
972 } else {
973 if (!InSrc) {
974 InSrc = true;
975 CS << SrcName << "[";
976 }
977 if (M == SM_SentinelUndef)
978 CS << "u";
979 else
980 CS << M;
981 }
982 }
983 if (InSrc)
984 CS << "]";
985 CS.flush();
986
987 return Comment;
988 }
989
EmitInstruction(const MachineInstr * MI)990 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
991 X86MCInstLower MCInstLowering(*MF, *this);
992 const X86RegisterInfo *RI = MF->getSubtarget<X86Subtarget>().getRegisterInfo();
993
994 switch (MI->getOpcode()) {
995 case TargetOpcode::DBG_VALUE:
996 llvm_unreachable("Should be handled target independently");
997
998 // Emit nothing here but a comment if we can.
999 case X86::Int_MemBarrier:
1000 OutStreamer.emitRawComment("MEMBARRIER");
1001 return;
1002
1003
1004 case X86::EH_RETURN:
1005 case X86::EH_RETURN64: {
1006 // Lower these as normal, but add some comments.
1007 unsigned Reg = MI->getOperand(0).getReg();
1008 OutStreamer.AddComment(StringRef("eh_return, addr: %") +
1009 X86ATTInstPrinter::getRegisterName(Reg));
1010 break;
1011 }
1012 case X86::TAILJMPr:
1013 case X86::TAILJMPm:
1014 case X86::TAILJMPd:
1015 case X86::TAILJMPr64:
1016 case X86::TAILJMPm64:
1017 case X86::TAILJMPd64:
1018 case X86::TAILJMPr64_REX:
1019 case X86::TAILJMPm64_REX:
1020 case X86::TAILJMPd64_REX:
1021 // Lower these as normal, but add some comments.
1022 OutStreamer.AddComment("TAILCALL");
1023 break;
1024
1025 case X86::TLS_addr32:
1026 case X86::TLS_addr64:
1027 case X86::TLS_base_addr32:
1028 case X86::TLS_base_addr64:
1029 return LowerTlsAddr(MCInstLowering, *MI);
1030
1031 case X86::MOVPC32r: {
1032 // This is a pseudo op for a two instruction sequence with a label, which
1033 // looks like:
1034 // call "L1$pb"
1035 // "L1$pb":
1036 // popl %esi
1037
1038 // Emit the call.
1039 MCSymbol *PICBase = MF->getPICBaseSymbol();
1040 // FIXME: We would like an efficient form for this, so we don't have to do a
1041 // lot of extra uniquing.
1042 EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32)
1043 .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
1044
1045 // Emit the label.
1046 OutStreamer.EmitLabel(PICBase);
1047
1048 // popl $reg
1049 EmitAndCountInstruction(MCInstBuilder(X86::POP32r)
1050 .addReg(MI->getOperand(0).getReg()));
1051 return;
1052 }
1053
1054 case X86::ADD32ri: {
1055 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
1056 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
1057 break;
1058
1059 // Okay, we have something like:
1060 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
1061
1062 // For this, we want to print something like:
1063 // MYGLOBAL + (. - PICBASE)
1064 // However, we can't generate a ".", so just emit a new label here and refer
1065 // to it.
1066 MCSymbol *DotSym = OutContext.CreateTempSymbol();
1067 OutStreamer.EmitLabel(DotSym);
1068
1069 // Now that we have emitted the label, lower the complex operand expression.
1070 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
1071
1072 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
1073 const MCExpr *PICBase =
1074 MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext);
1075 DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
1076
1077 DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
1078 DotExpr, OutContext);
1079
1080 EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
1081 .addReg(MI->getOperand(0).getReg())
1082 .addReg(MI->getOperand(1).getReg())
1083 .addExpr(DotExpr));
1084 return;
1085 }
1086 case TargetOpcode::STATEPOINT:
1087 return LowerSTATEPOINT(OutStreamer, SM, *MI, Subtarget->is64Bit(), TM,
1088 getSubtargetInfo(), MCInstLowering);
1089
1090 case TargetOpcode::STACKMAP:
1091 return LowerSTACKMAP(*MI);
1092
1093 case TargetOpcode::PATCHPOINT:
1094 return LowerPATCHPOINT(*MI);
1095
1096 case X86::MORESTACK_RET:
1097 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1098 return;
1099
1100 case X86::MORESTACK_RET_RESTORE_R10:
1101 // Return, then restore R10.
1102 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1103 EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr)
1104 .addReg(X86::R10)
1105 .addReg(X86::RAX));
1106 return;
1107
1108 case X86::SEH_PushReg:
1109 OutStreamer.EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm()));
1110 return;
1111
1112 case X86::SEH_SaveReg:
1113 OutStreamer.EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1114 MI->getOperand(1).getImm());
1115 return;
1116
1117 case X86::SEH_SaveXMM:
1118 OutStreamer.EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1119 MI->getOperand(1).getImm());
1120 return;
1121
1122 case X86::SEH_StackAlloc:
1123 OutStreamer.EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1124 return;
1125
1126 case X86::SEH_SetFrame:
1127 OutStreamer.EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1128 MI->getOperand(1).getImm());
1129 return;
1130
1131 case X86::SEH_PushFrame:
1132 OutStreamer.EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1133 return;
1134
1135 case X86::SEH_EndPrologue:
1136 OutStreamer.EmitWinCFIEndProlog();
1137 return;
1138
1139 case X86::SEH_Epilogue: {
1140 MachineBasicBlock::const_iterator MBBI(MI);
1141 // Check if preceded by a call and emit nop if so.
1142 for (MBBI = PrevCrossBBInst(MBBI); MBBI; MBBI = PrevCrossBBInst(MBBI)) {
1143 // Conservatively assume that pseudo instructions don't emit code and keep
1144 // looking for a call. We may emit an unnecessary nop in some cases.
1145 if (!MBBI->isPseudo()) {
1146 if (MBBI->isCall())
1147 EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
1148 break;
1149 }
1150 }
1151 return;
1152 }
1153
1154 // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1155 // a constant shuffle mask. We won't be able to do this at the MC layer
1156 // because the mask isn't an immediate.
1157 case X86::PSHUFBrm:
1158 case X86::VPSHUFBrm:
1159 case X86::VPSHUFBYrm: {
1160 if (!OutStreamer.isVerboseAsm())
1161 break;
1162 assert(MI->getNumOperands() > 5 &&
1163 "We should always have at least 5 operands!");
1164 const MachineOperand &DstOp = MI->getOperand(0);
1165 const MachineOperand &SrcOp = MI->getOperand(1);
1166 const MachineOperand &MaskOp = MI->getOperand(5);
1167
1168 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1169 SmallVector<int, 16> Mask;
1170 DecodePSHUFBMask(C, Mask);
1171 if (!Mask.empty())
1172 OutStreamer.AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1173 }
1174 break;
1175 }
1176 case X86::VPERMILPSrm:
1177 case X86::VPERMILPDrm:
1178 case X86::VPERMILPSYrm:
1179 case X86::VPERMILPDYrm: {
1180 if (!OutStreamer.isVerboseAsm())
1181 break;
1182 assert(MI->getNumOperands() > 5 &&
1183 "We should always have at least 5 operands!");
1184 const MachineOperand &DstOp = MI->getOperand(0);
1185 const MachineOperand &SrcOp = MI->getOperand(1);
1186 const MachineOperand &MaskOp = MI->getOperand(5);
1187
1188 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1189 SmallVector<int, 16> Mask;
1190 DecodeVPERMILPMask(C, Mask);
1191 if (!Mask.empty())
1192 OutStreamer.AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1193 }
1194 break;
1195 }
1196
1197 // For loads from a constant pool to a vector register, print the constant
1198 // loaded.
1199 case X86::MOVAPDrm:
1200 case X86::VMOVAPDrm:
1201 case X86::VMOVAPDYrm:
1202 case X86::MOVUPDrm:
1203 case X86::VMOVUPDrm:
1204 case X86::VMOVUPDYrm:
1205 case X86::MOVAPSrm:
1206 case X86::VMOVAPSrm:
1207 case X86::VMOVAPSYrm:
1208 case X86::MOVUPSrm:
1209 case X86::VMOVUPSrm:
1210 case X86::VMOVUPSYrm:
1211 case X86::MOVDQArm:
1212 case X86::VMOVDQArm:
1213 case X86::VMOVDQAYrm:
1214 case X86::MOVDQUrm:
1215 case X86::VMOVDQUrm:
1216 case X86::VMOVDQUYrm:
1217 if (!OutStreamer.isVerboseAsm())
1218 break;
1219 if (MI->getNumOperands() > 4)
1220 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
1221 std::string Comment;
1222 raw_string_ostream CS(Comment);
1223 const MachineOperand &DstOp = MI->getOperand(0);
1224 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
1225 if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
1226 CS << "[";
1227 for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements; ++i) {
1228 if (i != 0)
1229 CS << ",";
1230 if (CDS->getElementType()->isIntegerTy())
1231 CS << CDS->getElementAsInteger(i);
1232 else if (CDS->getElementType()->isFloatTy())
1233 CS << CDS->getElementAsFloat(i);
1234 else if (CDS->getElementType()->isDoubleTy())
1235 CS << CDS->getElementAsDouble(i);
1236 else
1237 CS << "?";
1238 }
1239 CS << "]";
1240 OutStreamer.AddComment(CS.str());
1241 } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
1242 CS << "<";
1243 for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands; ++i) {
1244 if (i != 0)
1245 CS << ",";
1246 Constant *COp = CV->getOperand(i);
1247 if (isa<UndefValue>(COp)) {
1248 CS << "u";
1249 } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
1250 CS << CI->getZExtValue();
1251 } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
1252 SmallString<32> Str;
1253 CF->getValueAPF().toString(Str);
1254 CS << Str;
1255 } else {
1256 CS << "?";
1257 }
1258 }
1259 CS << ">";
1260 OutStreamer.AddComment(CS.str());
1261 }
1262 }
1263 break;
1264 }
1265
1266 MCInst TmpInst;
1267 MCInstLowering.Lower(MI, TmpInst);
1268
1269 // Stackmap shadows cannot include branch targets, so we can count the bytes
1270 // in a call towards the shadow, but must ensure that the no thread returns
1271 // in to the stackmap shadow. The only way to achieve this is if the call
1272 // is at the end of the shadow.
1273 if (MI->isCall()) {
1274 // Count then size of the call towards the shadow
1275 SMShadowTracker.count(TmpInst, getSubtargetInfo());
1276 // Then flush the shadow so that we fill with nops before the call, not
1277 // after it.
1278 SMShadowTracker.emitShadowPadding(OutStreamer, getSubtargetInfo());
1279 // Then emit the call
1280 OutStreamer.EmitInstruction(TmpInst, getSubtargetInfo());
1281 return;
1282 }
1283
1284 EmitAndCountInstruction(TmpInst);
1285 }
1286