1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include "r600_hw_context_priv.h"
27 #include "evergreend.h"
28 #include "util/u_memory.h"
29
30 static const struct r600_reg evergreen_config_reg_list[] = {
31 {R_008958_VGT_PRIMITIVE_TYPE, 0},
32 };
33
34
35 static const struct r600_reg cayman_config_reg_list[] = {
36 {R_008958_VGT_PRIMITIVE_TYPE, 0, 0},
37 {R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
38 {R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
39 };
40
41 static const struct r600_reg evergreen_ctl_const_list[] = {
42 {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
43 };
44
45 static const struct r600_reg evergreen_context_reg_list[] = {
46 {R_028008_DB_DEPTH_VIEW, 0, 0},
47 {R_028010_DB_RENDER_OVERRIDE2, 0, 0},
48 {GROUP_FORCE_NEW_BLOCK, 0, 0},
49 {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0},
50 {GROUP_FORCE_NEW_BLOCK, 0, 0},
51 {R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0},
52 {GROUP_FORCE_NEW_BLOCK, 0, 0},
53 {R_028044_DB_STENCIL_INFO, 0, 0},
54 {GROUP_FORCE_NEW_BLOCK, 0, 0},
55 {R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0},
56 {GROUP_FORCE_NEW_BLOCK, 0, 0},
57 {R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0},
58 {GROUP_FORCE_NEW_BLOCK, 0, 0},
59 {R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0},
60 {GROUP_FORCE_NEW_BLOCK, 0, 0},
61 {R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0},
62 {GROUP_FORCE_NEW_BLOCK, 0, 0},
63 {R_028058_DB_DEPTH_SIZE, 0, 0},
64 {R_02805C_DB_DEPTH_SLICE, 0, 0},
65 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
66 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
67 {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
68 {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
69 {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
70 {R_028350_SX_MISC, 0, 0},
71 {GROUP_FORCE_NEW_BLOCK, 0, 0},
72 {R_028408_VGT_INDX_OFFSET, 0, 0},
73 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
74 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
75 {GROUP_FORCE_NEW_BLOCK, 0, 0},
76 {R_028414_CB_BLEND_RED, 0, 0},
77 {R_028418_CB_BLEND_GREEN, 0, 0},
78 {R_02841C_CB_BLEND_BLUE, 0, 0},
79 {R_028420_CB_BLEND_ALPHA, 0, 0},
80 {R_028430_DB_STENCILREFMASK, 0, 0},
81 {R_028434_DB_STENCILREFMASK_BF, 0, 0},
82 {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
83 {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
84 {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
85 {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
86 {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
87 {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
88 {R_0285BC_PA_CL_UCP0_X, 0, 0},
89 {R_0285C0_PA_CL_UCP0_Y, 0, 0},
90 {R_0285C4_PA_CL_UCP0_Z, 0, 0},
91 {R_0285C8_PA_CL_UCP0_W, 0, 0},
92 {R_0285CC_PA_CL_UCP1_X, 0, 0},
93 {R_0285D0_PA_CL_UCP1_Y, 0, 0},
94 {R_0285D4_PA_CL_UCP1_Z, 0, 0},
95 {R_0285D8_PA_CL_UCP1_W, 0, 0},
96 {R_0285DC_PA_CL_UCP2_X, 0, 0},
97 {R_0285E0_PA_CL_UCP2_Y, 0, 0},
98 {R_0285E4_PA_CL_UCP2_Z, 0, 0},
99 {R_0285E8_PA_CL_UCP2_W, 0, 0},
100 {R_0285EC_PA_CL_UCP3_X, 0, 0},
101 {R_0285F0_PA_CL_UCP3_Y, 0, 0},
102 {R_0285F4_PA_CL_UCP3_Z, 0, 0},
103 {R_0285F8_PA_CL_UCP3_W, 0, 0},
104 {R_0285FC_PA_CL_UCP4_X, 0, 0},
105 {R_028600_PA_CL_UCP4_Y, 0, 0},
106 {R_028604_PA_CL_UCP4_Z, 0, 0},
107 {R_028608_PA_CL_UCP4_W, 0, 0},
108 {R_02860C_PA_CL_UCP5_X, 0, 0},
109 {R_028610_PA_CL_UCP5_Y, 0, 0},
110 {R_028614_PA_CL_UCP5_Z, 0, 0},
111 {R_028618_PA_CL_UCP5_W, 0, 0},
112 {GROUP_FORCE_NEW_BLOCK, 0, 0},
113 {R_02861C_SPI_VS_OUT_ID_0, 0, 0},
114 {R_028620_SPI_VS_OUT_ID_1, 0, 0},
115 {R_028624_SPI_VS_OUT_ID_2, 0, 0},
116 {R_028628_SPI_VS_OUT_ID_3, 0, 0},
117 {R_02862C_SPI_VS_OUT_ID_4, 0, 0},
118 {R_028630_SPI_VS_OUT_ID_5, 0, 0},
119 {R_028634_SPI_VS_OUT_ID_6, 0, 0},
120 {R_028638_SPI_VS_OUT_ID_7, 0, 0},
121 {R_02863C_SPI_VS_OUT_ID_8, 0, 0},
122 {R_028640_SPI_VS_OUT_ID_9, 0, 0},
123 {GROUP_FORCE_NEW_BLOCK, 0, 0},
124 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
125 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
126 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
127 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
128 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
129 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
130 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
131 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
132 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
133 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
134 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
135 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
136 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
137 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
138 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
139 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
140 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
141 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
142 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
143 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
144 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
145 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
146 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
147 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
148 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
149 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
150 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
151 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
152 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
153 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
154 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
155 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
156 {GROUP_FORCE_NEW_BLOCK, 0, 0},
157 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
158 {R_0286C8_SPI_THREAD_GROUPING, 0, 0},
159 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
160 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
161 {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
162 {R_0286D8_SPI_INPUT_Z, 0, 0},
163 {R_0286E0_SPI_BARYC_CNTL, 0, 0},
164 {R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0},
165 {R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0},
166 {R_028780_CB_BLEND0_CONTROL, 0, 0},
167 {R_028784_CB_BLEND1_CONTROL, 0, 0},
168 {R_028788_CB_BLEND2_CONTROL, 0, 0},
169 {R_02878C_CB_BLEND3_CONTROL, 0, 0},
170 {R_028790_CB_BLEND4_CONTROL, 0, 0},
171 {R_028794_CB_BLEND5_CONTROL, 0, 0},
172 {R_028798_CB_BLEND6_CONTROL, 0, 0},
173 {R_02879C_CB_BLEND7_CONTROL, 0, 0},
174 {R_028800_DB_DEPTH_CONTROL, 0, 0},
175 {R_02880C_DB_SHADER_CONTROL, 0, 0},
176 {R_028808_CB_COLOR_CONTROL, 0, 0},
177 {R_028810_PA_CL_CLIP_CNTL, 0, 0},
178 {R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
179 {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
180 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
181 {R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
182 {R_02884C_SQ_PGM_EXPORTS_PS, 0, 0},
183 {R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
184 {R_028860_SQ_PGM_RESOURCES_VS, 0, 0},
185 {R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0},
186 {R_0288EC_SQ_LDS_ALLOC_PS, 0, 0},
187 {R_028A00_PA_SU_POINT_SIZE, 0, 0},
188 {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
189 {R_028A08_PA_SU_LINE_CNTL, 0, 0},
190 {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
191 {R_028A48_PA_SC_MODE_CNTL_0, 0, 0},
192 {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
193 {R_028ABC_DB_HTILE_SURFACE, 0, 0},
194 {R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
195 {R_028B70_DB_ALPHA_TO_MASK, 0, 0},
196 {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
197 {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
198 {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0},
199 {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
200 {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
201 {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
202 {R_028C00_PA_SC_LINE_CNTL, 0, 0},
203 {R_028C04_PA_SC_AA_CONFIG, 0, 0},
204 {R_028C08_PA_SU_VTX_CNTL, 0, 0},
205 {GROUP_FORCE_NEW_BLOCK, 0, 0},
206 {R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, 0, 0},
207 {R_028C20_PA_SC_AA_SAMPLE_LOCS_1, 0, 0},
208 {R_028C24_PA_SC_AA_SAMPLE_LOCS_2, 0, 0},
209 {R_028C28_PA_SC_AA_SAMPLE_LOCS_3, 0, 0},
210 {R_028C2C_PA_SC_AA_SAMPLE_LOCS_4, 0, 0},
211 {R_028C30_PA_SC_AA_SAMPLE_LOCS_5, 0, 0},
212 {R_028C34_PA_SC_AA_SAMPLE_LOCS_6, 0, 0},
213 {R_028C38_PA_SC_AA_SAMPLE_LOCS_7, 0, 0},
214 {GROUP_FORCE_NEW_BLOCK, 0, 0},
215 {R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0},
216 {R_028C64_CB_COLOR0_PITCH, 0, 0},
217 {R_028C68_CB_COLOR0_SLICE, 0, 0},
218 {R_028C6C_CB_COLOR0_VIEW, 0, 0},
219 {R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0},
220 {R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0},
221 {R_028C78_CB_COLOR0_DIM, 0, 0},
222 {R_028C7C_CB_COLOR0_CMASK, REG_FLAG_NEED_BO},
223 {R_028C80_CB_COLOR0_CMASK_SLICE},
224 {R_028C84_CB_COLOR0_FMASK, REG_FLAG_NEED_BO},
225 {R_028C88_CB_COLOR0_FMASK_SLICE},
226 {R_028C8C_CB_COLOR0_CLEAR_WORD0},
227 {R_028C90_CB_COLOR0_CLEAR_WORD1},
228 {R_028C94_CB_COLOR0_CLEAR_WORD2},
229 {R_028C98_CB_COLOR0_CLEAR_WORD3},
230 {GROUP_FORCE_NEW_BLOCK, 0, 0},
231 {R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0},
232 {R_028CA0_CB_COLOR1_PITCH, 0, 0},
233 {R_028CA4_CB_COLOR1_SLICE, 0, 0},
234 {R_028CA8_CB_COLOR1_VIEW, 0, 0},
235 {R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0},
236 {R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0},
237 {R_028CB4_CB_COLOR1_DIM, 0, 0},
238 {R_028CB8_CB_COLOR1_CMASK, REG_FLAG_NEED_BO, 0},
239 {R_028CBC_CB_COLOR1_CMASK_SLICE, 0, 0},
240 {R_028CC0_CB_COLOR1_FMASK, REG_FLAG_NEED_BO, 0},
241 {R_028CC4_CB_COLOR1_FMASK_SLICE, 0, 0},
242 {R_028CC8_CB_COLOR1_CLEAR_WORD0},
243 {R_028CCC_CB_COLOR1_CLEAR_WORD1},
244 {R_028CD0_CB_COLOR1_CLEAR_WORD2},
245 {R_028CD4_CB_COLOR1_CLEAR_WORD3},
246 {GROUP_FORCE_NEW_BLOCK, 0, 0},
247 {R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0},
248 {R_028CDC_CB_COLOR2_PITCH, 0, 0},
249 {R_028CE0_CB_COLOR2_SLICE, 0, 0},
250 {R_028CE4_CB_COLOR2_VIEW, 0, 0},
251 {R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0},
252 {R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0},
253 {R_028CF0_CB_COLOR2_DIM, 0, 0},
254 {R_028CF4_CB_COLOR2_CMASK, REG_FLAG_NEED_BO, 0},
255 {R_028CF8_CB_COLOR2_CMASK_SLICE, 0, 0},
256 {R_028CFC_CB_COLOR2_FMASK, REG_FLAG_NEED_BO, 0},
257 {R_028D00_CB_COLOR2_FMASK_SLICE, 0, 0},
258 {R_028D04_CB_COLOR2_CLEAR_WORD0},
259 {R_028D08_CB_COLOR2_CLEAR_WORD1},
260 {R_028D0C_CB_COLOR2_CLEAR_WORD2},
261 {R_028D10_CB_COLOR2_CLEAR_WORD3},
262 {GROUP_FORCE_NEW_BLOCK, 0, 0},
263 {R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0},
264 {R_028D18_CB_COLOR3_PITCH, 0, 0},
265 {R_028D1C_CB_COLOR3_SLICE, 0, 0},
266 {R_028D20_CB_COLOR3_VIEW, 0, 0},
267 {R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0},
268 {R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0},
269 {R_028D2C_CB_COLOR3_DIM, 0, 0},
270 {R_028D30_CB_COLOR3_CMASK, REG_FLAG_NEED_BO},
271 {R_028D34_CB_COLOR3_CMASK_SLICE},
272 {R_028D38_CB_COLOR3_FMASK, REG_FLAG_NEED_BO},
273 {R_028D3C_CB_COLOR3_FMASK_SLICE},
274 {R_028D40_CB_COLOR3_CLEAR_WORD0},
275 {R_028D44_CB_COLOR3_CLEAR_WORD1},
276 {R_028D48_CB_COLOR3_CLEAR_WORD2},
277 {R_028D4C_CB_COLOR3_CLEAR_WORD3},
278 {GROUP_FORCE_NEW_BLOCK, 0, 0},
279 {R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0},
280 {R_028D54_CB_COLOR4_PITCH, 0, 0},
281 {R_028D58_CB_COLOR4_SLICE, 0, 0},
282 {R_028D5C_CB_COLOR4_VIEW, 0, 0},
283 {R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0},
284 {R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0},
285 {R_028D68_CB_COLOR4_DIM, 0, 0},
286 {R_028D6C_CB_COLOR4_CMASK, REG_FLAG_NEED_BO},
287 {R_028D70_CB_COLOR4_CMASK_SLICE},
288 {R_028D74_CB_COLOR4_FMASK, REG_FLAG_NEED_BO},
289 {R_028D78_CB_COLOR4_FMASK_SLICE},
290 {R_028D7C_CB_COLOR4_CLEAR_WORD0},
291 {R_028D80_CB_COLOR4_CLEAR_WORD1},
292 {R_028D84_CB_COLOR4_CLEAR_WORD2},
293 {R_028D88_CB_COLOR4_CLEAR_WORD3},
294 {GROUP_FORCE_NEW_BLOCK, 0, 0},
295 {R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0},
296 {R_028D90_CB_COLOR5_PITCH, 0, 0},
297 {R_028D94_CB_COLOR5_SLICE, 0, 0},
298 {R_028D98_CB_COLOR5_VIEW, 0, 0},
299 {R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0},
300 {R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0},
301 {R_028DA4_CB_COLOR5_DIM, 0, 0},
302 {R_028DA8_CB_COLOR5_CMASK, REG_FLAG_NEED_BO},
303 {R_028DAC_CB_COLOR5_CMASK_SLICE},
304 {R_028DB0_CB_COLOR5_FMASK, REG_FLAG_NEED_BO},
305 {R_028DB4_CB_COLOR5_FMASK_SLICE},
306 {R_028DB8_CB_COLOR5_CLEAR_WORD0},
307 {R_028DBC_CB_COLOR5_CLEAR_WORD1},
308 {R_028DC0_CB_COLOR5_CLEAR_WORD2},
309 {R_028DC4_CB_COLOR5_CLEAR_WORD3},
310 {GROUP_FORCE_NEW_BLOCK, 0, 0},
311 {R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0},
312 {R_028DCC_CB_COLOR6_PITCH, 0, 0},
313 {R_028DD0_CB_COLOR6_SLICE, 0, 0},
314 {R_028DD4_CB_COLOR6_VIEW, 0, 0},
315 {R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0},
316 {R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0},
317 {R_028DE0_CB_COLOR6_DIM, 0, 0},
318 {R_028DE4_CB_COLOR6_CMASK, REG_FLAG_NEED_BO},
319 {R_028DE8_CB_COLOR6_CMASK_SLICE},
320 {R_028DEC_CB_COLOR6_FMASK, REG_FLAG_NEED_BO},
321 {R_028DF0_CB_COLOR6_FMASK_SLICE},
322 {R_028DF4_CB_COLOR6_CLEAR_WORD0},
323 {R_028DF8_CB_COLOR6_CLEAR_WORD1},
324 {R_028DFC_CB_COLOR6_CLEAR_WORD2},
325 {R_028E00_CB_COLOR6_CLEAR_WORD3},
326 {GROUP_FORCE_NEW_BLOCK, 0, 0},
327 {R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0},
328 {R_028E08_CB_COLOR7_PITCH, 0, 0},
329 {R_028E0C_CB_COLOR7_SLICE, 0, 0},
330 {R_028E10_CB_COLOR7_VIEW, 0, 0},
331 {R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0},
332 {R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0},
333 {R_028E1C_CB_COLOR7_DIM, 0, 0},
334 {R_028E20_CB_COLOR7_CMASK, REG_FLAG_NEED_BO},
335 {R_028E24_CB_COLOR7_CMASK_SLICE},
336 {R_028E28_CB_COLOR7_FMASK, REG_FLAG_NEED_BO},
337 {R_028E2C_CB_COLOR7_FMASK_SLICE},
338 {R_028E30_CB_COLOR7_CLEAR_WORD0},
339 {R_028E34_CB_COLOR7_CLEAR_WORD1},
340 {R_028E38_CB_COLOR7_CLEAR_WORD2},
341 {R_028E3C_CB_COLOR7_CLEAR_WORD3},
342 {GROUP_FORCE_NEW_BLOCK, 0, 0},
343 {R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0},
344 {R_028E44_CB_COLOR8_PITCH, 0, 0},
345 {R_028E48_CB_COLOR8_SLICE, 0, 0},
346 {R_028E4C_CB_COLOR8_VIEW, 0, 0},
347 {R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0},
348 {R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0},
349 {R_028E58_CB_COLOR8_DIM, 0, 0},
350 {GROUP_FORCE_NEW_BLOCK, 0, 0},
351 {R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0},
352 {R_028E60_CB_COLOR9_PITCH, 0, 0},
353 {R_028E64_CB_COLOR9_SLICE, 0, 0},
354 {R_028E68_CB_COLOR9_VIEW, 0, 0},
355 {R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0},
356 {R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0},
357 {R_028E74_CB_COLOR9_DIM, 0, 0},
358 {GROUP_FORCE_NEW_BLOCK, 0, 0},
359 {R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0},
360 {R_028E7C_CB_COLOR10_PITCH, 0, 0},
361 {R_028E80_CB_COLOR10_SLICE, 0, 0},
362 {R_028E84_CB_COLOR10_VIEW, 0, 0},
363 {R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0},
364 {R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0},
365 {R_028E90_CB_COLOR10_DIM, 0, 0},
366 {GROUP_FORCE_NEW_BLOCK, 0, 0},
367 {R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0},
368 {R_028E98_CB_COLOR11_PITCH, 0, 0},
369 {R_028E9C_CB_COLOR11_SLICE, 0, 0},
370 {R_028EA0_CB_COLOR11_VIEW, 0, 0},
371 {R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0},
372 {R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0},
373 {R_028EAC_CB_COLOR11_DIM, 0, 0},
374 };
375
376 static const struct r600_reg cayman_context_reg_list[] = {
377 {R_028008_DB_DEPTH_VIEW, 0, 0},
378 {R_028010_DB_RENDER_OVERRIDE2, 0, 0},
379 {GROUP_FORCE_NEW_BLOCK, 0, 0},
380 {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0},
381 {GROUP_FORCE_NEW_BLOCK, 0, 0},
382 {R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0},
383 {GROUP_FORCE_NEW_BLOCK, 0, 0},
384 {R_028044_DB_STENCIL_INFO, 0, 0},
385 {GROUP_FORCE_NEW_BLOCK, 0, 0},
386 {R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0},
387 {GROUP_FORCE_NEW_BLOCK, 0, 0},
388 {R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0},
389 {GROUP_FORCE_NEW_BLOCK, 0, 0},
390 {R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0},
391 {GROUP_FORCE_NEW_BLOCK, 0, 0},
392 {R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0},
393 {GROUP_FORCE_NEW_BLOCK, 0, 0},
394 {R_028058_DB_DEPTH_SIZE, 0, 0},
395 {R_02805C_DB_DEPTH_SLICE, 0, 0},
396 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
397 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
398 {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
399 {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
400 {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
401 {R_028350_SX_MISC, 0, 0},
402 {GROUP_FORCE_NEW_BLOCK, 0, 0},
403 {R_028408_VGT_INDX_OFFSET, 0, 0},
404 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
405 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
406 {GROUP_FORCE_NEW_BLOCK, 0, 0},
407 {R_028414_CB_BLEND_RED, 0, 0},
408 {R_028418_CB_BLEND_GREEN, 0, 0},
409 {R_02841C_CB_BLEND_BLUE, 0, 0},
410 {R_028420_CB_BLEND_ALPHA, 0, 0},
411 {R_028430_DB_STENCILREFMASK, 0, 0},
412 {R_028434_DB_STENCILREFMASK_BF, 0, 0},
413 {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
414 {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
415 {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
416 {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
417 {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
418 {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
419 {R_0285BC_PA_CL_UCP0_X, 0, 0},
420 {R_0285C0_PA_CL_UCP0_Y, 0, 0},
421 {R_0285C4_PA_CL_UCP0_Z, 0, 0},
422 {R_0285C8_PA_CL_UCP0_W, 0, 0},
423 {R_0285CC_PA_CL_UCP1_X, 0, 0},
424 {R_0285D0_PA_CL_UCP1_Y, 0, 0},
425 {R_0285D4_PA_CL_UCP1_Z, 0, 0},
426 {R_0285D8_PA_CL_UCP1_W, 0, 0},
427 {R_0285DC_PA_CL_UCP2_X, 0, 0},
428 {R_0285E0_PA_CL_UCP2_Y, 0, 0},
429 {R_0285E4_PA_CL_UCP2_Z, 0, 0},
430 {R_0285E8_PA_CL_UCP2_W, 0, 0},
431 {R_0285EC_PA_CL_UCP3_X, 0, 0},
432 {R_0285F0_PA_CL_UCP3_Y, 0, 0},
433 {R_0285F4_PA_CL_UCP3_Z, 0, 0},
434 {R_0285F8_PA_CL_UCP3_W, 0, 0},
435 {R_0285FC_PA_CL_UCP4_X, 0, 0},
436 {R_028600_PA_CL_UCP4_Y, 0, 0},
437 {R_028604_PA_CL_UCP4_Z, 0, 0},
438 {R_028608_PA_CL_UCP4_W, 0, 0},
439 {R_02860C_PA_CL_UCP5_X, 0, 0},
440 {R_028610_PA_CL_UCP5_Y, 0, 0},
441 {R_028614_PA_CL_UCP5_Z, 0, 0},
442 {R_028618_PA_CL_UCP5_W, 0, 0},
443 {R_02861C_SPI_VS_OUT_ID_0, 0, 0},
444 {R_028620_SPI_VS_OUT_ID_1, 0, 0},
445 {R_028624_SPI_VS_OUT_ID_2, 0, 0},
446 {R_028628_SPI_VS_OUT_ID_3, 0, 0},
447 {R_02862C_SPI_VS_OUT_ID_4, 0, 0},
448 {R_028630_SPI_VS_OUT_ID_5, 0, 0},
449 {R_028634_SPI_VS_OUT_ID_6, 0, 0},
450 {R_028638_SPI_VS_OUT_ID_7, 0, 0},
451 {R_02863C_SPI_VS_OUT_ID_8, 0, 0},
452 {R_028640_SPI_VS_OUT_ID_9, 0, 0},
453 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
454 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
455 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
456 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
457 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
458 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
459 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
460 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
461 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
462 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
463 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
464 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
465 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
466 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
467 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
468 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
469 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
470 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
471 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
472 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
473 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
474 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
475 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
476 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
477 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
478 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
479 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
480 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
481 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
482 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
483 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
484 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
485 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
486 {R_0286C8_SPI_THREAD_GROUPING, 0, 0},
487 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
488 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
489 {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
490 {R_0286D8_SPI_INPUT_Z, 0, 0},
491 {R_0286E0_SPI_BARYC_CNTL, 0, 0},
492 {R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0},
493 {R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0},
494 {R_028780_CB_BLEND0_CONTROL, 0, 0},
495 {R_028784_CB_BLEND1_CONTROL, 0, 0},
496 {R_028788_CB_BLEND2_CONTROL, 0, 0},
497 {R_02878C_CB_BLEND3_CONTROL, 0, 0},
498 {R_028790_CB_BLEND4_CONTROL, 0, 0},
499 {R_028794_CB_BLEND5_CONTROL, 0, 0},
500 {R_028798_CB_BLEND6_CONTROL, 0, 0},
501 {R_02879C_CB_BLEND7_CONTROL, 0, 0},
502 {R_028800_DB_DEPTH_CONTROL, 0, 0},
503 {CM_R_028804_DB_EQAA},
504 {R_028808_CB_COLOR_CONTROL, 0, 0},
505 {R_02880C_DB_SHADER_CONTROL, 0, 0},
506 {R_028810_PA_CL_CLIP_CNTL, 0, 0},
507 {R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
508 {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
509 {R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0},
510 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
511 {R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
512 {R_02884C_SQ_PGM_EXPORTS_PS, 0, 0},
513 {R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
514 {R_028860_SQ_PGM_RESOURCES_VS, 0, 0},
515 {R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0},
516 {R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0},
517 {R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0},
518 {R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0},
519 {R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0},
520 {R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0},
521 {R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0},
522 {R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0},
523 {R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0},
524 {R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0},
525 {R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0},
526 {R_028A00_PA_SU_POINT_SIZE, 0, 0},
527 {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
528 {R_028A08_PA_SU_LINE_CNTL, 0, 0},
529 {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
530 {R_028A48_PA_SC_MODE_CNTL_0, 0, 0},
531 {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
532 {R_028ABC_DB_HTILE_SURFACE, 0, 0},
533 {R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
534 {R_028B70_DB_ALPHA_TO_MASK, 0, 0},
535 {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
536 {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
537 {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0},
538 {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
539 {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
540 {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
541 {CM_R_028BDC_PA_SC_LINE_CNTL, 0, 0},
542 {CM_R_028BE0_PA_SC_AA_CONFIG, 0, 0},
543 {CM_R_028BE4_PA_SU_VTX_CNTL, 0, 0},
544 {CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0, 0},
545 {CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, 0, 0},
546 {CM_R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0, 0},
547 {CM_R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0, 0},
548 {CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0, 0},
549 {CM_R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, 0, 0},
550 {CM_R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0, 0},
551 {CM_R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0, 0},
552 {CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0, 0},
553 {CM_R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, 0, 0},
554 {CM_R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0, 0},
555 {CM_R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0, 0},
556 {CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0, 0},
557 {CM_R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, 0, 0},
558 {CM_R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, 0, 0},
559 {CM_R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, 0, 0},
560 {GROUP_FORCE_NEW_BLOCK, 0, 0},
561 {R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0},
562 {R_028C64_CB_COLOR0_PITCH, 0, 0},
563 {R_028C68_CB_COLOR0_SLICE, 0, 0},
564 {R_028C6C_CB_COLOR0_VIEW, 0, 0},
565 {R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0},
566 {R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0},
567 {R_028C78_CB_COLOR0_DIM, 0, 0},
568 {R_028C7C_CB_COLOR0_CMASK, REG_FLAG_NEED_BO},
569 {R_028C80_CB_COLOR0_CMASK_SLICE},
570 {R_028C84_CB_COLOR0_FMASK, REG_FLAG_NEED_BO},
571 {R_028C88_CB_COLOR0_FMASK_SLICE},
572 {R_028C8C_CB_COLOR0_CLEAR_WORD0},
573 {R_028C90_CB_COLOR0_CLEAR_WORD1},
574 {R_028C94_CB_COLOR0_CLEAR_WORD2},
575 {R_028C98_CB_COLOR0_CLEAR_WORD3},
576 {GROUP_FORCE_NEW_BLOCK, 0, 0},
577 {R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0},
578 {R_028CA0_CB_COLOR1_PITCH, 0, 0},
579 {R_028CA4_CB_COLOR1_SLICE, 0, 0},
580 {R_028CA8_CB_COLOR1_VIEW, 0, 0},
581 {R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0},
582 {R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0},
583 {R_028CB4_CB_COLOR1_DIM, 0, 0},
584 {R_028CB8_CB_COLOR1_CMASK, REG_FLAG_NEED_BO, 0},
585 {R_028CBC_CB_COLOR1_CMASK_SLICE, 0, 0},
586 {R_028CC0_CB_COLOR1_FMASK, REG_FLAG_NEED_BO, 0},
587 {R_028CC4_CB_COLOR1_FMASK_SLICE, 0, 0},
588 {R_028CC8_CB_COLOR1_CLEAR_WORD0},
589 {R_028CCC_CB_COLOR1_CLEAR_WORD1},
590 {R_028CD0_CB_COLOR1_CLEAR_WORD2},
591 {R_028CD4_CB_COLOR1_CLEAR_WORD3},
592 {GROUP_FORCE_NEW_BLOCK, 0, 0},
593 {R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0},
594 {R_028CDC_CB_COLOR2_PITCH, 0, 0},
595 {R_028CE0_CB_COLOR2_SLICE, 0, 0},
596 {R_028CE4_CB_COLOR2_VIEW, 0, 0},
597 {R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0},
598 {R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0},
599 {R_028CF0_CB_COLOR2_DIM, 0, 0},
600 {R_028CF4_CB_COLOR2_CMASK, REG_FLAG_NEED_BO, 0},
601 {R_028CF8_CB_COLOR2_CMASK_SLICE, 0, 0},
602 {R_028CFC_CB_COLOR2_FMASK, REG_FLAG_NEED_BO, 0},
603 {R_028D00_CB_COLOR2_FMASK_SLICE, 0, 0},
604 {R_028D04_CB_COLOR2_CLEAR_WORD0},
605 {R_028D08_CB_COLOR2_CLEAR_WORD1},
606 {R_028D0C_CB_COLOR2_CLEAR_WORD2},
607 {R_028D10_CB_COLOR2_CLEAR_WORD3},
608 {GROUP_FORCE_NEW_BLOCK, 0, 0},
609 {R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0},
610 {R_028D18_CB_COLOR3_PITCH, 0, 0},
611 {R_028D1C_CB_COLOR3_SLICE, 0, 0},
612 {R_028D20_CB_COLOR3_VIEW, 0, 0},
613 {R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0},
614 {R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0},
615 {R_028D2C_CB_COLOR3_DIM, 0, 0},
616 {R_028D30_CB_COLOR3_CMASK, REG_FLAG_NEED_BO},
617 {R_028D34_CB_COLOR3_CMASK_SLICE},
618 {R_028D38_CB_COLOR3_FMASK, REG_FLAG_NEED_BO},
619 {R_028D3C_CB_COLOR3_FMASK_SLICE},
620 {R_028D40_CB_COLOR3_CLEAR_WORD0},
621 {R_028D44_CB_COLOR3_CLEAR_WORD1},
622 {R_028D48_CB_COLOR3_CLEAR_WORD2},
623 {R_028D4C_CB_COLOR3_CLEAR_WORD3},
624 {GROUP_FORCE_NEW_BLOCK, 0, 0},
625 {R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0},
626 {R_028D54_CB_COLOR4_PITCH, 0, 0},
627 {R_028D58_CB_COLOR4_SLICE, 0, 0},
628 {R_028D5C_CB_COLOR4_VIEW, 0, 0},
629 {R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0},
630 {R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0},
631 {R_028D68_CB_COLOR4_DIM, 0, 0},
632 {R_028D6C_CB_COLOR4_CMASK, REG_FLAG_NEED_BO},
633 {R_028D70_CB_COLOR4_CMASK_SLICE},
634 {R_028D74_CB_COLOR4_FMASK, REG_FLAG_NEED_BO},
635 {R_028D78_CB_COLOR4_FMASK_SLICE},
636 {R_028D7C_CB_COLOR4_CLEAR_WORD0},
637 {R_028D80_CB_COLOR4_CLEAR_WORD1},
638 {R_028D84_CB_COLOR4_CLEAR_WORD2},
639 {R_028D88_CB_COLOR4_CLEAR_WORD3},
640 {GROUP_FORCE_NEW_BLOCK, 0, 0},
641 {R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0},
642 {R_028D90_CB_COLOR5_PITCH, 0, 0},
643 {R_028D94_CB_COLOR5_SLICE, 0, 0},
644 {R_028D98_CB_COLOR5_VIEW, 0, 0},
645 {R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0},
646 {R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0},
647 {R_028DA4_CB_COLOR5_DIM, 0, 0},
648 {R_028DA8_CB_COLOR5_CMASK, REG_FLAG_NEED_BO},
649 {R_028DAC_CB_COLOR5_CMASK_SLICE},
650 {R_028DB0_CB_COLOR5_FMASK, REG_FLAG_NEED_BO},
651 {R_028DB4_CB_COLOR5_FMASK_SLICE},
652 {R_028DB8_CB_COLOR5_CLEAR_WORD0},
653 {R_028DBC_CB_COLOR5_CLEAR_WORD1},
654 {R_028DC0_CB_COLOR5_CLEAR_WORD2},
655 {R_028DC4_CB_COLOR5_CLEAR_WORD3},
656 {GROUP_FORCE_NEW_BLOCK, 0, 0},
657 {R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0},
658 {R_028DCC_CB_COLOR6_PITCH, 0, 0},
659 {R_028DD0_CB_COLOR6_SLICE, 0, 0},
660 {R_028DD4_CB_COLOR6_VIEW, 0, 0},
661 {R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0},
662 {R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0},
663 {R_028DE0_CB_COLOR6_DIM, 0, 0},
664 {R_028DE4_CB_COLOR6_CMASK, REG_FLAG_NEED_BO},
665 {R_028DE8_CB_COLOR6_CMASK_SLICE},
666 {R_028DEC_CB_COLOR6_FMASK, REG_FLAG_NEED_BO},
667 {R_028DF0_CB_COLOR6_FMASK_SLICE},
668 {R_028DF4_CB_COLOR6_CLEAR_WORD0},
669 {R_028DF8_CB_COLOR6_CLEAR_WORD1},
670 {R_028DFC_CB_COLOR6_CLEAR_WORD2},
671 {R_028E00_CB_COLOR6_CLEAR_WORD3},
672 {GROUP_FORCE_NEW_BLOCK, 0, 0},
673 {R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0},
674 {R_028E08_CB_COLOR7_PITCH, 0, 0},
675 {R_028E0C_CB_COLOR7_SLICE, 0, 0},
676 {R_028E10_CB_COLOR7_VIEW, 0, 0},
677 {R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0},
678 {R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0},
679 {R_028E1C_CB_COLOR7_DIM, 0, 0},
680 {R_028E20_CB_COLOR7_CMASK, REG_FLAG_NEED_BO},
681 {R_028E24_CB_COLOR7_CMASK_SLICE},
682 {R_028E28_CB_COLOR7_FMASK, REG_FLAG_NEED_BO},
683 {R_028E2C_CB_COLOR7_FMASK_SLICE},
684 {R_028E30_CB_COLOR7_CLEAR_WORD0},
685 {R_028E34_CB_COLOR7_CLEAR_WORD1},
686 {R_028E38_CB_COLOR7_CLEAR_WORD2},
687 {R_028E3C_CB_COLOR7_CLEAR_WORD3},
688 {GROUP_FORCE_NEW_BLOCK, 0, 0},
689 {R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0},
690 {R_028E44_CB_COLOR8_PITCH, 0, 0},
691 {R_028E48_CB_COLOR8_SLICE, 0, 0},
692 {R_028E4C_CB_COLOR8_VIEW, 0, 0},
693 {R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0},
694 {R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0},
695 {R_028E58_CB_COLOR8_DIM, 0, 0},
696 {GROUP_FORCE_NEW_BLOCK, 0, 0},
697 {R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0},
698 {R_028E60_CB_COLOR9_PITCH, 0, 0},
699 {R_028E64_CB_COLOR9_SLICE, 0, 0},
700 {R_028E68_CB_COLOR9_VIEW, 0, 0},
701 {R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0},
702 {R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0},
703 {R_028E74_CB_COLOR9_DIM, 0, 0},
704 {GROUP_FORCE_NEW_BLOCK, 0, 0},
705 {R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0},
706 {R_028E7C_CB_COLOR10_PITCH, 0, 0},
707 {R_028E80_CB_COLOR10_SLICE, 0, 0},
708 {R_028E84_CB_COLOR10_VIEW, 0, 0},
709 {R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0},
710 {R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0},
711 {R_028E90_CB_COLOR10_DIM, 0, 0},
712 {GROUP_FORCE_NEW_BLOCK, 0, 0},
713 {R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0},
714 {R_028E98_CB_COLOR11_PITCH, 0, 0},
715 {R_028E9C_CB_COLOR11_SLICE, 0, 0},
716 {R_028EA0_CB_COLOR11_VIEW, 0, 0},
717 {R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0},
718 {R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0},
719 {R_028EAC_CB_COLOR11_DIM, 0, 0},
720 };
721
evergreen_loop_const_init(struct r600_context * ctx,uint32_t offset)722 static int evergreen_loop_const_init(struct r600_context *ctx, uint32_t offset)
723 {
724 unsigned nreg = 32;
725 struct r600_reg r600_loop_consts[32];
726 int i;
727
728 for (i = 0; i < nreg; i++) {
729 r600_loop_consts[i].offset = EVERGREEN_LOOP_CONST_OFFSET + ((offset + i) * 4);
730 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
731 r600_loop_consts[i].sbu_flags = 0;
732 }
733 return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, EVERGREEN_LOOP_CONST_OFFSET);
734 }
735
evergreen_context_init(struct r600_context * ctx)736 int evergreen_context_init(struct r600_context *ctx)
737 {
738 int r;
739
740 /* add blocks */
741 if (ctx->family >= CHIP_CAYMAN)
742 r = r600_context_add_block(ctx, cayman_config_reg_list,
743 Elements(cayman_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
744 else
745 r = r600_context_add_block(ctx, evergreen_config_reg_list,
746 Elements(evergreen_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
747 if (r)
748 goto out_err;
749 if (ctx->family >= CHIP_CAYMAN)
750 r = r600_context_add_block(ctx, cayman_context_reg_list,
751 Elements(cayman_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
752 else
753 r = r600_context_add_block(ctx, evergreen_context_reg_list,
754 Elements(evergreen_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
755 if (r)
756 goto out_err;
757 r = r600_context_add_block(ctx, evergreen_ctl_const_list,
758 Elements(evergreen_ctl_const_list), PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET);
759 if (r)
760 goto out_err;
761
762 /* PS loop const */
763 evergreen_loop_const_init(ctx, 0);
764 /* VS loop const */
765 evergreen_loop_const_init(ctx, 32);
766
767 r = r600_setup_block_table(ctx);
768 if (r)
769 goto out_err;
770
771 ctx->max_db = 8;
772 return 0;
773 out_err:
774 r600_context_fini(ctx);
775 return r;
776 }
777
evergreen_flush_vgt_streamout(struct r600_context * ctx)778 void evergreen_flush_vgt_streamout(struct r600_context *ctx)
779 {
780 struct radeon_winsys_cs *cs = ctx->cs;
781
782 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0);
783 cs->buf[cs->cdw++] = (R_0084FC_CP_STRMOUT_CNTL - EVERGREEN_CONFIG_REG_OFFSET) >> 2;
784 cs->buf[cs->cdw++] = 0;
785
786 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
787 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
788
789 cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
790 cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
791 cs->buf[cs->cdw++] = R_0084FC_CP_STRMOUT_CNTL >> 2; /* register */
792 cs->buf[cs->cdw++] = 0;
793 cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* reference value */
794 cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* mask */
795 cs->buf[cs->cdw++] = 4; /* poll interval */
796 }
797
evergreen_set_streamout_enable(struct r600_context * ctx,unsigned buffer_enable_bit)798 void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
799 {
800 struct radeon_winsys_cs *cs = ctx->cs;
801
802 if (buffer_enable_bit) {
803 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
804 cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
805 cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(1);
806
807 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
808 cs->buf[cs->cdw++] = (R_028B98_VGT_STRMOUT_BUFFER_CONFIG - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
809 cs->buf[cs->cdw++] = S_028B98_STREAM_0_BUFFER_EN(buffer_enable_bit);
810 } else {
811 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
812 cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
813 cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(0);
814 }
815 }
816