1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "HexagonRegisterInfo.h"
16 #include "Hexagon.h"
17 #include "HexagonMachineFunctionInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "HexagonTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/MC/MachineLocation.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37
38 using namespace llvm;
39
HexagonRegisterInfo()40 HexagonRegisterInfo::HexagonRegisterInfo()
41 : HexagonGenRegisterInfo(Hexagon::R31) {}
42
43 const MCPhysReg *
getCalleeSavedRegs(const MachineFunction * MF) const44 HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
45 static const MCPhysReg CalleeSavedRegsV3[] = {
46 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
47 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
48 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
49 };
50
51 switch (MF->getSubtarget<HexagonSubtarget>().getHexagonArchVersion()) {
52 case HexagonSubtarget::V4:
53 case HexagonSubtarget::V5:
54 return CalleeSavedRegsV3;
55 }
56 llvm_unreachable("Callee saved registers requested for unknown architecture "
57 "version");
58 }
59
getReservedRegs(const MachineFunction & MF) const60 BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
61 const {
62 BitVector Reserved(getNumRegs());
63 Reserved.set(HEXAGON_RESERVED_REG_1);
64 Reserved.set(HEXAGON_RESERVED_REG_2);
65 Reserved.set(Hexagon::R29);
66 Reserved.set(Hexagon::R30);
67 Reserved.set(Hexagon::R31);
68 Reserved.set(Hexagon::D14);
69 Reserved.set(Hexagon::D15);
70 Reserved.set(Hexagon::LC0);
71 Reserved.set(Hexagon::LC1);
72 Reserved.set(Hexagon::SA0);
73 Reserved.set(Hexagon::SA1);
74 return Reserved;
75 }
76
77
78 const TargetRegisterClass* const*
getCalleeSavedRegClasses(const MachineFunction * MF) const79 HexagonRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
80 static const TargetRegisterClass * const CalleeSavedRegClassesV3[] = {
81 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
82 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
83 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
84 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
85 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
86 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
87 };
88
89 switch (MF->getSubtarget<HexagonSubtarget>().getHexagonArchVersion()) {
90 case HexagonSubtarget::V4:
91 case HexagonSubtarget::V5:
92 return CalleeSavedRegClassesV3;
93 }
94 llvm_unreachable("Callee saved register classes requested for unknown "
95 "architecture version");
96 }
97
eliminateFrameIndex(MachineBasicBlock::iterator II,int SPAdj,unsigned FIOperandNum,RegScavenger * RS) const98 void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
99 int SPAdj, unsigned FIOperandNum,
100 RegScavenger *RS) const {
101 //
102 // Hexagon_TODO: Do we need to enforce this for Hexagon?
103 assert(SPAdj == 0 && "Unexpected");
104
105 MachineInstr &MI = *II;
106 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
107
108 // Addressable stack objects are accessed using neg. offsets from %fp.
109 MachineFunction &MF = *MI.getParent()->getParent();
110 const HexagonInstrInfo &TII =
111 *static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
112 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
113 MachineFrameInfo &MFI = *MF.getFrameInfo();
114
115 unsigned FrameReg = getFrameRegister(MF);
116 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
117 if (!TFI->hasFP(MF)) {
118 // We will not reserve space on the stack for the lr and fp registers.
119 Offset -= 2 * Hexagon_WordSize;
120 }
121
122 unsigned FrameSize = MFI.getStackSize();
123 if (MI.getOpcode() == Hexagon::TFR_FI)
124 MI.setDesc(TII.get(Hexagon::A2_addi));
125
126 if (!MFI.hasVarSizedObjects() &&
127 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) &&
128 !TII.isSpillPredRegOp(&MI)) {
129 // Replace frame index with a stack pointer reference.
130 MI.getOperand(FIOperandNum).ChangeToRegister(getStackRegister(), false,
131 false, true);
132 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(FrameSize+Offset);
133 } else {
134 // Replace frame index with a frame pointer reference.
135 if (!TII.isValidOffset(MI.getOpcode(), Offset)) {
136
137 // If the offset overflows, then correct it.
138 //
139 // For loads, we do not need a reserved register
140 // r0 = memw(r30 + #10000) to:
141 //
142 // r0 = add(r30, #10000)
143 // r0 = memw(r0)
144 if ( (MI.getOpcode() == Hexagon::L2_loadri_io) ||
145 (MI.getOpcode() == Hexagon::L2_loadrd_io) ||
146 (MI.getOpcode() == Hexagon::L2_loadrh_io) ||
147 (MI.getOpcode() == Hexagon::L2_loadruh_io) ||
148 (MI.getOpcode() == Hexagon::L2_loadrb_io) ||
149 (MI.getOpcode() == Hexagon::L2_loadrub_io)) {
150 unsigned dstReg = (MI.getOpcode() == Hexagon::L2_loadrd_io) ?
151 getSubReg(MI.getOperand(0).getReg(), Hexagon::subreg_loreg) :
152 MI.getOperand(0).getReg();
153
154 // Check if offset can fit in addi.
155 if (!TII.isValidOffset(Hexagon::A2_addi, Offset)) {
156 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
157 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
158 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
159 TII.get(Hexagon::A2_add),
160 dstReg).addReg(FrameReg).addReg(dstReg);
161 } else {
162 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
163 TII.get(Hexagon::A2_addi),
164 dstReg).addReg(FrameReg).addImm(Offset);
165 }
166
167 MI.getOperand(FIOperandNum).ChangeToRegister(dstReg, false, false,true);
168 MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
169 } else if ((MI.getOpcode() == Hexagon::S2_storeri_io) ||
170 (MI.getOpcode() == Hexagon::S2_storerd_io) ||
171 (MI.getOpcode() == Hexagon::S2_storerh_io) ||
172 (MI.getOpcode() == Hexagon::S2_storerb_io)) {
173 // For stores, we need a reserved register. Change
174 // memw(r30 + #10000) = r0 to:
175 //
176 // rs = add(r30, #10000);
177 // memw(rs) = r0
178 unsigned resReg = HEXAGON_RESERVED_REG_1;
179
180 // Check if offset can fit in addi.
181 if (!TII.isValidOffset(Hexagon::A2_addi, Offset)) {
182 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
183 TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset);
184 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
185 TII.get(Hexagon::A2_add),
186 resReg).addReg(FrameReg).addReg(resReg);
187 } else {
188 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
189 TII.get(Hexagon::A2_addi),
190 resReg).addReg(FrameReg).addImm(Offset);
191 }
192 MI.getOperand(FIOperandNum).ChangeToRegister(resReg, false, false,true);
193 MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
194 } else if (TII.isMemOp(&MI)) {
195 // use the constant extender if the instruction provides it
196 if (TII.isConstExtended(&MI)) {
197 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);
198 MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
199 TII.immediateExtend(&MI);
200 } else {
201 llvm_unreachable("Need to implement for memops");
202 }
203 } else {
204 unsigned dstReg = MI.getOperand(0).getReg();
205 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
206 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
207 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
208 TII.get(Hexagon::A2_add),
209 dstReg).addReg(FrameReg).addReg(dstReg);
210 // Can we delete MI??? r2 = add (r2, #0).
211 MI.getOperand(FIOperandNum).ChangeToRegister(dstReg, false, false,true);
212 MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
213 }
214 } else {
215 // If the offset is small enough to fit in the immediate field, directly
216 // encode it.
217 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);
218 MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
219 }
220 }
221
222 }
223
getRARegister() const224 unsigned HexagonRegisterInfo::getRARegister() const {
225 return Hexagon::R31;
226 }
227
getFrameRegister(const MachineFunction & MF) const228 unsigned HexagonRegisterInfo::getFrameRegister(const MachineFunction
229 &MF) const {
230 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
231 if (TFI->hasFP(MF)) {
232 return Hexagon::R30;
233 }
234
235 return Hexagon::R29;
236 }
237
getFrameRegister() const238 unsigned HexagonRegisterInfo::getFrameRegister() const {
239 return Hexagon::R30;
240 }
241
getStackRegister() const242 unsigned HexagonRegisterInfo::getStackRegister() const {
243 return Hexagon::R29;
244 }
245
246 #define GET_REGINFO_TARGET_DESC
247 #include "HexagonGenRegisterInfo.inc"
248