1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "MipsRegisterInfo.h"
15 #include "Mips.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsInstrInfo.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/IR/Constants.h"
27 #include "llvm/IR/DebugInfo.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38
39 using namespace llvm;
40
41 #define DEBUG_TYPE "mips-reg-info"
42
43 #define GET_REGINFO_TARGET_DESC
44 #include "MipsGenRegisterInfo.inc"
45
MipsRegisterInfo()46 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {}
47
getPICCallReg()48 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
49
50 const TargetRegisterClass *
getPointerRegClass(const MachineFunction & MF,unsigned Kind) const51 MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
52 unsigned Kind) const {
53 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
54 return Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
55 }
56
57 unsigned
getRegPressureLimit(const TargetRegisterClass * RC,MachineFunction & MF) const58 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
59 MachineFunction &MF) const {
60 switch (RC->getID()) {
61 default:
62 return 0;
63 case Mips::GPR32RegClassID:
64 case Mips::GPR64RegClassID:
65 case Mips::DSPRRegClassID: {
66 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
67 return 28 - TFI->hasFP(MF);
68 }
69 case Mips::FGR32RegClassID:
70 return 32;
71 case Mips::AFGR64RegClassID:
72 return 16;
73 case Mips::FGR64RegClassID:
74 return 32;
75 }
76 }
77
78 //===----------------------------------------------------------------------===//
79 // Callee Saved Registers methods
80 //===----------------------------------------------------------------------===//
81
82 /// Mips Callee Saved Registers
83 const MCPhysReg *
getCalleeSavedRegs(const MachineFunction * MF) const84 MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
85 const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
86 if (Subtarget.isSingleFloat())
87 return CSR_SingleFloatOnly_SaveList;
88
89 if (Subtarget.isABI_N64())
90 return CSR_N64_SaveList;
91
92 if (Subtarget.isABI_N32())
93 return CSR_N32_SaveList;
94
95 if (Subtarget.isFP64bit())
96 return CSR_O32_FP64_SaveList;
97
98 if (Subtarget.isFPXX())
99 return CSR_O32_FPXX_SaveList;
100
101 return CSR_O32_SaveList;
102 }
103
104 const uint32_t *
getCallPreservedMask(const MachineFunction & MF,CallingConv::ID) const105 MipsRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
106 CallingConv::ID) const {
107 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
108 if (Subtarget.isSingleFloat())
109 return CSR_SingleFloatOnly_RegMask;
110
111 if (Subtarget.isABI_N64())
112 return CSR_N64_RegMask;
113
114 if (Subtarget.isABI_N32())
115 return CSR_N32_RegMask;
116
117 if (Subtarget.isFP64bit())
118 return CSR_O32_FP64_RegMask;
119
120 if (Subtarget.isFPXX())
121 return CSR_O32_FPXX_RegMask;
122
123 return CSR_O32_RegMask;
124 }
125
getMips16RetHelperMask()126 const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
127 return CSR_Mips16RetHelper_RegMask;
128 }
129
130 BitVector MipsRegisterInfo::
getReservedRegs(const MachineFunction & MF) const131 getReservedRegs(const MachineFunction &MF) const {
132 static const MCPhysReg ReservedGPR32[] = {
133 Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
134 };
135
136 static const MCPhysReg ReservedGPR64[] = {
137 Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
138 };
139
140 BitVector Reserved(getNumRegs());
141 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
142 typedef TargetRegisterClass::const_iterator RegIter;
143
144 for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
145 Reserved.set(ReservedGPR32[I]);
146
147 // Reserve registers for the NaCl sandbox.
148 if (Subtarget.isTargetNaCl()) {
149 Reserved.set(Mips::T6); // Reserved for control flow mask.
150 Reserved.set(Mips::T7); // Reserved for memory access mask.
151 Reserved.set(Mips::T8); // Reserved for thread pointer.
152 }
153
154 for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
155 Reserved.set(ReservedGPR64[I]);
156
157 // For mno-abicalls, GP is a program invariant!
158 if (!Subtarget.isABICalls()) {
159 Reserved.set(Mips::GP);
160 Reserved.set(Mips::GP_64);
161 }
162
163 if (Subtarget.isFP64bit()) {
164 // Reserve all registers in AFGR64.
165 for (RegIter Reg = Mips::AFGR64RegClass.begin(),
166 EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
167 Reserved.set(*Reg);
168 } else {
169 // Reserve all registers in FGR64.
170 for (RegIter Reg = Mips::FGR64RegClass.begin(),
171 EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
172 Reserved.set(*Reg);
173 }
174 // Reserve FP if this function should have a dedicated frame pointer register.
175 if (Subtarget.getFrameLowering()->hasFP(MF)) {
176 if (Subtarget.inMips16Mode())
177 Reserved.set(Mips::S0);
178 else {
179 Reserved.set(Mips::FP);
180 Reserved.set(Mips::FP_64);
181 }
182 }
183
184 // Reserve hardware registers.
185 Reserved.set(Mips::HWR29);
186
187 // Reserve DSP control register.
188 Reserved.set(Mips::DSPPos);
189 Reserved.set(Mips::DSPSCount);
190 Reserved.set(Mips::DSPCarry);
191 Reserved.set(Mips::DSPEFI);
192 Reserved.set(Mips::DSPOutFlag);
193
194 // Reserve MSA control registers.
195 Reserved.set(Mips::MSAIR);
196 Reserved.set(Mips::MSACSR);
197 Reserved.set(Mips::MSAAccess);
198 Reserved.set(Mips::MSASave);
199 Reserved.set(Mips::MSAModify);
200 Reserved.set(Mips::MSARequest);
201 Reserved.set(Mips::MSAMap);
202 Reserved.set(Mips::MSAUnmap);
203
204 // Reserve RA if in mips16 mode.
205 if (Subtarget.inMips16Mode()) {
206 const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
207 Reserved.set(Mips::RA);
208 Reserved.set(Mips::RA_64);
209 Reserved.set(Mips::T0);
210 Reserved.set(Mips::T1);
211 if (MF.getFunction()->hasFnAttribute("saveS2") || MipsFI->hasSaveS2())
212 Reserved.set(Mips::S2);
213 }
214
215 // Reserve GP if small section is used.
216 if (Subtarget.useSmallSection()) {
217 Reserved.set(Mips::GP);
218 Reserved.set(Mips::GP_64);
219 }
220
221 if (Subtarget.isABI_O32() && !Subtarget.useOddSPReg()) {
222 for (const auto &Reg : Mips::OddSPRegClass)
223 Reserved.set(Reg);
224 }
225
226 return Reserved;
227 }
228
229 bool
requiresRegisterScavenging(const MachineFunction & MF) const230 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
231 return true;
232 }
233
234 bool
trackLivenessAfterRegAlloc(const MachineFunction & MF) const235 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
236 return true;
237 }
238
239 // FrameIndex represent objects inside a abstract stack.
240 // We must replace FrameIndex with an stack/frame pointer
241 // direct reference.
242 void MipsRegisterInfo::
eliminateFrameIndex(MachineBasicBlock::iterator II,int SPAdj,unsigned FIOperandNum,RegScavenger * RS) const243 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
244 unsigned FIOperandNum, RegScavenger *RS) const {
245 MachineInstr &MI = *II;
246 MachineFunction &MF = *MI.getParent()->getParent();
247
248 DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
249 errs() << "<--------->\n" << MI);
250
251 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
252 uint64_t stackSize = MF.getFrameInfo()->getStackSize();
253 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
254
255 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
256 << "spOffset : " << spOffset << "\n"
257 << "stackSize : " << stackSize << "\n");
258
259 eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
260 }
261
262 unsigned MipsRegisterInfo::
getFrameRegister(const MachineFunction & MF) const263 getFrameRegister(const MachineFunction &MF) const {
264 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
265 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
266 bool IsN64 =
267 static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64();
268
269 if (Subtarget.inMips16Mode())
270 return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
271 else
272 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
273 (IsN64 ? Mips::SP_64 : Mips::SP);
274
275 }
276
277