1 //===-- SparcRegisterInfo.cpp - SPARC Register Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the SPARC implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "SparcRegisterInfo.h"
15 #include "Sparc.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "SparcSubtarget.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/IR/Type.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27
28 using namespace llvm;
29
30 #define GET_REGINFO_TARGET_DESC
31 #include "SparcGenRegisterInfo.inc"
32
33 static cl::opt<bool>
34 ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
35 cl::desc("Reserve application registers (%g2-%g4)"));
36
SparcRegisterInfo()37 SparcRegisterInfo::SparcRegisterInfo() : SparcGenRegisterInfo(SP::O7) {}
38
39 const MCPhysReg*
getCalleeSavedRegs(const MachineFunction * MF) const40 SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
41 return CSR_SaveList;
42 }
43
44 const uint32_t *
getCallPreservedMask(const MachineFunction & MF,CallingConv::ID CC) const45 SparcRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
46 CallingConv::ID CC) const {
47 return CSR_RegMask;
48 }
49
50 const uint32_t*
getRTCallPreservedMask(CallingConv::ID CC) const51 SparcRegisterInfo::getRTCallPreservedMask(CallingConv::ID CC) const {
52 return RTCSR_RegMask;
53 }
54
getReservedRegs(const MachineFunction & MF) const55 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
56 BitVector Reserved(getNumRegs());
57 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
58 // FIXME: G1 reserved for now for large imm generation by frame code.
59 Reserved.set(SP::G1);
60
61 // G1-G4 can be used in applications.
62 if (ReserveAppRegisters) {
63 Reserved.set(SP::G2);
64 Reserved.set(SP::G3);
65 Reserved.set(SP::G4);
66 }
67 // G5 is not reserved in 64 bit mode.
68 if (!Subtarget.is64Bit())
69 Reserved.set(SP::G5);
70
71 Reserved.set(SP::O6);
72 Reserved.set(SP::I6);
73 Reserved.set(SP::I7);
74 Reserved.set(SP::G0);
75 Reserved.set(SP::G6);
76 Reserved.set(SP::G7);
77
78 // Unaliased double registers are not available in non-V9 targets.
79 if (!Subtarget.isV9()) {
80 for (unsigned n = 0; n != 16; ++n) {
81 for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI)
82 Reserved.set(*AI);
83 }
84 }
85
86 return Reserved;
87 }
88
89 const TargetRegisterClass*
getPointerRegClass(const MachineFunction & MF,unsigned Kind) const90 SparcRegisterInfo::getPointerRegClass(const MachineFunction &MF,
91 unsigned Kind) const {
92 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
93 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
94 }
95
replaceFI(MachineFunction & MF,MachineBasicBlock::iterator II,MachineInstr & MI,DebugLoc dl,unsigned FIOperandNum,int Offset,unsigned FramePtr)96 static void replaceFI(MachineFunction &MF,
97 MachineBasicBlock::iterator II,
98 MachineInstr &MI,
99 DebugLoc dl,
100 unsigned FIOperandNum, int Offset,
101 unsigned FramePtr)
102 {
103 // Replace frame index with a frame pointer reference.
104 if (Offset >= -4096 && Offset <= 4095) {
105 // If the offset is small enough to fit in the immediate field, directly
106 // encode it.
107 MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
108 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
109 return;
110 }
111
112 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
113
114 // FIXME: it would be better to scavenge a register here instead of
115 // reserving G1 all of the time.
116 if (Offset >= 0) {
117 // Emit nonnegaive immediates with sethi + or.
118 // sethi %hi(Offset), %g1
119 // add %g1, %fp, %g1
120 // Insert G1+%lo(offset) into the user.
121 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
122 .addImm(HI22(Offset));
123
124
125 // Emit G1 = G1 + I6
126 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
127 .addReg(FramePtr);
128 // Insert: G1+%lo(offset) into the user.
129 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
130 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(LO10(Offset));
131 return;
132 }
133
134 // Emit Negative numbers with sethi + xor
135 // sethi %hix(Offset), %g1
136 // xor %g1, %lox(offset), %g1
137 // add %g1, %fp, %g1
138 // Insert: G1 + 0 into the user.
139 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
140 .addImm(HIX22(Offset));
141 BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1)
142 .addReg(SP::G1).addImm(LOX10(Offset));
143
144 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
145 .addReg(FramePtr);
146 // Insert: G1+%lo(offset) into the user.
147 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
148 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
149 }
150
151
152 void
eliminateFrameIndex(MachineBasicBlock::iterator II,int SPAdj,unsigned FIOperandNum,RegScavenger * RS) const153 SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
154 int SPAdj, unsigned FIOperandNum,
155 RegScavenger *RS) const {
156 assert(SPAdj == 0 && "Unexpected");
157
158 MachineInstr &MI = *II;
159 DebugLoc dl = MI.getDebugLoc();
160 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
161
162 // Addressable stack objects are accessed using neg. offsets from %fp
163 MachineFunction &MF = *MI.getParent()->getParent();
164 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
165 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
166 MI.getOperand(FIOperandNum + 1).getImm() +
167 Subtarget.getStackPointerBias();
168 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
169 unsigned FramePtr = SP::I6;
170 if (FuncInfo->isLeafProc()) {
171 // Use %sp and adjust offset if needed.
172 FramePtr = SP::O6;
173 int stackSize = MF.getFrameInfo()->getStackSize();
174 Offset += (stackSize) ? Subtarget.getAdjustedFrameSize(stackSize) : 0 ;
175 }
176
177 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) {
178 if (MI.getOpcode() == SP::STQFri) {
179 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
180 unsigned SrcReg = MI.getOperand(2).getReg();
181 unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
182 unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
183 MachineInstr *StMI =
184 BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
185 .addReg(FramePtr).addImm(0).addReg(SrcEvenReg);
186 replaceFI(MF, II, *StMI, dl, 0, Offset, FramePtr);
187 MI.setDesc(TII.get(SP::STDFri));
188 MI.getOperand(2).setReg(SrcOddReg);
189 Offset += 8;
190 } else if (MI.getOpcode() == SP::LDQFri) {
191 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
192 unsigned DestReg = MI.getOperand(0).getReg();
193 unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64);
194 unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64);
195 MachineInstr *StMI =
196 BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)
197 .addReg(FramePtr).addImm(0);
198 replaceFI(MF, II, *StMI, dl, 1, Offset, FramePtr);
199
200 MI.setDesc(TII.get(SP::LDDFri));
201 MI.getOperand(0).setReg(DestOddReg);
202 Offset += 8;
203 }
204 }
205
206 replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FramePtr);
207
208 }
209
getFrameRegister(const MachineFunction & MF) const210 unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
211 return SP::I6;
212 }
213
214