1 //===-- ARMSelectionDAGInfo.h - ARM SelectionDAG Info -----------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the ARM subclass for TargetSelectionDAGInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARMSELECTIONDAGINFO_H
15 #define LLVM_LIB_TARGET_ARM_ARMSELECTIONDAGINFO_H
16 
17 #include "MCTargetDesc/ARMAddressingModes.h"
18 #include "llvm/Target/TargetSelectionDAGInfo.h"
19 
20 namespace llvm {
21 
22 namespace ARM_AM {
getShiftOpcForNode(unsigned Opcode)23   static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) {
24     switch (Opcode) {
25     default:          return ARM_AM::no_shift;
26     case ISD::SHL:    return ARM_AM::lsl;
27     case ISD::SRL:    return ARM_AM::lsr;
28     case ISD::SRA:    return ARM_AM::asr;
29     case ISD::ROTR:   return ARM_AM::ror;
30     //case ISD::ROTL:  // Only if imm -> turn into ROTR.
31     // Can't handle RRX here, because it would require folding a flag into
32     // the addressing mode.  :(  This causes us to miss certain things.
33     //case ARMISD::RRX: return ARM_AM::rrx;
34     }
35   }
36 }  // end namespace ARM_AM
37 
38 class ARMSelectionDAGInfo : public TargetSelectionDAGInfo {
39 public:
40   explicit ARMSelectionDAGInfo(const DataLayout &DL);
41   ~ARMSelectionDAGInfo();
42 
43   SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
44                                   SDValue Chain,
45                                   SDValue Dst, SDValue Src,
46                                   SDValue Size, unsigned Align,
47                                   bool isVolatile, bool AlwaysInline,
48                                   MachinePointerInfo DstPtrInfo,
49                                   MachinePointerInfo SrcPtrInfo) const override;
50 
51   // Adjust parameters for memset, see RTABI section 4.3.4
52   SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl,
53                                   SDValue Chain,
54                                   SDValue Op1, SDValue Op2,
55                                   SDValue Op3, unsigned Align,
56                                   bool isVolatile,
57                                   MachinePointerInfo DstPtrInfo) const override;
58 };
59 
60 }
61 
62 #endif
63