1 //===-- X86RegisterInfo.h - X86 Register Information Impl -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the X86 implementation of the TargetRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_X86_X86REGISTERINFO_H 15 #define LLVM_LIB_TARGET_X86_X86REGISTERINFO_H 16 17 #include "llvm/Target/TargetRegisterInfo.h" 18 19 #define GET_REGINFO_HEADER 20 #include "X86GenRegisterInfo.inc" 21 22 namespace llvm { 23 class X86RegisterInfo final : public X86GenRegisterInfo { 24 private: 25 /// Is64Bit - Is the target 64-bits. 26 /// 27 bool Is64Bit; 28 29 /// IsWin64 - Is the target on of win64 flavours 30 /// 31 bool IsWin64; 32 33 /// SlotSize - Stack slot size in bytes. 34 /// 35 unsigned SlotSize; 36 37 /// StackPtr - X86 physical register used as stack ptr. 38 /// 39 unsigned StackPtr; 40 41 /// FramePtr - X86 physical register used as frame ptr. 42 /// 43 unsigned FramePtr; 44 45 /// BasePtr - X86 physical register used as a base ptr in complex stack 46 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to 47 /// variable size stack objects. 48 unsigned BasePtr; 49 50 public: 51 X86RegisterInfo(const Triple &TT); 52 53 // FIXME: This should be tablegen'd like getDwarfRegNum is 54 int getSEHRegNum(unsigned i) const; 55 56 /// Code Generation virtual methods... 57 /// 58 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override; 59 60 /// getMatchingSuperRegClass - Return a subclass of the specified register 61 /// class A so that each register in it has a sub-register of the 62 /// specified sub-register index which is in the specified register class B. 63 const TargetRegisterClass * 64 getMatchingSuperRegClass(const TargetRegisterClass *A, 65 const TargetRegisterClass *B, 66 unsigned Idx) const override; 67 68 const TargetRegisterClass * 69 getSubClassWithSubReg(const TargetRegisterClass *RC, 70 unsigned Idx) const override; 71 72 const TargetRegisterClass * 73 getLargestLegalSuperClass(const TargetRegisterClass *RC, 74 const MachineFunction &MF) const override; 75 76 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 77 /// values. 78 const TargetRegisterClass * 79 getPointerRegClass(const MachineFunction &MF, 80 unsigned Kind = 0) const override; 81 82 /// getCrossCopyRegClass - Returns a legal register class to copy a register 83 /// in the specified class to or from. Returns NULL if it is possible to copy 84 /// between a two registers of the specified class. 85 const TargetRegisterClass * 86 getCrossCopyRegClass(const TargetRegisterClass *RC) const override; 87 88 unsigned getRegPressureLimit(const TargetRegisterClass *RC, 89 MachineFunction &MF) const override; 90 91 /// getCalleeSavedRegs - Return a null-terminated list of all of the 92 /// callee-save registers on this target. 93 const MCPhysReg * 94 getCalleeSavedRegs(const MachineFunction* MF) const override; 95 const uint32_t *getCallPreservedMask(const MachineFunction &MF, 96 CallingConv::ID) const override; 97 const uint32_t *getNoPreservedMask() const; 98 99 /// getReservedRegs - Returns a bitset indexed by physical register number 100 /// indicating if a register is a special register that has particular uses and 101 /// should be considered unavailable at all times, e.g. SP, RA. This is used by 102 /// register scavenger to determine what registers are free. 103 BitVector getReservedRegs(const MachineFunction &MF) const override; 104 105 bool hasBasePointer(const MachineFunction &MF) const; 106 107 bool canRealignStack(const MachineFunction &MF) const; 108 109 bool needsStackRealignment(const MachineFunction &MF) const override; 110 111 bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 112 int &FrameIdx) const override; 113 114 void eliminateFrameIndex(MachineBasicBlock::iterator MI, 115 int SPAdj, unsigned FIOperandNum, 116 RegScavenger *RS = nullptr) const override; 117 118 // Debug information queries. 119 unsigned getFrameRegister(const MachineFunction &MF) const override; 120 unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const; getStackRegister()121 unsigned getStackRegister() const { return StackPtr; } getBaseRegister()122 unsigned getBaseRegister() const { return BasePtr; } 123 // FIXME: Move to FrameInfok getSlotSize()124 unsigned getSlotSize() const { return SlotSize; } 125 }; 126 127 // getX86SubSuperRegister - X86 utility function. It returns the sub or super 128 // register of a specific X86 register. 129 // e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX 130 unsigned getX86SubSuperRegister(unsigned, MVT::SimpleValueType, bool High=false); 131 132 //get512BitRegister - X86 utility - returns 512-bit super register 133 unsigned get512BitSuperRegister(unsigned Reg); 134 135 } // End llvm namespace 136 137 #endif 138