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Searched defs:info (Results 1 – 25 of 68) sorted by relevance

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/art/compiler/dex/quick/
Dgen_invoke.cc48 void Mir2Lir::AddIntrinsicSlowPath(CallInfo* info, LIR* branch, LIR* resume) { in AddIntrinsicSlowPath()
489 static void CommonCallCodeLoadThisIntoArg1(const CallInfo* info, Mir2Lir* cg) { in CommonCallCodeLoadThisIntoArg1()
494 static void CommonCallCodeLoadClassIntoArg0(const CallInfo* info, Mir2Lir* cg) { in CommonCallCodeLoadClassIntoArg0()
523 static int NextVCallInsn(CompilationUnit* cu, CallInfo* info, in NextVCallInsn()
569 static int NextInterfaceCallInsn(CompilationUnit* cu, CallInfo* info, int state, in NextInterfaceCallInsn()
610 static int NextInvokeInsnSP(CompilationUnit* cu, CallInfo* info, in NextInvokeInsnSP()
639 static int NextStaticCallInsnSP(CompilationUnit* cu, CallInfo* info, in NextStaticCallInsnSP()
647 static int NextDirectCallInsnSP(CompilationUnit* cu, CallInfo* info, int state, in NextDirectCallInsnSP()
654 static int NextSuperCallInsnSP(CompilationUnit* cu, CallInfo* info, int state, in NextSuperCallInsnSP()
661 static int NextVCallInsnSP(CompilationUnit* cu, CallInfo* info, int state, in NextVCallInsnSP()
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Dralloc_util.cc84 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); in RegisterPool() local
90 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); in RegisterPool() local
96 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); in RegisterPool() local
102 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); in RegisterPool() local
179 RegisterInfo* info = GetRegInfo(reg); in Clobber() local
198 void Mir2Lir::ClobberAliases(RegisterInfo* info, uint32_t clobber_mask) { in ClobberAliases()
344 RegisterInfo* info = regs[next]; in AllocTempBody() local
371 RegisterInfo* info = regs[next]; in AllocTempBody() local
516 RegisterInfo* info = GetRegInfo(reg); in AllocLiveReg() local
646 RegisterInfo* info = nullptr; in NullifyRange() local
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Dquick_cfi_test.cc91 for (const auto& info : m2l->reg_pool_->core_regs_) { in TestImpl() local
97 for (const auto& info : m2l->reg_pool_->sp_regs_) { in TestImpl() local
Dmir_to_lir-inl.h101 inline LIR* Mir2Lir::NewLIR2NoDest(int opcode, int src, int info) { in NewLIR2NoDest()
121 inline LIR* Mir2Lir::NewLIR4(int opcode, int dest, int src1, int src2, int info) { in NewLIR4()
/art/runtime/
Dgc_root.h89 ALWAYS_INLINE void VisitRoot(mirror::Object** roots, const RootInfo& info) in VisitRoot()
95 ALWAYS_INLINE void VisitRootIfNonNull(mirror::Object** roots, const RootInfo& info) in VisitRootIfNonNull()
114 void VisitRoots(mirror::Object*** roots, size_t count, const RootInfo& info) OVERRIDE in VisitRoots()
122 const RootInfo& info) OVERRIDE in VisitRoots()
138 void VisitRoot(RootVisitor* visitor, const RootInfo& info) const in VisitRoot()
146 void VisitRootIfNonNull(RootVisitor* visitor, const RootInfo& info) const in VisitRootIfNonNull()
Dstack_map.cc109 void StackMap::SetDexPc(const CodeInfo& info, uint32_t dex_pc) { in SetDexPc()
117 void StackMap::SetNativePcOffset(const CodeInfo& info, uint32_t native_pc_offset) { in SetNativePcOffset()
128 void StackMap::SetDexRegisterMapOffset(const CodeInfo& info, uint32_t offset) { in SetDexRegisterMapOffset()
143 void StackMap::SetInlineDescriptorOffset(const CodeInfo& info, uint32_t offset) { in SetInlineDescriptorOffset()
157 void StackMap::SetRegisterMask(const CodeInfo& info, uint32_t mask) { in SetRegisterMask()
Dfault_handler.cc81 static void art_fault_handler(int sig, siginfo_t* info, void* context) { in art_fault_handler()
86 static void art_nested_signal_handler(int sig, siginfo_t* info, void* context) { in art_nested_signal_handler()
148 void FaultManager::HandleFault(int sig, siginfo_t* info, void* context) { in HandleFault()
Druntime_android.cc34 void HandleUnexpectedSignal(int signal_number, siginfo_t* info, void* raw_context) { in HandleUnexpectedSignal()
Druntime_linux.cc55 utsname info; in Dump() local
304 void HandleUnexpectedSignal(int signal_number, siginfo_t* info, void* raw_context) { in HandleUnexpectedSignal()
/art/compiler/dex/quick/arm64/
Dfp_arm64.cc372 bool Arm64Mir2Lir::GenInlinedAbsFloat(CallInfo* info) { in GenInlinedAbsFloat()
391 bool Arm64Mir2Lir::GenInlinedAbsDouble(CallInfo* info) { in GenInlinedAbsDouble()
410 bool Arm64Mir2Lir::GenInlinedSqrt(CallInfo* info) { in GenInlinedSqrt()
420 bool Arm64Mir2Lir::GenInlinedCeil(CallInfo* info) { in GenInlinedCeil()
430 bool Arm64Mir2Lir::GenInlinedFloor(CallInfo* info) { in GenInlinedFloor()
440 bool Arm64Mir2Lir::GenInlinedRint(CallInfo* info) { in GenInlinedRint()
450 bool Arm64Mir2Lir::GenInlinedRound(CallInfo* info, bool is_double) { in GenInlinedRound()
467 bool Arm64Mir2Lir::GenInlinedMinMaxFP(CallInfo* info, bool is_min, bool is_double) { in GenInlinedMinMaxFP()
/art/compiler/dex/quick/arm/
Dfp_arm.cc171 RegisterInfo* info = GetRegInfo(rl_src.reg); in GenConversion() local
195 RegisterInfo* info = GetRegInfo(rl_src.reg); in GenConversion() local
388 bool ArmMir2Lir::GenInlinedAbsFloat(CallInfo* info) { in GenInlinedAbsFloat()
406 bool ArmMir2Lir::GenInlinedAbsDouble(CallInfo* info) { in GenInlinedAbsDouble()
433 bool ArmMir2Lir::GenInlinedSqrt(CallInfo* info) { in GenInlinedSqrt()
/art/compiler/optimizing/
Dlicm.cc32 HLoopInformation* info = instruction->GetBlock()->GetLoopInformation(); in InputsAreDefinedBeforeLoop() local
66 static void UpdateLoopPhisIn(HEnvironment* environment, HLoopInformation* info) { in UpdateLoopPhisIn()
Dside_effects_analysis.cc83 void SideEffectsAnalysis::UpdateLoopEffects(HLoopInformation* info, SideEffects effects) { in UpdateLoopEffects()
/art/tools/dexfuzz/src/dexfuzz/rawdex/formats/
DContainsPoolIndex.java40 public PoolIndexKind getPoolIndexKind(OpcodeInfo info); in getPoolIndexKind()
DFormat3rc.java62 public PoolIndexKind getPoolIndexKind(OpcodeInfo info) { in getPoolIndexKind()
DFormat21c.java66 public PoolIndexKind getPoolIndexKind(OpcodeInfo info) { in getPoolIndexKind()
DFormat22c.java66 public PoolIndexKind getPoolIndexKind(OpcodeInfo info) { in getPoolIndexKind()
DFormat22cs.java67 public PoolIndexKind getPoolIndexKind(OpcodeInfo info) { in getPoolIndexKind()
DFormat31c.java65 public PoolIndexKind getPoolIndexKind(OpcodeInfo info) { in getPoolIndexKind()
DFormat35c.java69 public PoolIndexKind getPoolIndexKind(OpcodeInfo info) { in getPoolIndexKind()
/art/compiler/dex/quick/x86/
Dfp_x86.cc605 bool X86Mir2Lir::GenInlinedSqrt(CallInfo* info) { in GenInlinedSqrt()
619 bool X86Mir2Lir::GenInlinedAbsFloat(CallInfo* info) { in GenInlinedAbsFloat()
666 bool X86Mir2Lir::GenInlinedAbsDouble(CallInfo* info) { in GenInlinedAbsDouble()
731 bool X86Mir2Lir::GenInlinedMinMaxFP(CallInfo* info, bool is_min, bool is_double) { in GenInlinedMinMaxFP()
Dtarget_x86.cc659 RegisterInfo* info = new (arena_) RegisterInfo(reg, GetRegMaskCommon(reg)); in CompilerInitializeRegAlloc() local
670 RegisterInfo* info = new (arena_) RegisterInfo(RegStorage(kRIPReg), kEncodeNone); in CompilerInitializeRegAlloc() local
1121 bool X86Mir2Lir::GenInlinedArrayCopyCharArray(CallInfo* info) { in GenInlinedArrayCopyCharArray()
1256 bool X86Mir2Lir::GenInlinedIndexOf(CallInfo* info, bool zero_based) { in GenInlinedIndexOf()
1507 for (RegisterInfo *info = xp_reg_info->GetAliasChain(); in ReserveVectorRegisters() local
1524 for (RegisterInfo *info = xp_reg_info->GetAliasChain(); in ReturnVectorRegisters() local
2416 bool X86Mir2Lir::GenInlinedCharAt(CallInfo* info) { in GenInlinedCharAt()
2459 bool X86Mir2Lir::GenInlinedCurrentThread(CallInfo* info) { in GenInlinedCurrentThread()
2490 RegisterInfo* info = mir_to_lir_->GetRegInfo(reg); in ExplicitTempRegisterLock() local
2521 int X86Mir2Lir::GenDalvikArgsBulkCopy(CallInfo* info, int first, int count) { in GenDalvikArgsBulkCopy()
/art/compiler/dex/quick/mips/
Dint_mips.cc344 bool MipsMir2Lir::GenInlinedCas(CallInfo* info, bool is_long, bool is_object) { in GenInlinedCas()
349 bool MipsMir2Lir::GenInlinedAbsFloat(CallInfo* info) { in GenInlinedAbsFloat()
355 bool MipsMir2Lir::GenInlinedAbsDouble(CallInfo* info) { in GenInlinedAbsDouble()
361 bool MipsMir2Lir::GenInlinedSqrt(CallInfo* info) { in GenInlinedSqrt()
366 bool MipsMir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { in GenInlinedPeek()
389 bool MipsMir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { in GenInlinedPoke()
/art/runtime/gc/space/
Dlarge_object_space.cc396 void FreeListSpace::RemoveFreePrev(AllocationInfo* info) { in RemoveFreePrev()
409 AllocationInfo* info = GetAllocationInfoForAddress(reinterpret_cast<uintptr_t>(obj)); in Free() local
465 AllocationInfo* info = GetAllocationInfoForAddress(reinterpret_cast<uintptr_t>(obj)); in AllocationSize() local
485 AllocationInfo* info = *it; in Alloc() local
559 const AllocationInfo* info = GetAllocationInfoForAddress(reinterpret_cast<uintptr_t>(obj)); in IsZygoteLargeObject() local
/art/tools/dexfuzz/src/dexfuzz/
DLog.java48 public static void info(String msg) { in info() method in Log

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