/art/compiler/dex/quick/ |
D | gen_invoke.cc | 48 void Mir2Lir::AddIntrinsicSlowPath(CallInfo* info, LIR* branch, LIR* resume) { in AddIntrinsicSlowPath() 489 static void CommonCallCodeLoadThisIntoArg1(const CallInfo* info, Mir2Lir* cg) { in CommonCallCodeLoadThisIntoArg1() 494 static void CommonCallCodeLoadClassIntoArg0(const CallInfo* info, Mir2Lir* cg) { in CommonCallCodeLoadClassIntoArg0() 523 static int NextVCallInsn(CompilationUnit* cu, CallInfo* info, in NextVCallInsn() 569 static int NextInterfaceCallInsn(CompilationUnit* cu, CallInfo* info, int state, in NextInterfaceCallInsn() 610 static int NextInvokeInsnSP(CompilationUnit* cu, CallInfo* info, in NextInvokeInsnSP() 639 static int NextStaticCallInsnSP(CompilationUnit* cu, CallInfo* info, in NextStaticCallInsnSP() 647 static int NextDirectCallInsnSP(CompilationUnit* cu, CallInfo* info, int state, in NextDirectCallInsnSP() 654 static int NextSuperCallInsnSP(CompilationUnit* cu, CallInfo* info, int state, in NextSuperCallInsnSP() 661 static int NextVCallInsnSP(CompilationUnit* cu, CallInfo* info, int state, in NextVCallInsnSP() [all …]
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D | ralloc_util.cc | 84 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); in RegisterPool() local 90 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); in RegisterPool() local 96 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); in RegisterPool() local 102 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); in RegisterPool() local 179 RegisterInfo* info = GetRegInfo(reg); in Clobber() local 198 void Mir2Lir::ClobberAliases(RegisterInfo* info, uint32_t clobber_mask) { in ClobberAliases() 344 RegisterInfo* info = regs[next]; in AllocTempBody() local 371 RegisterInfo* info = regs[next]; in AllocTempBody() local 516 RegisterInfo* info = GetRegInfo(reg); in AllocLiveReg() local 646 RegisterInfo* info = nullptr; in NullifyRange() local [all …]
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D | quick_cfi_test.cc | 91 for (const auto& info : m2l->reg_pool_->core_regs_) { in TestImpl() local 97 for (const auto& info : m2l->reg_pool_->sp_regs_) { in TestImpl() local
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D | mir_to_lir-inl.h | 101 inline LIR* Mir2Lir::NewLIR2NoDest(int opcode, int src, int info) { in NewLIR2NoDest() 121 inline LIR* Mir2Lir::NewLIR4(int opcode, int dest, int src1, int src2, int info) { in NewLIR4()
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/art/runtime/ |
D | gc_root.h | 89 ALWAYS_INLINE void VisitRoot(mirror::Object** roots, const RootInfo& info) in VisitRoot() 95 ALWAYS_INLINE void VisitRootIfNonNull(mirror::Object** roots, const RootInfo& info) in VisitRootIfNonNull() 114 void VisitRoots(mirror::Object*** roots, size_t count, const RootInfo& info) OVERRIDE in VisitRoots() 122 const RootInfo& info) OVERRIDE in VisitRoots() 138 void VisitRoot(RootVisitor* visitor, const RootInfo& info) const in VisitRoot() 146 void VisitRootIfNonNull(RootVisitor* visitor, const RootInfo& info) const in VisitRootIfNonNull()
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D | stack_map.cc | 109 void StackMap::SetDexPc(const CodeInfo& info, uint32_t dex_pc) { in SetDexPc() 117 void StackMap::SetNativePcOffset(const CodeInfo& info, uint32_t native_pc_offset) { in SetNativePcOffset() 128 void StackMap::SetDexRegisterMapOffset(const CodeInfo& info, uint32_t offset) { in SetDexRegisterMapOffset() 143 void StackMap::SetInlineDescriptorOffset(const CodeInfo& info, uint32_t offset) { in SetInlineDescriptorOffset() 157 void StackMap::SetRegisterMask(const CodeInfo& info, uint32_t mask) { in SetRegisterMask()
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D | fault_handler.cc | 81 static void art_fault_handler(int sig, siginfo_t* info, void* context) { in art_fault_handler() 86 static void art_nested_signal_handler(int sig, siginfo_t* info, void* context) { in art_nested_signal_handler() 148 void FaultManager::HandleFault(int sig, siginfo_t* info, void* context) { in HandleFault()
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D | runtime_android.cc | 34 void HandleUnexpectedSignal(int signal_number, siginfo_t* info, void* raw_context) { in HandleUnexpectedSignal()
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D | runtime_linux.cc | 55 utsname info; in Dump() local 304 void HandleUnexpectedSignal(int signal_number, siginfo_t* info, void* raw_context) { in HandleUnexpectedSignal()
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/art/compiler/dex/quick/arm64/ |
D | fp_arm64.cc | 372 bool Arm64Mir2Lir::GenInlinedAbsFloat(CallInfo* info) { in GenInlinedAbsFloat() 391 bool Arm64Mir2Lir::GenInlinedAbsDouble(CallInfo* info) { in GenInlinedAbsDouble() 410 bool Arm64Mir2Lir::GenInlinedSqrt(CallInfo* info) { in GenInlinedSqrt() 420 bool Arm64Mir2Lir::GenInlinedCeil(CallInfo* info) { in GenInlinedCeil() 430 bool Arm64Mir2Lir::GenInlinedFloor(CallInfo* info) { in GenInlinedFloor() 440 bool Arm64Mir2Lir::GenInlinedRint(CallInfo* info) { in GenInlinedRint() 450 bool Arm64Mir2Lir::GenInlinedRound(CallInfo* info, bool is_double) { in GenInlinedRound() 467 bool Arm64Mir2Lir::GenInlinedMinMaxFP(CallInfo* info, bool is_min, bool is_double) { in GenInlinedMinMaxFP()
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/art/compiler/dex/quick/arm/ |
D | fp_arm.cc | 171 RegisterInfo* info = GetRegInfo(rl_src.reg); in GenConversion() local 195 RegisterInfo* info = GetRegInfo(rl_src.reg); in GenConversion() local 388 bool ArmMir2Lir::GenInlinedAbsFloat(CallInfo* info) { in GenInlinedAbsFloat() 406 bool ArmMir2Lir::GenInlinedAbsDouble(CallInfo* info) { in GenInlinedAbsDouble() 433 bool ArmMir2Lir::GenInlinedSqrt(CallInfo* info) { in GenInlinedSqrt()
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/art/compiler/optimizing/ |
D | licm.cc | 32 HLoopInformation* info = instruction->GetBlock()->GetLoopInformation(); in InputsAreDefinedBeforeLoop() local 66 static void UpdateLoopPhisIn(HEnvironment* environment, HLoopInformation* info) { in UpdateLoopPhisIn()
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D | side_effects_analysis.cc | 83 void SideEffectsAnalysis::UpdateLoopEffects(HLoopInformation* info, SideEffects effects) { in UpdateLoopEffects()
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/art/tools/dexfuzz/src/dexfuzz/rawdex/formats/ |
D | ContainsPoolIndex.java | 40 public PoolIndexKind getPoolIndexKind(OpcodeInfo info); in getPoolIndexKind()
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D | Format3rc.java | 62 public PoolIndexKind getPoolIndexKind(OpcodeInfo info) { in getPoolIndexKind()
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D | Format21c.java | 66 public PoolIndexKind getPoolIndexKind(OpcodeInfo info) { in getPoolIndexKind()
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D | Format22c.java | 66 public PoolIndexKind getPoolIndexKind(OpcodeInfo info) { in getPoolIndexKind()
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D | Format22cs.java | 67 public PoolIndexKind getPoolIndexKind(OpcodeInfo info) { in getPoolIndexKind()
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D | Format31c.java | 65 public PoolIndexKind getPoolIndexKind(OpcodeInfo info) { in getPoolIndexKind()
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D | Format35c.java | 69 public PoolIndexKind getPoolIndexKind(OpcodeInfo info) { in getPoolIndexKind()
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/art/compiler/dex/quick/x86/ |
D | fp_x86.cc | 605 bool X86Mir2Lir::GenInlinedSqrt(CallInfo* info) { in GenInlinedSqrt() 619 bool X86Mir2Lir::GenInlinedAbsFloat(CallInfo* info) { in GenInlinedAbsFloat() 666 bool X86Mir2Lir::GenInlinedAbsDouble(CallInfo* info) { in GenInlinedAbsDouble() 731 bool X86Mir2Lir::GenInlinedMinMaxFP(CallInfo* info, bool is_min, bool is_double) { in GenInlinedMinMaxFP()
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D | target_x86.cc | 659 RegisterInfo* info = new (arena_) RegisterInfo(reg, GetRegMaskCommon(reg)); in CompilerInitializeRegAlloc() local 670 RegisterInfo* info = new (arena_) RegisterInfo(RegStorage(kRIPReg), kEncodeNone); in CompilerInitializeRegAlloc() local 1121 bool X86Mir2Lir::GenInlinedArrayCopyCharArray(CallInfo* info) { in GenInlinedArrayCopyCharArray() 1256 bool X86Mir2Lir::GenInlinedIndexOf(CallInfo* info, bool zero_based) { in GenInlinedIndexOf() 1507 for (RegisterInfo *info = xp_reg_info->GetAliasChain(); in ReserveVectorRegisters() local 1524 for (RegisterInfo *info = xp_reg_info->GetAliasChain(); in ReturnVectorRegisters() local 2416 bool X86Mir2Lir::GenInlinedCharAt(CallInfo* info) { in GenInlinedCharAt() 2459 bool X86Mir2Lir::GenInlinedCurrentThread(CallInfo* info) { in GenInlinedCurrentThread() 2490 RegisterInfo* info = mir_to_lir_->GetRegInfo(reg); in ExplicitTempRegisterLock() local 2521 int X86Mir2Lir::GenDalvikArgsBulkCopy(CallInfo* info, int first, int count) { in GenDalvikArgsBulkCopy()
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/art/compiler/dex/quick/mips/ |
D | int_mips.cc | 344 bool MipsMir2Lir::GenInlinedCas(CallInfo* info, bool is_long, bool is_object) { in GenInlinedCas() 349 bool MipsMir2Lir::GenInlinedAbsFloat(CallInfo* info) { in GenInlinedAbsFloat() 355 bool MipsMir2Lir::GenInlinedAbsDouble(CallInfo* info) { in GenInlinedAbsDouble() 361 bool MipsMir2Lir::GenInlinedSqrt(CallInfo* info) { in GenInlinedSqrt() 366 bool MipsMir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { in GenInlinedPeek() 389 bool MipsMir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { in GenInlinedPoke()
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/art/runtime/gc/space/ |
D | large_object_space.cc | 396 void FreeListSpace::RemoveFreePrev(AllocationInfo* info) { in RemoveFreePrev() 409 AllocationInfo* info = GetAllocationInfoForAddress(reinterpret_cast<uintptr_t>(obj)); in Free() local 465 AllocationInfo* info = GetAllocationInfoForAddress(reinterpret_cast<uintptr_t>(obj)); in AllocationSize() local 485 AllocationInfo* info = *it; in Alloc() local 559 const AllocationInfo* info = GetAllocationInfoForAddress(reinterpret_cast<uintptr_t>(obj)); in IsZygoteLargeObject() local
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/art/tools/dexfuzz/src/dexfuzz/ |
D | Log.java | 48 public static void info(String msg) { in info() method in Log
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