1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
16 
17 #include "MCTargetDesc/MipsABIInfo.h"
18 #include "MipsFrameLowering.h"
19 #include "MipsISelLowering.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsSelectionDAGInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
26 #include <string>
27 
28 #define GET_SUBTARGETINFO_HEADER
29 #include "MipsGenSubtargetInfo.inc"
30 
31 namespace llvm {
32 class StringRef;
33 
34 class MipsTargetMachine;
35 
36 class MipsSubtarget : public MipsGenSubtargetInfo {
37   virtual void anchor();
38 
39   enum MipsArchEnum {
40     MipsDefault,
41     Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
42     Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
43   };
44 
45   // Mips architecture version
46   MipsArchEnum MipsArchVersion;
47 
48   // IsLittle - The target is Little Endian
49   bool IsLittle;
50 
51   // IsSingleFloat - The target only supports single precision float
52   // point operations. This enable the target to use all 32 32-bit
53   // floating point registers instead of only using even ones.
54   bool IsSingleFloat;
55 
56   // IsFPXX - MIPS O32 modeless ABI.
57   bool IsFPXX;
58 
59   // NoABICalls - Disable SVR4-style position-independent code.
60   bool NoABICalls;
61 
62   // IsFP64bit - The target processor has 64-bit floating point registers.
63   bool IsFP64bit;
64 
65   /// Are odd single-precision registers permitted?
66   /// This corresponds to -modd-spreg and -mno-odd-spreg
67   bool UseOddSPReg;
68 
69   // IsNan2008 - IEEE 754-2008 NaN encoding.
70   bool IsNaN2008bit;
71 
72   // IsFP64bit - General-purpose registers are 64 bits wide
73   bool IsGP64bit;
74 
75   // HasVFPU - Processor has a vector floating point unit.
76   bool HasVFPU;
77 
78   // CPU supports cnMIPS (Cavium Networks Octeon CPU).
79   bool HasCnMips;
80 
81   // isLinux - Target system is Linux. Is false we consider ELFOS for now.
82   bool IsLinux;
83 
84   // UseSmallSection - Small section is used.
85   bool UseSmallSection;
86 
87   /// Features related to the presence of specific instructions.
88 
89   // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
90   bool HasMips3_32;
91 
92   // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
93   bool HasMips3_32r2;
94 
95   // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
96   bool HasMips4_32;
97 
98   // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
99   bool HasMips4_32r2;
100 
101   // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
102   bool HasMips5_32r2;
103 
104   // InMips16 -- can process Mips16 instructions
105   bool InMips16Mode;
106 
107   // Mips16 hard float
108   bool InMips16HardFloat;
109 
110   // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
111   bool PreviousInMips16Mode;
112 
113   // InMicroMips -- can process MicroMips instructions
114   bool InMicroMipsMode;
115 
116   // HasDSP, HasDSPR2 -- supports DSP ASE.
117   bool HasDSP, HasDSPR2;
118 
119   // Allow mixed Mips16 and Mips32 in one source file
120   bool AllowMixed16_32;
121 
122   // Optimize for space by compiling all functions as Mips 16 unless
123   // it needs floating point. Functions needing floating point are
124   // compiled as Mips32
125   bool Os16;
126 
127   // HasMSA -- supports MSA ASE.
128   bool HasMSA;
129 
130   InstrItineraryData InstrItins;
131 
132   // We can override the determination of whether we are in mips16 mode
133   // as from the command line
134   enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
135 
136   const MipsTargetMachine &TM;
137 
138   Triple TargetTriple;
139 
140   const MipsSelectionDAGInfo TSInfo;
141   std::unique_ptr<const MipsInstrInfo> InstrInfo;
142   std::unique_ptr<const MipsFrameLowering> FrameLowering;
143   std::unique_ptr<const MipsTargetLowering> TLInfo;
144 
145 public:
146   /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
147   bool enablePostMachineScheduler() const override;
148   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
149   CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
150 
151   /// Only O32 and EABI supported right now.
152   bool isABI_EABI() const;
153   bool isABI_N64() const;
154   bool isABI_N32() const;
155   bool isABI_O32() const;
156   const MipsABIInfo &getABI() const;
isABI_FPXX()157   bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
158 
159   /// This constructor initializes the data members to match that
160   /// of the specified triple.
161   MipsSubtarget(const std::string &TT, const std::string &CPU,
162                 const std::string &FS, bool little,
163                 const MipsTargetMachine &TM);
164 
165   /// ParseSubtargetFeatures - Parses features string setting specified
166   /// subtarget options.  Definition of function is auto generated by tblgen.
167   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
168 
hasMips1()169   bool hasMips1() const { return MipsArchVersion >= Mips1; }
hasMips2()170   bool hasMips2() const { return MipsArchVersion >= Mips2; }
hasMips3()171   bool hasMips3() const { return MipsArchVersion >= Mips3; }
hasMips4()172   bool hasMips4() const { return MipsArchVersion >= Mips4; }
hasMips5()173   bool hasMips5() const { return MipsArchVersion >= Mips5; }
hasMips4_32()174   bool hasMips4_32() const { return HasMips4_32; }
hasMips4_32r2()175   bool hasMips4_32r2() const { return HasMips4_32r2; }
hasMips32()176   bool hasMips32() const {
177     return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
178            hasMips64();
179   }
hasMips32r2()180   bool hasMips32r2() const {
181     return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
182            hasMips64r2();
183   }
hasMips32r3()184   bool hasMips32r3() const {
185     return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
186            hasMips64r2();
187   }
hasMips32r5()188   bool hasMips32r5() const {
189     return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
190            hasMips64r2();
191   }
hasMips32r6()192   bool hasMips32r6() const {
193     return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
194            hasMips64r6();
195   }
hasMips64()196   bool hasMips64() const { return MipsArchVersion >= Mips64; }
hasMips64r2()197   bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
hasMips64r3()198   bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
hasMips64r5()199   bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
hasMips64r6()200   bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
201 
hasCnMips()202   bool hasCnMips() const { return HasCnMips; }
203 
isLittle()204   bool isLittle() const { return IsLittle; }
isABICalls()205   bool isABICalls() const { return !NoABICalls; }
isFPXX()206   bool isFPXX() const { return IsFPXX; }
isFP64bit()207   bool isFP64bit() const { return IsFP64bit; }
useOddSPReg()208   bool useOddSPReg() const { return UseOddSPReg; }
noOddSPReg()209   bool noOddSPReg() const { return !UseOddSPReg; }
isNaN2008()210   bool isNaN2008() const { return IsNaN2008bit; }
isGP64bit()211   bool isGP64bit() const { return IsGP64bit; }
isGP32bit()212   bool isGP32bit() const { return !IsGP64bit; }
getGPRSizeInBytes()213   unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
isSingleFloat()214   bool isSingleFloat() const { return IsSingleFloat; }
hasVFPU()215   bool hasVFPU() const { return HasVFPU; }
inMips16Mode()216   bool inMips16Mode() const { return InMips16Mode; }
inMips16ModeDefault()217   bool inMips16ModeDefault() const {
218     return InMips16Mode;
219   }
220   // Hard float for mips16 means essentially to compile as soft float
221   // but to use a runtime library for soft float that is written with
222   // native mips32 floating point instructions (those runtime routines
223   // run in mips32 hard float mode).
inMips16HardFloat()224   bool inMips16HardFloat() const {
225     return inMips16Mode() && InMips16HardFloat;
226   }
inMicroMipsMode()227   bool inMicroMipsMode() const { return InMicroMipsMode; }
hasDSP()228   bool hasDSP() const { return HasDSP; }
hasDSPR2()229   bool hasDSPR2() const { return HasDSPR2; }
hasMSA()230   bool hasMSA() const { return HasMSA; }
useSmallSection()231   bool useSmallSection() const { return UseSmallSection; }
232 
hasStandardEncoding()233   bool hasStandardEncoding() const { return !inMips16Mode(); }
234 
235   bool abiUsesSoftFloat() const;
236 
enableLongBranchPass()237   bool enableLongBranchPass() const {
238     return hasStandardEncoding() || allowMixed16_32();
239   }
240 
241   /// Features related to the presence of specific instructions.
hasExtractInsert()242   bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
hasMTHC1()243   bool hasMTHC1() const { return hasMips32r2(); }
244 
allowMixed16_32()245   bool allowMixed16_32() const { return inMips16ModeDefault() |
246                                         AllowMixed16_32; }
247 
os16()248   bool os16() const { return Os16; }
249 
isTargetNaCl()250   bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
251 
252   // for now constant islands are on for the whole compilation unit but we only
253   // really use them if in addition we are in mips16 mode
254   static bool useConstantIslands();
255 
stackAlignment()256   unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
257 
258   // Grab relocation model
259   Reloc::Model getRelocationModel() const;
260 
261   MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
262                                                  const TargetMachine &TM);
263 
264   /// Does the system support unaligned memory access.
265   ///
266   /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
267   /// specify which component of the system provides it. Hardware, software, and
268   /// hybrid implementations are all valid.
systemSupportsUnalignedAccess()269   bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
270 
271   // Set helper classes
272   void setHelperClassesMips16();
273   void setHelperClassesMipsSE();
274 
getSelectionDAGInfo()275   const MipsSelectionDAGInfo *getSelectionDAGInfo() const override {
276     return &TSInfo;
277   }
getInstrInfo()278   const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
getFrameLowering()279   const TargetFrameLowering *getFrameLowering() const override {
280     return FrameLowering.get();
281   }
getRegisterInfo()282   const MipsRegisterInfo *getRegisterInfo() const override {
283     return &InstrInfo->getRegisterInfo();
284   }
getTargetLowering()285   const MipsTargetLowering *getTargetLowering() const override {
286     return TLInfo.get();
287   }
getInstrItineraryData()288   const InstrItineraryData *getInstrItineraryData() const override {
289     return &InstrItins;
290   }
291 };
292 } // End llvm namespace
293 
294 #endif
295