1 /* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ART_COMPILER_DEX_QUICK_ARM64_ARM64_LIR_H_ 18 #define ART_COMPILER_DEX_QUICK_ARM64_ARM64_LIR_H_ 19 20 #include "dex/compiler_enums.h" 21 #include "dex/reg_location.h" 22 #include "dex/reg_storage.h" 23 24 namespace art { 25 26 /* 27 * Runtime register usage conventions. 28 * 29 * r0 : As in C/C++ w0 is 32-bit return register and x0 is 64-bit. 30 * r0-r7 : Argument registers in both Dalvik and C/C++ conventions. 31 * However, for Dalvik->Dalvik calls we'll pass the target's Method* 32 * pointer in x0 as a hidden arg0. Otherwise used as codegen scratch 33 * registers. 34 * r8-r15 : Caller save registers (used as temporary registers). 35 * r16-r17: Also known as ip0-ip1, respectively. Used as scratch registers by 36 * the linker, by the trampolines and other stubs (the backend uses 37 * these as temporary registers). 38 * r18 : (rxSELF) is reserved (pointer to thread-local storage). 39 * r19-r29: Callee save registers (promotion targets). 40 * r30 : (lr) is reserved (the link register). 41 * rsp : (sp) is reserved (the stack pointer). 42 * rzr : (zr) is reserved (the zero register). 43 * 44 * 18 core temps that codegen can use (r0-r17). 45 * 10 core registers that can be used for promotion. 46 * 47 * Floating-point registers 48 * v0-v31 49 * 50 * v0 : s0 is return register for singles (32-bit) and d0 for doubles (64-bit). 51 * This is analogous to the C/C++ (hard-float) calling convention. 52 * v0-v7 : Floating-point argument registers in both Dalvik and C/C++ conventions. 53 * Also used as temporary and codegen scratch registers. 54 * 55 * v0-v7 and v16-v31 : trashed across C calls. 56 * v8-v15 : bottom 64-bits preserved across C calls (d8-d15 are preserved). 57 * 58 * v16-v31: Used as codegen temp/scratch. 59 * v8-v15 : Can be used for promotion. 60 * 61 * Calling convention (Hard-float) 62 * o On a call to a Dalvik method, pass target's Method* in x0 63 * o r1-r7, v0-v7 will be used for the first 7+8 arguments 64 * o Arguments which cannot be put in registers are placed in appropriate 65 * out slots by the caller. 66 * o Maintain a 16-byte stack alignment 67 * 68 * Stack frame diagram (stack grows down, higher addresses at top): 69 * 70 * +--------------------------------------------+ 71 * | IN[ins-1] | {Note: resides in caller's frame} 72 * | . | 73 * | IN[0] | 74 * | caller's method ArtMethod* | {Pointer sized reference} 75 * +============================================+ {Note: start of callee's frame} 76 * | spill region | {variable sized - will include lr if non-leaf} 77 * +--------------------------------------------+ 78 * | ...filler word... | {Note: used as 2nd word of V[locals-1] if long} 79 * +--------------------------------------------+ 80 * | V[locals-1] | 81 * | V[locals-2] | 82 * | . | 83 * | . | 84 * | V[1] | 85 * | V[0] | 86 * +--------------------------------------------+ 87 * | 0 to 3 words padding | 88 * +--------------------------------------------+ 89 * | OUT[outs-1] | 90 * | OUT[outs-2] | 91 * | . | 92 * | OUT[0] | 93 * | current method ArtMethod* | <<== sp w/ 16-byte alignment 94 * +============================================+ 95 */ 96 97 // First FP callee save. 98 #define A64_FP_CALLEE_SAVE_BASE 8 99 100 // Temporary macros, used to mark code which wants to distinguish betweek zr/sp. 101 #define A64_REG_IS_SP(reg_num) ((reg_num) == rwsp || (reg_num) == rsp) 102 #define A64_REG_IS_ZR(reg_num) ((reg_num) == rwzr || (reg_num) == rxzr) 103 #define A64_REGSTORAGE_IS_SP_OR_ZR(rs) (((rs).GetRegNum() & 0x1f) == 0x1f) 104 105 enum A64ResourceEncodingPos { 106 kA64GPReg0 = 0, 107 kA64RegLR = 30, 108 kA64RegSP = 31, 109 kA64FPReg0 = 32, 110 kA64RegEnd = 64, 111 }; 112 113 #define IS_SIGNED_IMM(size, value) \ 114 ((value) >= -(1 << ((size) - 1)) && (value) < (1 << ((size) - 1))) 115 #define IS_SIGNED_IMM7(value) IS_SIGNED_IMM(7, value) 116 #define IS_SIGNED_IMM9(value) IS_SIGNED_IMM(9, value) 117 #define IS_SIGNED_IMM12(value) IS_SIGNED_IMM(12, value) 118 #define IS_SIGNED_IMM14(value) IS_SIGNED_IMM(14, value) 119 #define IS_SIGNED_IMM19(value) IS_SIGNED_IMM(19, value) 120 #define IS_SIGNED_IMM21(value) IS_SIGNED_IMM(21, value) 121 #define IS_SIGNED_IMM26(value) IS_SIGNED_IMM(26, value) 122 123 // Quick macro used to define the registers. 124 #define A64_REGISTER_CODE_LIST(R) \ 125 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \ 126 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \ 127 R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \ 128 R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31) 129 130 // Registers (integer) values. 131 enum A64NativeRegisterPool { // private marker to avoid generate-operator-out.py from processing. 132 # define A64_DEFINE_REGISTERS(nr) \ 133 rw##nr = RegStorage::k32BitSolo | RegStorage::kCoreRegister | nr, \ 134 rx##nr = RegStorage::k64BitSolo | RegStorage::kCoreRegister | nr, \ 135 rf##nr = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | nr, \ 136 rd##nr = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | nr, 137 A64_REGISTER_CODE_LIST(A64_DEFINE_REGISTERS) 138 #undef A64_DEFINE_REGISTERS 139 140 rxzr = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 0x3f, 141 rwzr = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 0x3f, 142 rsp = rx31, 143 rwsp = rw31, 144 145 // Aliases which are not defined in "ARM Architecture Reference, register names". 146 rxIP0 = rx16, 147 rxIP1 = rx17, 148 rxSELF = rx18, 149 rxLR = rx30, 150 /* 151 * FIXME: It's a bit awkward to define both 32 and 64-bit views of these - we'll only ever use 152 * the 64-bit view. However, for now we'll define a 32-bit view to keep these from being 153 * allocated as 32-bit temp registers. 154 */ 155 rwIP0 = rw16, 156 rwIP1 = rw17, 157 rwSELF = rw18, 158 rwLR = rw30, 159 }; 160 161 #define A64_DEFINE_REGSTORAGES(nr) \ 162 constexpr RegStorage rs_w##nr(RegStorage::kValid | rw##nr); \ 163 constexpr RegStorage rs_x##nr(RegStorage::kValid | rx##nr); \ 164 constexpr RegStorage rs_f##nr(RegStorage::kValid | rf##nr); \ 165 constexpr RegStorage rs_d##nr(RegStorage::kValid | rd##nr); 166 A64_REGISTER_CODE_LIST(A64_DEFINE_REGSTORAGES) 167 #undef A64_DEFINE_REGSTORAGES 168 169 constexpr RegStorage rs_xzr(RegStorage::kValid | rxzr); 170 constexpr RegStorage rs_wzr(RegStorage::kValid | rwzr); 171 constexpr RegStorage rs_xIP0(RegStorage::kValid | rxIP0); 172 constexpr RegStorage rs_wIP0(RegStorage::kValid | rwIP0); 173 constexpr RegStorage rs_xIP1(RegStorage::kValid | rxIP1); 174 constexpr RegStorage rs_wIP1(RegStorage::kValid | rwIP1); 175 // Reserved registers. 176 constexpr RegStorage rs_xSELF(RegStorage::kValid | rxSELF); 177 constexpr RegStorage rs_sp(RegStorage::kValid | rsp); 178 constexpr RegStorage rs_xLR(RegStorage::kValid | rxLR); 179 // TODO: eliminate the need for these. 180 constexpr RegStorage rs_wSELF(RegStorage::kValid | rwSELF); 181 constexpr RegStorage rs_wsp(RegStorage::kValid | rwsp); 182 constexpr RegStorage rs_wLR(RegStorage::kValid | rwLR); 183 184 // RegisterLocation templates return values (following the hard-float calling convention). 185 const RegLocation a64_loc_c_return = 186 {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rs_w0, INVALID_SREG, INVALID_SREG}; 187 const RegLocation a64_loc_c_return_ref = 188 {kLocPhysReg, 0, 0, 0, 0, 0, 1, 0, 1, rs_x0, INVALID_SREG, INVALID_SREG}; 189 const RegLocation a64_loc_c_return_wide = 190 {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, rs_x0, INVALID_SREG, INVALID_SREG}; 191 const RegLocation a64_loc_c_return_float = 192 {kLocPhysReg, 0, 0, 0, 1, 0, 0, 0, 1, rs_f0, INVALID_SREG, INVALID_SREG}; 193 const RegLocation a64_loc_c_return_double = 194 {kLocPhysReg, 1, 0, 0, 1, 0, 0, 0, 1, rs_d0, INVALID_SREG, INVALID_SREG}; 195 196 /** 197 * @brief Shift-type to be applied to a register via EncodeShift(). 198 */ 199 enum A64ShiftEncodings { 200 kA64Lsl = 0x0, 201 kA64Lsr = 0x1, 202 kA64Asr = 0x2, 203 kA64Ror = 0x3 204 }; 205 206 /** 207 * @brief Extend-type to be applied to a register via EncodeExtend(). 208 */ 209 enum A64RegExtEncodings { 210 kA64Uxtb = 0x0, 211 kA64Uxth = 0x1, 212 kA64Uxtw = 0x2, 213 kA64Uxtx = 0x3, 214 kA64Sxtb = 0x4, 215 kA64Sxth = 0x5, 216 kA64Sxtw = 0x6, 217 kA64Sxtx = 0x7 218 }; 219 220 #define ENCODE_NO_SHIFT (EncodeShift(kA64Lsl, 0)) 221 #define ENCODE_NO_EXTEND (EncodeExtend(kA64Uxtx, 0)) 222 /* 223 * The following enum defines the list of supported A64 instructions by the 224 * assembler. Their corresponding EncodingMap positions will be defined in 225 * assemble_arm64.cc. 226 */ 227 enum A64Opcode { 228 kA64First = 0, 229 kA64Adc3rrr = kA64First, // adc [00011010000] rm[20-16] [000000] rn[9-5] rd[4-0]. 230 kA64Add4RRdT, // add [s001000100] imm_12[21-10] rn[9-5] rd[4-0]. 231 kA64Add4rrro, // add [00001011000] rm[20-16] imm_6[15-10] rn[9-5] rd[4-0]. 232 kA64Add4RRre, // add [00001011001] rm[20-16] option[15-13] imm_3[12-10] rn[9-5] rd[4-0]. 233 kA64Adr2xd, // adr [0] immlo[30-29] [10000] immhi[23-5] rd[4-0]. 234 kA64Adrp2xd, // adrp [1] immlo[30-29] [10000] immhi[23-5] rd[4-0]. 235 kA64And3Rrl, // and [00010010] N[22] imm_r[21-16] imm_s[15-10] rn[9-5] rd[4-0]. 236 kA64And4rrro, // and [00001010] shift[23-22] [N=0] rm[20-16] imm_6[15-10] rn[9-5] rd[4-0]. 237 kA64Asr3rrd, // asr [0001001100] immr[21-16] imms[15-10] rn[9-5] rd[4-0]. 238 kA64Asr3rrr, // asr alias of "sbfm arg0, arg1, arg2, {#31/#63}". 239 kA64B2ct, // b.cond [01010100] imm_19[23-5] [0] cond[3-0]. 240 kA64Blr1x, // blr [1101011000111111000000] rn[9-5] [00000]. 241 kA64Br1x, // br [1101011000011111000000] rn[9-5] [00000]. 242 kA64Bl1t, // bl [100101] imm26[25-0]. 243 kA64Brk1d, // brk [11010100001] imm_16[20-5] [00000]. 244 kA64B1t, // b [00010100] offset_26[25-0]. 245 kA64Cbnz2rt, // cbnz[00110101] imm_19[23-5] rt[4-0]. 246 kA64Cbz2rt, // cbz [00110100] imm_19[23-5] rt[4-0]. 247 kA64Cmn3rro, // cmn [s0101011] shift[23-22] [0] rm[20-16] imm_6[15-10] rn[9-5] [11111]. 248 kA64Cmn3Rre, // cmn [s0101011001] rm[20-16] option[15-13] imm_3[12-10] rn[9-5] [11111]. 249 kA64Cmn3RdT, // cmn [00110001] shift[23-22] imm_12[21-10] rn[9-5] [11111]. 250 kA64Cmp3rro, // cmp [s1101011] shift[23-22] [0] rm[20-16] imm_6[15-10] rn[9-5] [11111]. 251 kA64Cmp3Rre, // cmp [s1101011001] rm[20-16] option[15-13] imm_3[12-10] rn[9-5] [11111]. 252 kA64Cmp3RdT, // cmp [01110001] shift[23-22] imm_12[21-10] rn[9-5] [11111]. 253 kA64Csel4rrrc, // csel[s0011010100] rm[20-16] cond[15-12] [00] rn[9-5] rd[4-0]. 254 kA64Csinc4rrrc, // csinc [s0011010100] rm[20-16] cond[15-12] [01] rn[9-5] rd[4-0]. 255 kA64Csinv4rrrc, // csinv [s1011010100] rm[20-16] cond[15-12] [00] rn[9-5] rd[4-0]. 256 kA64Csneg4rrrc, // csneg [s1011010100] rm[20-16] cond[15-12] [01] rn[9-5] rd[4-0]. 257 kA64Dmb1B, // dmb [11010101000000110011] CRm[11-8] [10111111]. 258 kA64Eor3Rrl, // eor [s10100100] N[22] imm_r[21-16] imm_s[15-10] rn[9-5] rd[4-0]. 259 kA64Eor4rrro, // eor [s1001010] shift[23-22] [0] rm[20-16] imm_6[15-10] rn[9-5] rd[4-0]. 260 kA64Extr4rrrd, // extr[s00100111N0] rm[20-16] imm_s[15-10] rn[9-5] rd[4-0]. 261 kA64Fabs2ff, // fabs[000111100s100000110000] rn[9-5] rd[4-0]. 262 kA64Fadd3fff, // fadd[000111100s1] rm[20-16] [001010] rn[9-5] rd[4-0]. 263 kA64Fcmp1f, // fcmp[000111100s100000001000] rn[9-5] [01000]. 264 kA64Fcmp2ff, // fcmp[000111100s1] rm[20-16] [001000] rn[9-5] [00000]. 265 kA64Fcvtzs2wf, // fcvtzs [000111100s111000000000] rn[9-5] rd[4-0]. 266 kA64Fcvtzs2xf, // fcvtzs [100111100s111000000000] rn[9-5] rd[4-0]. 267 kA64Fcvt2Ss, // fcvt [0001111000100010110000] rn[9-5] rd[4-0]. 268 kA64Fcvt2sS, // fcvt [0001111001100010010000] rn[9-5] rd[4-0]. 269 kA64Fcvtms2ws, // fcvtms [0001111000110000000000] rn[9-5] rd[4-0]. 270 kA64Fcvtms2xS, // fcvtms [1001111001110000000000] rn[9-5] rd[4-0]. 271 kA64Fdiv3fff, // fdiv[000111100s1] rm[20-16] [000110] rn[9-5] rd[4-0]. 272 kA64Fmax3fff, // fmax[000111100s1] rm[20-16] [010010] rn[9-5] rd[4-0]. 273 kA64Fmin3fff, // fmin[000111100s1] rm[20-16] [010110] rn[9-5] rd[4-0]. 274 kA64Fmov2ff, // fmov[000111100s100000010000] rn[9-5] rd[4-0]. 275 kA64Fmov2fI, // fmov[000111100s1] imm_8[20-13] [10000000] rd[4-0]. 276 kA64Fmov2sw, // fmov[0001111000100111000000] rn[9-5] rd[4-0]. 277 kA64Fmov2Sx, // fmov[1001111001100111000000] rn[9-5] rd[4-0]. 278 kA64Fmov2ws, // fmov[0001111001101110000000] rn[9-5] rd[4-0]. 279 kA64Fmov2xS, // fmov[1001111001101111000000] rn[9-5] rd[4-0]. 280 kA64Fmul3fff, // fmul[000111100s1] rm[20-16] [000010] rn[9-5] rd[4-0]. 281 kA64Fneg2ff, // fneg[000111100s100001010000] rn[9-5] rd[4-0]. 282 kA64Frintp2ff, // frintp [000111100s100100110000] rn[9-5] rd[4-0]. 283 kA64Frintm2ff, // frintm [000111100s100101010000] rn[9-5] rd[4-0]. 284 kA64Frintn2ff, // frintn [000111100s100100010000] rn[9-5] rd[4-0]. 285 kA64Frintz2ff, // frintz [000111100s100101110000] rn[9-5] rd[4-0]. 286 kA64Fsqrt2ff, // fsqrt[000111100s100001110000] rn[9-5] rd[4-0]. 287 kA64Fsub3fff, // fsub[000111100s1] rm[20-16] [001110] rn[9-5] rd[4-0]. 288 kA64Ldrb3wXd, // ldrb[0011100101] imm_12[21-10] rn[9-5] rt[4-0]. 289 kA64Ldrb3wXx, // ldrb[00111000011] rm[20-16] [011] S[12] [10] rn[9-5] rt[4-0]. 290 kA64Ldrsb3rXd, // ldrsb[001110011s] imm_12[21-10] rn[9-5] rt[4-0]. 291 kA64Ldrsb3rXx, // ldrsb[0011 1000 1s1] rm[20-16] [011] S[12] [10] rn[9-5] rt[4-0]. 292 kA64Ldrh3wXF, // ldrh[0111100101] imm_12[21-10] rn[9-5] rt[4-0]. 293 kA64Ldrh4wXxd, // ldrh[01111000011] rm[20-16] [011] S[12] [10] rn[9-5] rt[4-0]. 294 kA64Ldrsh3rXF, // ldrsh[011110011s] imm_12[21-10] rn[9-5] rt[4-0]. 295 kA64Ldrsh4rXxd, // ldrsh[011110001s1] rm[20-16] [011] S[12] [10] rn[9-5] rt[4-0] 296 kA64Ldr2fp, // ldr [0s011100] imm_19[23-5] rt[4-0]. 297 kA64Ldr2rp, // ldr [0s011000] imm_19[23-5] rt[4-0]. 298 kA64Ldr3fXD, // ldr [1s11110100] imm_12[21-10] rn[9-5] rt[4-0]. 299 kA64Ldr3rXD, // ldr [1s111000010] imm_9[20-12] [01] rn[9-5] rt[4-0]. 300 kA64Ldr4fXxG, // ldr [1s111100011] rm[20-16] [011] S[12] [10] rn[9-5] rt[4-0]. 301 kA64Ldr4rXxG, // ldr [1s111000011] rm[20-16] [011] S[12] [10] rn[9-5] rt[4-0]. 302 kA64LdrPost3rXd, // ldr [1s111000010] imm_9[20-12] [01] rn[9-5] rt[4-0]. 303 kA64Ldp4ffXD, // ldp [0s10110101] imm_7[21-15] rt2[14-10] rn[9-5] rt[4-0]. 304 kA64Ldp4rrXD, // ldp [s010100101] imm_7[21-15] rt2[14-10] rn[9-5] rt[4-0]. 305 kA64LdpPost4rrXD, // ldp [s010100011] imm_7[21-15] rt2[14-10] rn[9-5] rt[4-0]. 306 kA64Ldur3fXd, // ldur[1s111100010] imm_9[20-12] [00] rn[9-5] rt[4-0]. 307 kA64Ldur3rXd, // ldur[1s111000010] imm_9[20-12] [00] rn[9-5] rt[4-0]. 308 kA64Ldxr2rX, // ldxr[1s00100001011111011111] rn[9-5] rt[4-0]. 309 kA64Ldaxr2rX, // ldaxr[1s00100001011111111111] rn[9-5] rt[4-0]. 310 kA64Lsl3rrr, // lsl [s0011010110] rm[20-16] [001000] rn[9-5] rd[4-0]. 311 kA64Lsr3rrd, // lsr alias of "ubfm arg0, arg1, arg2, #{31/63}". 312 kA64Lsr3rrr, // lsr [s0011010110] rm[20-16] [001001] rn[9-5] rd[4-0]. 313 kA64Madd4rrrr, // madd[s0011011000] rm[20-16] [0] ra[14-10] rn[9-5] rd[4-0]. 314 kA64Movk3rdM, // mov [010100101] hw[22-21] imm_16[20-5] rd[4-0]. 315 kA64Movn3rdM, // mov [000100101] hw[22-21] imm_16[20-5] rd[4-0]. 316 kA64Movz3rdM, // mov [011100101] hw[22-21] imm_16[20-5] rd[4-0]. 317 kA64Mov2rr, // mov [00101010000] rm[20-16] [000000] [11111] rd[4-0]. 318 kA64Mvn2rr, // mov [00101010001] rm[20-16] [000000] [11111] rd[4-0]. 319 kA64Mul3rrr, // mul [00011011000] rm[20-16] [011111] rn[9-5] rd[4-0]. 320 kA64Msub4rrrr, // msub[s0011011000] rm[20-16] [1] ra[14-10] rn[9-5] rd[4-0]. 321 kA64Neg3rro, // neg alias of "sub arg0, rzr, arg1, arg2". 322 kA64Nop0, // nop alias of "hint #0" [11010101000000110010000000011111]. 323 kA64Orr3Rrl, // orr [s01100100] N[22] imm_r[21-16] imm_s[15-10] rn[9-5] rd[4-0]. 324 kA64Orr4rrro, // orr [s0101010] shift[23-22] [0] rm[20-16] imm_6[15-10] rn[9-5] rd[4-0]. 325 kA64Ret, // ret [11010110010111110000001111000000]. 326 kA64Rbit2rr, // rbit [s101101011000000000000] rn[9-5] rd[4-0]. 327 kA64Rev2rr, // rev [s10110101100000000001x] rn[9-5] rd[4-0]. 328 kA64Rev162rr, // rev16[s101101011000000000001] rn[9-5] rd[4-0]. 329 kA64Ror3rrr, // ror [s0011010110] rm[20-16] [001011] rn[9-5] rd[4-0]. 330 kA64Sbc3rrr, // sbc [s0011010000] rm[20-16] [000000] rn[9-5] rd[4-0]. 331 kA64Sbfm4rrdd, // sbfm[0001001100] imm_r[21-16] imm_s[15-10] rn[9-5] rd[4-0]. 332 kA64Scvtf2fw, // scvtf [000111100s100010000000] rn[9-5] rd[4-0]. 333 kA64Scvtf2fx, // scvtf [100111100s100010000000] rn[9-5] rd[4-0]. 334 kA64Sdiv3rrr, // sdiv[s0011010110] rm[20-16] [000011] rn[9-5] rd[4-0]. 335 kA64Smull3xww, // smull [10011011001] rm[20-16] [011111] rn[9-5] rd[4-0]. 336 kA64Smulh3xxx, // smulh [10011011010] rm[20-16] [011111] rn[9-5] rd[4-0]. 337 kA64Stp4ffXD, // stp [0s10110100] imm_7[21-15] rt2[14-10] rn[9-5] rt[4-0]. 338 kA64Stp4rrXD, // stp [s010100100] imm_7[21-15] rt2[14-10] rn[9-5] rt[4-0]. 339 kA64StpPost4rrXD, // stp [s010100010] imm_7[21-15] rt2[14-10] rn[9-5] rt[4-0]. 340 kA64StpPre4ffXD, // stp [0s10110110] imm_7[21-15] rt2[14-10] rn[9-5] rt[4-0]. 341 kA64StpPre4rrXD, // stp [s010100110] imm_7[21-15] rt2[14-10] rn[9-5] rt[4-0]. 342 kA64Str3fXD, // str [1s11110100] imm_12[21-10] rn[9-5] rt[4-0]. 343 kA64Str4fXxG, // str [1s111100001] rm[20-16] [011] S[12] [10] rn[9-5] rt[4-0]. 344 kA64Str3rXD, // str [1s11100100] imm_12[21-10] rn[9-5] rt[4-0]. 345 kA64Str4rXxG, // str [1s111000001] rm[20-16] option[15-13] S[12-12] [10] rn[9-5] rt[4-0]. 346 kA64Strb3wXd, // strb[0011100100] imm_12[21-10] rn[9-5] rt[4-0]. 347 kA64Strb3wXx, // strb[00111000001] rm[20-16] [011] S[12] [10] rn[9-5] rt[4-0]. 348 kA64Strh3wXF, // strh[0111100100] imm_12[21-10] rn[9-5] rt[4-0]. 349 kA64Strh4wXxd, // strh[01111000001] rm[20-16] [011] S[12] [10] rn[9-5] rt[4-0]. 350 kA64StrPost3rXd, // str [1s111000000] imm_9[20-12] [01] rn[9-5] rt[4-0]. 351 kA64Stur3fXd, // stur[1s111100000] imm_9[20-12] [00] rn[9-5] rt[4-0]. 352 kA64Stur3rXd, // stur[1s111000000] imm_9[20-12] [00] rn[9-5] rt[4-0]. 353 kA64Stxr3wrX, // stxr[11001000000] rs[20-16] [011111] rn[9-5] rt[4-0]. 354 kA64Stlxr3wrX, // stlxr[11001000000] rs[20-16] [111111] rn[9-5] rt[4-0]. 355 kA64Sub4RRdT, // sub [s101000100] imm_12[21-10] rn[9-5] rd[4-0]. 356 kA64Sub4rrro, // sub [s1001011000] rm[20-16] imm_6[15-10] rn[9-5] rd[4-0]. 357 kA64Sub4RRre, // sub [s1001011001] rm[20-16] option[15-13] imm_3[12-10] rn[9-5] rd[4-0]. 358 kA64Subs3rRd, // subs[s111000100] imm_12[21-10] rn[9-5] rd[4-0]. 359 kA64Tst2rl, // tst alias of "ands rzr, rn, #imm". 360 kA64Tst3rro, // tst alias of "ands rzr, arg1, arg2, arg3". 361 kA64Tbnz3rht, // tbnz imm_6_b5[31] [0110111] imm_6_b40[23-19] imm_14[18-5] rt[4-0]. 362 kA64Tbz3rht, // tbz imm_6_b5[31] [0110110] imm_6_b40[23-19] imm_14[18-5] rt[4-0]. 363 kA64Ubfm4rrdd, // ubfm[s10100110] N[22] imm_r[21-16] imm_s[15-10] rn[9-5] rd[4-0]. 364 kA64Last, 365 kA64NotWide = kA64First, // 0 - Flag used to select the first instruction variant. 366 kA64Wide = 0x1000 // Flag used to select the second instruction variant. 367 }; 368 std::ostream& operator<<(std::ostream& os, const A64Opcode& rhs); 369 370 /* 371 * The A64 instruction set provides two variants for many instructions. For example, "mov wN, wM" 372 * and "mov xN, xM" or - for floating point instructions - "mov sN, sM" and "mov dN, dM". 373 * It definitely makes sense to exploit this symmetries of the instruction set. We do this via the 374 * WIDE, UNWIDE macros. For opcodes that allow it, the wide variant can be obtained by applying the 375 * WIDE macro to the non-wide opcode. E.g. WIDE(kA64Sub4RRdT). 376 */ 377 378 // Return the wide and no-wide variants of the given opcode. 379 #define WIDE(op) ((A64Opcode)((op) | kA64Wide)) 380 #define UNWIDE(op) ((A64Opcode)((op) & ~kA64Wide)) 381 382 // Whether the given opcode is wide. 383 #define IS_WIDE(op) (((op) & kA64Wide) != 0) 384 385 enum A64OpDmbOptions { 386 kSY = 0xf, 387 kST = 0xe, 388 kISH = 0xb, 389 kISHST = 0xa, 390 kISHLD = 0x9, 391 kNSH = 0x7, 392 kNSHST = 0x6 393 }; 394 395 // Instruction assembly field_loc kind. 396 enum A64EncodingKind { 397 // All the formats below are encoded in the same way (as a kFmtBitBlt). 398 // These are grouped together, for fast handling (e.g. "if (LIKELY(fmt <= kFmtBitBlt)) ..."). 399 kFmtRegW = 0, // Word register (w) or wzr. 400 kFmtRegX, // Extended word register (x) or xzr. 401 kFmtRegR, // Register with same width as the instruction or zr. 402 kFmtRegWOrSp, // Word register (w) or wsp. 403 kFmtRegXOrSp, // Extended word register (x) or sp. 404 kFmtRegROrSp, // Register with same width as the instruction or sp. 405 kFmtRegS, // Single FP reg. 406 kFmtRegD, // Double FP reg. 407 kFmtRegF, // Single/double FP reg depending on the instruction width. 408 kFmtBitBlt, // Bit string using end/start. 409 410 // Less likely formats. 411 kFmtUnused, // Unused field and marks end of formats. 412 kFmtImm6Shift, // Shift immediate, 6-bit at [31, 23..19]. 413 kFmtImm21, // Sign-extended immediate using [23..5,30..29]. 414 kFmtShift, // Register shift, 9-bit at [23..21, 15..10].. 415 kFmtExtend, // Register extend, 9-bit at [23..21, 15..10]. 416 kFmtSkip, // Unused field, but continue to next. 417 }; 418 std::ostream& operator<<(std::ostream& os, const A64EncodingKind & rhs); 419 420 // Struct used to define the snippet positions for each A64 opcode. 421 struct A64EncodingMap { 422 uint32_t wskeleton; 423 uint32_t xskeleton; 424 struct { 425 A64EncodingKind kind; 426 int end; // end for kFmtBitBlt, 1-bit slice end for FP regs. 427 int start; // start for kFmtBitBlt, 4-bit slice end for FP regs. 428 } field_loc[4]; 429 A64Opcode opcode; // can be WIDE()-ned to indicate it has a wide variant. 430 uint64_t flags; 431 const char* name; 432 const char* fmt; 433 int size; // Note: size is in bytes. 434 FixupKind fixup; 435 }; 436 437 } // namespace art 438 439 #endif // ART_COMPILER_DEX_QUICK_ARM64_ARM64_LIR_H_ 440