1 //===- HexagonInstPrinter.cpp - Convert Hexagon MCInst to assembly syntax -===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class prints an Hexagon MCInst to a .s file.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "HexagonAsmPrinter.h"
15 #include "Hexagon.h"
16 #include "HexagonInstPrinter.h"
17 #include "MCTargetDesc/HexagonMCInstrInfo.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/Support/raw_ostream.h"
23
24 using namespace llvm;
25
26 #define DEBUG_TYPE "asm-printer"
27
28 #define GET_INSTRUCTION_NAME
29 #include "HexagonGenAsmWriter.inc"
30
31 const char HexagonInstPrinter::PacketPadding = '\t';
32 // Return the minimum value that a constant extendable operand can have
33 // without being extended.
getMinValue(uint64_t TSFlags)34 static int getMinValue(uint64_t TSFlags) {
35 unsigned isSigned =
36 (TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
37 unsigned bits =
38 (TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
39
40 if (isSigned)
41 return -1U << (bits - 1);
42
43 return 0;
44 }
45
46 // Return the maximum value that a constant extendable operand can have
47 // without being extended.
getMaxValue(uint64_t TSFlags)48 static int getMaxValue(uint64_t TSFlags) {
49 unsigned isSigned =
50 (TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
51 unsigned bits =
52 (TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
53
54 if (isSigned)
55 return ~(-1U << (bits - 1));
56
57 return ~(-1U << bits);
58 }
59
60 // Return true if the instruction must be extended.
isExtended(uint64_t TSFlags)61 static bool isExtended(uint64_t TSFlags) {
62 return (TSFlags >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
63 }
64
65 // Currently just used in an assert statement
66 static bool isExtendable(uint64_t TSFlags) LLVM_ATTRIBUTE_UNUSED;
67 // Return true if the instruction may be extended based on the operand value.
isExtendable(uint64_t TSFlags)68 static bool isExtendable(uint64_t TSFlags) {
69 return (TSFlags >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
70 }
71
getOpcodeName(unsigned Opcode) const72 StringRef HexagonInstPrinter::getOpcodeName(unsigned Opcode) const {
73 return MII.getName(Opcode);
74 }
75
getRegName(unsigned RegNo) const76 StringRef HexagonInstPrinter::getRegName(unsigned RegNo) const {
77 return getRegisterName(RegNo);
78 }
79
printInst(MCInst const * MI,raw_ostream & O,StringRef Annot,const MCSubtargetInfo & STI)80 void HexagonInstPrinter::printInst(MCInst const *MI, raw_ostream &O,
81 StringRef Annot,
82 const MCSubtargetInfo &STI) {
83 const char startPacket = '{',
84 endPacket = '}';
85 // TODO: add outer HW loop when it's supported too.
86 if (MI->getOpcode() == Hexagon::ENDLOOP0) {
87 // Ending a harware loop is different from ending an regular packet.
88 assert(HexagonMCInstrInfo::isPacketEnd(*MI) && "Loop-end must also end the packet");
89
90 if (HexagonMCInstrInfo::isPacketBegin(*MI)) {
91 // There must be a packet to end a loop.
92 // FIXME: when shuffling is always run, this shouldn't be needed.
93 MCInst Nop;
94 StringRef NoAnnot;
95
96 Nop.setOpcode (Hexagon::A2_nop);
97 HexagonMCInstrInfo::setPacketBegin (Nop, HexagonMCInstrInfo::isPacketBegin(*MI));
98 printInst (&Nop, O, NoAnnot, STI);
99 }
100
101 // Close the packet.
102 if (HexagonMCInstrInfo::isPacketEnd(*MI))
103 O << PacketPadding << endPacket;
104
105 printInstruction(MI, O);
106 }
107 else {
108 // Prefix the insn opening the packet.
109 if (HexagonMCInstrInfo::isPacketBegin(*MI))
110 O << PacketPadding << startPacket << '\n';
111
112 printInstruction(MI, O);
113
114 // Suffix the insn closing the packet.
115 if (HexagonMCInstrInfo::isPacketEnd(*MI))
116 // Suffix the packet in a new line always, since the GNU assembler has
117 // issues with a closing brace on the same line as CONST{32,64}.
118 O << '\n' << PacketPadding << endPacket;
119 }
120
121 printAnnotation(O, Annot);
122 }
123
printOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O) const124 void HexagonInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
125 raw_ostream &O) const {
126 const MCOperand& MO = MI->getOperand(OpNo);
127
128 if (MO.isReg()) {
129 O << getRegisterName(MO.getReg());
130 } else if(MO.isExpr()) {
131 O << *MO.getExpr();
132 } else if(MO.isImm()) {
133 printImmOperand(MI, OpNo, O);
134 } else {
135 llvm_unreachable("Unknown operand");
136 }
137 }
138
printImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O) const139 void HexagonInstPrinter::printImmOperand(const MCInst *MI, unsigned OpNo,
140 raw_ostream &O) const {
141 const MCOperand& MO = MI->getOperand(OpNo);
142
143 if(MO.isExpr()) {
144 O << *MO.getExpr();
145 } else if(MO.isImm()) {
146 O << MI->getOperand(OpNo).getImm();
147 } else {
148 llvm_unreachable("Unknown operand");
149 }
150 }
151
printExtOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O) const152 void HexagonInstPrinter::printExtOperand(const MCInst *MI, unsigned OpNo,
153 raw_ostream &O) const {
154 const MCOperand &MO = MI->getOperand(OpNo);
155 const MCInstrDesc &MII = getMII().get(MI->getOpcode());
156
157 assert((isExtendable(MII.TSFlags) || isExtended(MII.TSFlags)) &&
158 "Expecting an extendable operand");
159
160 if (MO.isExpr() || isExtended(MII.TSFlags)) {
161 O << "#";
162 } else if (MO.isImm()) {
163 int ImmValue = MO.getImm();
164 if (ImmValue < getMinValue(MII.TSFlags) ||
165 ImmValue > getMaxValue(MII.TSFlags))
166 O << "#";
167 }
168 printOperand(MI, OpNo, O);
169 }
170
printUnsignedImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O) const171 void HexagonInstPrinter::printUnsignedImmOperand(const MCInst *MI,
172 unsigned OpNo, raw_ostream &O) const {
173 O << MI->getOperand(OpNo).getImm();
174 }
175
printNegImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O) const176 void HexagonInstPrinter::printNegImmOperand(const MCInst *MI, unsigned OpNo,
177 raw_ostream &O) const {
178 O << -MI->getOperand(OpNo).getImm();
179 }
180
printNOneImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O) const181 void HexagonInstPrinter::printNOneImmOperand(const MCInst *MI, unsigned OpNo,
182 raw_ostream &O) const {
183 O << -1;
184 }
185
printMEMriOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O) const186 void HexagonInstPrinter::printMEMriOperand(const MCInst *MI, unsigned OpNo,
187 raw_ostream &O) const {
188 const MCOperand& MO0 = MI->getOperand(OpNo);
189 const MCOperand& MO1 = MI->getOperand(OpNo + 1);
190
191 O << getRegisterName(MO0.getReg());
192 O << " + #" << MO1.getImm();
193 }
194
printFrameIndexOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O) const195 void HexagonInstPrinter::printFrameIndexOperand(const MCInst *MI, unsigned OpNo,
196 raw_ostream &O) const {
197 const MCOperand& MO0 = MI->getOperand(OpNo);
198 const MCOperand& MO1 = MI->getOperand(OpNo + 1);
199
200 O << getRegisterName(MO0.getReg()) << ", #" << MO1.getImm();
201 }
202
printGlobalOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O) const203 void HexagonInstPrinter::printGlobalOperand(const MCInst *MI, unsigned OpNo,
204 raw_ostream &O) const {
205 assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
206
207 printOperand(MI, OpNo, O);
208 }
209
printJumpTable(const MCInst * MI,unsigned OpNo,raw_ostream & O) const210 void HexagonInstPrinter::printJumpTable(const MCInst *MI, unsigned OpNo,
211 raw_ostream &O) const {
212 assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
213
214 printOperand(MI, OpNo, O);
215 }
216
printConstantPool(const MCInst * MI,unsigned OpNo,raw_ostream & O) const217 void HexagonInstPrinter::printConstantPool(const MCInst *MI, unsigned OpNo,
218 raw_ostream &O) const {
219 assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
220
221 printOperand(MI, OpNo, O);
222 }
223
printBranchOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O) const224 void HexagonInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
225 raw_ostream &O) const {
226 // Branches can take an immediate operand. This is used by the branch
227 // selection pass to print $+8, an eight byte displacement from the PC.
228 llvm_unreachable("Unknown branch operand.");
229 }
230
printCallOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O) const231 void HexagonInstPrinter::printCallOperand(const MCInst *MI, unsigned OpNo,
232 raw_ostream &O) const {
233 }
234
printAbsAddrOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O) const235 void HexagonInstPrinter::printAbsAddrOperand(const MCInst *MI, unsigned OpNo,
236 raw_ostream &O) const {
237 }
238
printPredicateOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O) const239 void HexagonInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
240 raw_ostream &O) const {
241 }
242
printSymbol(const MCInst * MI,unsigned OpNo,raw_ostream & O,bool hi) const243 void HexagonInstPrinter::printSymbol(const MCInst *MI, unsigned OpNo,
244 raw_ostream &O, bool hi) const {
245 assert(MI->getOperand(OpNo).isImm() && "Unknown symbol operand");
246
247 O << '#' << (hi ? "HI" : "LO") << "(#";
248 printOperand(MI, OpNo, O);
249 O << ')';
250 }
251