1 //===-- InterferenceCache.cpp - Caching per-block interference ---------*--===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // InterferenceCache remembers per-block interference in LiveIntervalUnions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "InterferenceCache.h"
15 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
16 #include "llvm/Support/ErrorHandling.h"
17 #include "llvm/Target/TargetRegisterInfo.h"
18 
19 using namespace llvm;
20 
21 #define DEBUG_TYPE "regalloc"
22 
23 // Static member used for null interference cursors.
24 const InterferenceCache::BlockInterference
25     InterferenceCache::Cursor::NoInterference;
26 
27 // Initializes PhysRegEntries (instead of a SmallVector, PhysRegEntries is a
28 // buffer of size NumPhysRegs to speed up alloc/clear for targets with large
29 // reg files). Calloced memory is used for good form, and quites tools like
30 // Valgrind too, but zero initialized memory is not required by the algorithm:
31 // this is because PhysRegEntries works like a SparseSet and its entries are
32 // only valid when there is a corresponding CacheEntries assignment. There is
33 // also support for when pass managers are reused for targets with different
34 // numbers of PhysRegs: in this case PhysRegEntries is freed and reinitialized.
reinitPhysRegEntries()35 void InterferenceCache::reinitPhysRegEntries() {
36   if (PhysRegEntriesCount == TRI->getNumRegs()) return;
37   free(PhysRegEntries);
38   PhysRegEntriesCount = TRI->getNumRegs();
39   PhysRegEntries = (unsigned char*)
40     calloc(PhysRegEntriesCount, sizeof(unsigned char));
41 }
42 
init(MachineFunction * mf,LiveIntervalUnion * liuarray,SlotIndexes * indexes,LiveIntervals * lis,const TargetRegisterInfo * tri)43 void InterferenceCache::init(MachineFunction *mf,
44                              LiveIntervalUnion *liuarray,
45                              SlotIndexes *indexes,
46                              LiveIntervals *lis,
47                              const TargetRegisterInfo *tri) {
48   MF = mf;
49   LIUArray = liuarray;
50   TRI = tri;
51   reinitPhysRegEntries();
52   for (unsigned i = 0; i != CacheEntries; ++i)
53     Entries[i].clear(mf, indexes, lis);
54 }
55 
get(unsigned PhysReg)56 InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) {
57   unsigned E = PhysRegEntries[PhysReg];
58   if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) {
59     if (!Entries[E].valid(LIUArray, TRI))
60       Entries[E].revalidate(LIUArray, TRI);
61     return &Entries[E];
62   }
63   // No valid entry exists, pick the next round-robin entry.
64   E = RoundRobin;
65   if (++RoundRobin == CacheEntries)
66     RoundRobin = 0;
67   for (unsigned i = 0; i != CacheEntries; ++i) {
68     // Skip entries that are in use.
69     if (Entries[E].hasRefs()) {
70       if (++E == CacheEntries)
71         E = 0;
72       continue;
73     }
74     Entries[E].reset(PhysReg, LIUArray, TRI, MF);
75     PhysRegEntries[PhysReg] = E;
76     return &Entries[E];
77   }
78   llvm_unreachable("Ran out of interference cache entries.");
79 }
80 
81 /// revalidate - LIU contents have changed, update tags.
revalidate(LiveIntervalUnion * LIUArray,const TargetRegisterInfo * TRI)82 void InterferenceCache::Entry::revalidate(LiveIntervalUnion *LIUArray,
83                                           const TargetRegisterInfo *TRI) {
84   // Invalidate all block entries.
85   ++Tag;
86   // Invalidate all iterators.
87   PrevPos = SlotIndex();
88   unsigned i = 0;
89   for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i)
90     RegUnits[i].VirtTag = LIUArray[*Units].getTag();
91 }
92 
reset(unsigned physReg,LiveIntervalUnion * LIUArray,const TargetRegisterInfo * TRI,const MachineFunction * MF)93 void InterferenceCache::Entry::reset(unsigned physReg,
94                                      LiveIntervalUnion *LIUArray,
95                                      const TargetRegisterInfo *TRI,
96                                      const MachineFunction *MF) {
97   assert(!hasRefs() && "Cannot reset cache entry with references");
98   // LIU's changed, invalidate cache.
99   ++Tag;
100   PhysReg = physReg;
101   Blocks.resize(MF->getNumBlockIDs());
102 
103   // Reset iterators.
104   PrevPos = SlotIndex();
105   RegUnits.clear();
106   for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
107     RegUnits.push_back(LIUArray[*Units]);
108     RegUnits.back().Fixed = &LIS->getRegUnit(*Units);
109   }
110 }
111 
valid(LiveIntervalUnion * LIUArray,const TargetRegisterInfo * TRI)112 bool InterferenceCache::Entry::valid(LiveIntervalUnion *LIUArray,
113                                      const TargetRegisterInfo *TRI) {
114   unsigned i = 0, e = RegUnits.size();
115   for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) {
116     if (i == e)
117       return false;
118     if (LIUArray[*Units].changedSince(RegUnits[i].VirtTag))
119       return false;
120   }
121   return i == e;
122 }
123 
update(unsigned MBBNum)124 void InterferenceCache::Entry::update(unsigned MBBNum) {
125   SlotIndex Start, Stop;
126   std::tie(Start, Stop) = Indexes->getMBBRange(MBBNum);
127 
128   // Use advanceTo only when possible.
129   if (PrevPos != Start) {
130     if (!PrevPos.isValid() || Start < PrevPos) {
131       for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
132         RegUnitInfo &RUI = RegUnits[i];
133         RUI.VirtI.find(Start);
134         RUI.FixedI = RUI.Fixed->find(Start);
135       }
136     } else {
137       for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
138         RegUnitInfo &RUI = RegUnits[i];
139         RUI.VirtI.advanceTo(Start);
140         if (RUI.FixedI != RUI.Fixed->end())
141           RUI.FixedI = RUI.Fixed->advanceTo(RUI.FixedI, Start);
142       }
143     }
144     PrevPos = Start;
145   }
146 
147   MachineFunction::const_iterator MFI = MF->getBlockNumbered(MBBNum);
148   BlockInterference *BI = &Blocks[MBBNum];
149   ArrayRef<SlotIndex> RegMaskSlots;
150   ArrayRef<const uint32_t*> RegMaskBits;
151   for (;;) {
152     BI->Tag = Tag;
153     BI->First = BI->Last = SlotIndex();
154 
155     // Check for first interference from virtregs.
156     for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
157       LiveIntervalUnion::SegmentIter &I = RegUnits[i].VirtI;
158       if (!I.valid())
159         continue;
160       SlotIndex StartI = I.start();
161       if (StartI >= Stop)
162         continue;
163       if (!BI->First.isValid() || StartI < BI->First)
164         BI->First = StartI;
165     }
166 
167     // Same thing for fixed interference.
168     for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
169       LiveInterval::const_iterator I = RegUnits[i].FixedI;
170       LiveInterval::const_iterator E = RegUnits[i].Fixed->end();
171       if (I == E)
172         continue;
173       SlotIndex StartI = I->start;
174       if (StartI >= Stop)
175         continue;
176       if (!BI->First.isValid() || StartI < BI->First)
177         BI->First = StartI;
178     }
179 
180     // Also check for register mask interference.
181     RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum);
182     RegMaskBits = LIS->getRegMaskBitsInBlock(MBBNum);
183     SlotIndex Limit = BI->First.isValid() ? BI->First : Stop;
184     for (unsigned i = 0, e = RegMaskSlots.size();
185          i != e && RegMaskSlots[i] < Limit; ++i)
186       if (MachineOperand::clobbersPhysReg(RegMaskBits[i], PhysReg)) {
187         // Register mask i clobbers PhysReg before the LIU interference.
188         BI->First = RegMaskSlots[i];
189         break;
190       }
191 
192     PrevPos = Stop;
193     if (BI->First.isValid())
194       break;
195 
196     // No interference in this block? Go ahead and precompute the next block.
197     if (++MFI == MF->end())
198       return;
199     MBBNum = MFI->getNumber();
200     BI = &Blocks[MBBNum];
201     if (BI->Tag == Tag)
202       return;
203     std::tie(Start, Stop) = Indexes->getMBBRange(MBBNum);
204   }
205 
206   // Check for last interference in block.
207   for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
208     LiveIntervalUnion::SegmentIter &I = RegUnits[i].VirtI;
209     if (!I.valid() || I.start() >= Stop)
210       continue;
211     I.advanceTo(Stop);
212     bool Backup = !I.valid() || I.start() >= Stop;
213     if (Backup)
214       --I;
215     SlotIndex StopI = I.stop();
216     if (!BI->Last.isValid() || StopI > BI->Last)
217       BI->Last = StopI;
218     if (Backup)
219       ++I;
220   }
221 
222   // Fixed interference.
223   for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
224     LiveInterval::iterator &I = RegUnits[i].FixedI;
225     LiveRange *LR = RegUnits[i].Fixed;
226     if (I == LR->end() || I->start >= Stop)
227       continue;
228     I = LR->advanceTo(I, Stop);
229     bool Backup = I == LR->end() || I->start >= Stop;
230     if (Backup)
231       --I;
232     SlotIndex StopI = I->end;
233     if (!BI->Last.isValid() || StopI > BI->Last)
234       BI->Last = StopI;
235     if (Backup)
236       ++I;
237   }
238 
239   // Also check for register mask interference.
240   SlotIndex Limit = BI->Last.isValid() ? BI->Last : Start;
241   for (unsigned i = RegMaskSlots.size();
242        i && RegMaskSlots[i-1].getDeadSlot() > Limit; --i)
243     if (MachineOperand::clobbersPhysReg(RegMaskBits[i-1], PhysReg)) {
244       // Register mask i-1 clobbers PhysReg after the LIU interference.
245       // Model the regmask clobber as a dead def.
246       BI->Last = RegMaskSlots[i-1].getDeadSlot();
247       break;
248     }
249 }
250