| /art/compiler/dex/quick/ |
| D | mir_to_lir-inl.h | 111 inline LIR* Mir2Lir::NewLIR3(int opcode, int dest, int src1, int src2) { in NewLIR3()
121 inline LIR* Mir2Lir::NewLIR4(int opcode, int dest, int src1, int src2, int info) { in NewLIR4()
131 inline LIR* Mir2Lir::NewLIR5(int opcode, int dest, int src1, int src2, int info1, in NewLIR5()
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| /art/runtime/arch/arm64/ |
| D | memcmp16_arm64.S | 29 #define src2 x1 macro
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| /art/compiler/dex/ |
| D | ssa_transformation.cc | 414 const ArenaBitVector* src2) { in ComputeSuccLineIn()
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| D | gvn_dead_code_elimination_test.cc | 134 #define DEF_PHI2(bb, reg, src1, src2) \ argument
138 #define DEF_BINOP(bb, opcode, result, src1, src2) \ argument
140 #define DEF_BINOP_WIDE(bb, opcode, result, src1, src2) \ argument
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| D | global_value_numbering_test.cc | 134 #define DEF_PHI2(bb, reg, src1, src2) \ argument
136 #define DEF_BINOP(bb, opcode, result, src1, src2) \ argument
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| D | type_inference_test.cc | 139 #define DEF_PHI2(bb, reg, src1, src2) \ argument
141 #define DEF_BINOP(bb, opcode, result, src1, src2) \ argument
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| D | mir_optimization.cc | 445 static bool EvaluateBranch(Instruction::Code opcode, int32_t src1, int32_t src2) { in EvaluateBranch()
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| /art/compiler/dex/quick/mips/ |
| D | int_mips.cc | 83 LIR* MipsMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
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| /art/compiler/dex/quick/arm/ |
| D | int_arm.cc | 35 LIR* ArmMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
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| /art/compiler/dex/quick/arm64/ |
| D | int_arm64.cc | 35 LIR* Arm64Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
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| /art/compiler/dex/quick/x86/ |
| D | int_x86.cc | 99 LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
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| /art/runtime/ |
| D | debugger.cc | 1256 const uint16_t* src2 = reinterpret_cast<uint16_t*>(a->GetRawData(sizeof(uint16_t), 0)); in OutputArray() local
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