| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | intel_regions.c | 171 uint32_t tiling, drm_intel_bo *buffer) in intel_region_alloc_internal()
194 uint32_t tiling, in intel_region_alloc()
247 uint32_t bit_6_swizzle, tiling; in intel_region_alloc_for_handle() local
411 uint32_t tiling = region->tiling; in intel_region_get_tile_masks() local
444 uint32_t tiling = region->tiling; in intel_region_get_aligned_offset() local
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| D | intel_screen.c | 386 uint32_t tiling; in intel_create_image() local
893 uint32_t tiling = I915_TILING_X; in intel_detect_swizzling() local
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| D | gen7_wm_surface_state.c | 65 gen7_set_surface_tiling(struct gen7_surface_state *surf, uint32_t tiling) in gen7_set_surface_tiling()
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| D | gen7_blorp.cpp | 185 uint32_t tiling = surface->map_stencil_as_y_tiled in gen7_blorp_emit_surface_state() local
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| D | gen6_blorp.cpp | 446 uint32_t tiling = surface->map_stencil_as_y_tiled in gen6_blorp_emit_surface_state() local
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| D | brw_wm_surface_state.c | 633 brw_get_surface_tiling_bits(uint32_t tiling) in brw_get_surface_tiling_bits()
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| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| D | intel_regions.c | 171 uint32_t tiling, drm_intel_bo *buffer) in intel_region_alloc_internal()
194 uint32_t tiling, in intel_region_alloc()
247 uint32_t bit_6_swizzle, tiling; in intel_region_alloc_for_handle() local
411 uint32_t tiling = region->tiling; in intel_region_get_tile_masks() local
444 uint32_t tiling = region->tiling; in intel_region_get_aligned_offset() local
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| D | intel_screen.c | 386 uint32_t tiling; in intel_create_image() local
893 uint32_t tiling = I915_TILING_X; in intel_detect_swizzling() local
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| /external/mesa3d/src/mesa/drivers/dri/intel/ |
| D | intel_regions.c | 171 uint32_t tiling, drm_intel_bo *buffer) in intel_region_alloc_internal()
194 uint32_t tiling, in intel_region_alloc()
247 uint32_t bit_6_swizzle, tiling; in intel_region_alloc_for_handle() local
411 uint32_t tiling = region->tiling; in intel_region_get_tile_masks() local
444 uint32_t tiling = region->tiling; in intel_region_get_aligned_offset() local
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| D | intel_regions.h | 70 uint32_t tiling; /**< Which tiling mode the region is in */ member
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| D | intel_screen.c | 386 uint32_t tiling; in intel_create_image() local
893 uint32_t tiling = I915_TILING_X; in intel_detect_swizzling() local
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| /external/drm_gralloc/ |
| D | gralloc_drm_radeon.c | 81 static int radeon_get_pitch_align(struct radeon_info *info, int bpe, uint32_t tiling) in radeon_get_pitch_align()
122 static int radeon_get_height_align(struct radeon_info *info, uint32_t tiling) in radeon_get_height_align()
146 int bpe, uint32_t tiling) in radeon_get_base_align()
191 uint32_t tiling, domain; in radeon_alloc() local
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| D | gralloc_drm_intel.c | 71 uint32_t tiling; member
243 uint32_t *tiling, unsigned long *stride) in alloc_ibo()
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| /external/mesa3d/src/gallium/winsys/i915/drm/ |
| D | i915_drm_buffer.c | 58 enum i915_winsys_buffer_tile *tiling, in i915_drm_buffer_create_tiled()
94 enum i915_winsys_buffer_tile *tiling, in i915_drm_buffer_from_handle()
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| /external/mesa3d/src/gallium/drivers/i915/ |
| D | i915_screen.h | 50 boolean tiling; member
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| D | i915_state_sampler.c | 278 ms3_tiling_bits(enum i915_winsys_buffer_tile tiling) in ms3_tiling_bits()
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| D | i915_resource.h | 70 enum i915_winsys_buffer_tile tiling; member
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| D | i915_state_static.c | 79 buf_3d_tiling_bits(enum i915_winsys_buffer_tile tiling) in buf_3d_tiling_bits()
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| D | i915_resource_texture.c | 1008 enum i915_winsys_buffer_tile tiling; in i915_texture_from_handle() local
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| /external/mesa3d/src/gallium/winsys/i915/sw/ |
| D | i915_sw_winsys.h | 46 enum i915_winsys_buffer_tile tiling; member
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| D | i915_sw_buffer.c | 33 enum i915_winsys_buffer_tile *tiling, in i915_sw_buffer_create_tiled()
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| /external/libdrm/tegra/ |
| D | tegra.c | 355 struct drm_tegra_bo_tiling *tiling) in drm_tegra_bo_get_tiling()
382 const struct drm_tegra_bo_tiling *tiling) in drm_tegra_bo_set_tiling()
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| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_mipmap_tree.c | 78 unsigned tiling) in get_texture_image_size()
99 …row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, GLuint targe… in get_texture_image_row_stride()
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| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | radeon_mipmap_tree.c | 78 unsigned tiling) in get_texture_image_size()
99 …row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, GLuint targe… in get_texture_image_row_stride()
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| /external/libdrm/intel/ |
| D | intel_decode.c | 1790 const char *tiling; in decode_3d_1d() local
2165 const char *name, *tiling; in decode_3d_1d() local
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