1 //=- AArch64/AArch64MCCodeEmitter.cpp - Convert AArch64 code to machine code-=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the AArch64MCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "MCTargetDesc/AArch64AddressingModes.h"
15 #include "MCTargetDesc/AArch64FixupKinds.h"
16 #include "MCTargetDesc/AArch64MCExpr.h"
17 #include "Utils/AArch64BaseInfo.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/raw_ostream.h"
26 using namespace llvm;
27
28 #define DEBUG_TYPE "mccodeemitter"
29
30 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
31 STATISTIC(MCNumFixups, "Number of MC fixups created.");
32
33 namespace {
34
35 class AArch64MCCodeEmitter : public MCCodeEmitter {
36 MCContext &Ctx;
37
38 AArch64MCCodeEmitter(const AArch64MCCodeEmitter &); // DO NOT IMPLEMENT
39 void operator=(const AArch64MCCodeEmitter &); // DO NOT IMPLEMENT
40 public:
AArch64MCCodeEmitter(const MCInstrInfo & mcii,MCContext & ctx)41 AArch64MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) : Ctx(ctx) {}
42
~AArch64MCCodeEmitter()43 ~AArch64MCCodeEmitter() override {}
44
45 // getBinaryCodeForInstr - TableGen'erated function for getting the
46 // binary encoding for an instruction.
47 uint64_t getBinaryCodeForInstr(const MCInst &MI,
48 SmallVectorImpl<MCFixup> &Fixups,
49 const MCSubtargetInfo &STI) const;
50
51 /// getMachineOpValue - Return binary encoding of operand. If the machine
52 /// operand requires relocation, record the relocation and return zero.
53 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
54 SmallVectorImpl<MCFixup> &Fixups,
55 const MCSubtargetInfo &STI) const;
56
57 /// getLdStUImm12OpValue - Return encoding info for 12-bit unsigned immediate
58 /// attached to a load, store or prfm instruction. If operand requires a
59 /// relocation, record it and return zero in that part of the encoding.
60 template <uint32_t FixupKind>
61 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
62 SmallVectorImpl<MCFixup> &Fixups,
63 const MCSubtargetInfo &STI) const;
64
65 /// getAdrLabelOpValue - Return encoding info for 21-bit immediate ADR label
66 /// target.
67 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
68 SmallVectorImpl<MCFixup> &Fixups,
69 const MCSubtargetInfo &STI) const;
70
71 /// getAddSubImmOpValue - Return encoding for the 12-bit immediate value and
72 /// the 2-bit shift field.
73 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
74 SmallVectorImpl<MCFixup> &Fixups,
75 const MCSubtargetInfo &STI) const;
76
77 /// getCondBranchTargetOpValue - Return the encoded value for a conditional
78 /// branch target.
79 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
80 SmallVectorImpl<MCFixup> &Fixups,
81 const MCSubtargetInfo &STI) const;
82
83 /// getLoadLiteralOpValue - Return the encoded value for a load-literal
84 /// pc-relative address.
85 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
86 SmallVectorImpl<MCFixup> &Fixups,
87 const MCSubtargetInfo &STI) const;
88
89 /// getMemExtendOpValue - Return the encoded value for a reg-extend load/store
90 /// instruction: bit 0 is whether a shift is present, bit 1 is whether the
91 /// operation is a sign extend (as opposed to a zero extend).
92 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
93 SmallVectorImpl<MCFixup> &Fixups,
94 const MCSubtargetInfo &STI) const;
95
96 /// getTestBranchTargetOpValue - Return the encoded value for a test-bit-and-
97 /// branch target.
98 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
99 SmallVectorImpl<MCFixup> &Fixups,
100 const MCSubtargetInfo &STI) const;
101
102 /// getBranchTargetOpValue - Return the encoded value for an unconditional
103 /// branch target.
104 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
105 SmallVectorImpl<MCFixup> &Fixups,
106 const MCSubtargetInfo &STI) const;
107
108 /// getMoveWideImmOpValue - Return the encoded value for the immediate operand
109 /// of a MOVZ or MOVK instruction.
110 uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
111 SmallVectorImpl<MCFixup> &Fixups,
112 const MCSubtargetInfo &STI) const;
113
114 /// getVecShifterOpValue - Return the encoded value for the vector shifter.
115 uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
116 SmallVectorImpl<MCFixup> &Fixups,
117 const MCSubtargetInfo &STI) const;
118
119 /// getMoveVecShifterOpValue - Return the encoded value for the vector move
120 /// shifter (MSL).
121 uint32_t getMoveVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
122 SmallVectorImpl<MCFixup> &Fixups,
123 const MCSubtargetInfo &STI) const;
124
125 /// getFixedPointScaleOpValue - Return the encoded value for the
126 // FP-to-fixed-point scale factor.
127 uint32_t getFixedPointScaleOpValue(const MCInst &MI, unsigned OpIdx,
128 SmallVectorImpl<MCFixup> &Fixups,
129 const MCSubtargetInfo &STI) const;
130
131 uint32_t getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx,
132 SmallVectorImpl<MCFixup> &Fixups,
133 const MCSubtargetInfo &STI) const;
134 uint32_t getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx,
135 SmallVectorImpl<MCFixup> &Fixups,
136 const MCSubtargetInfo &STI) const;
137 uint32_t getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx,
138 SmallVectorImpl<MCFixup> &Fixups,
139 const MCSubtargetInfo &STI) const;
140 uint32_t getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx,
141 SmallVectorImpl<MCFixup> &Fixups,
142 const MCSubtargetInfo &STI) const;
143 uint32_t getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx,
144 SmallVectorImpl<MCFixup> &Fixups,
145 const MCSubtargetInfo &STI) const;
146 uint32_t getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx,
147 SmallVectorImpl<MCFixup> &Fixups,
148 const MCSubtargetInfo &STI) const;
149 uint32_t getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx,
150 SmallVectorImpl<MCFixup> &Fixups,
151 const MCSubtargetInfo &STI) const;
152 uint32_t getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,
153 SmallVectorImpl<MCFixup> &Fixups,
154 const MCSubtargetInfo &STI) const;
155
156 /// getSIMDShift64OpValue - Return the encoded value for the
157 // shift-by-immediate AdvSIMD instructions.
158 uint32_t getSIMDShift64OpValue(const MCInst &MI, unsigned OpIdx,
159 SmallVectorImpl<MCFixup> &Fixups,
160 const MCSubtargetInfo &STI) const;
161
162 uint32_t getSIMDShift64_32OpValue(const MCInst &MI, unsigned OpIdx,
163 SmallVectorImpl<MCFixup> &Fixups,
164 const MCSubtargetInfo &STI) const;
165
166 uint32_t getSIMDShift32OpValue(const MCInst &MI, unsigned OpIdx,
167 SmallVectorImpl<MCFixup> &Fixups,
168 const MCSubtargetInfo &STI) const;
169
170 uint32_t getSIMDShift16OpValue(const MCInst &MI, unsigned OpIdx,
171 SmallVectorImpl<MCFixup> &Fixups,
172 const MCSubtargetInfo &STI) const;
173
174 unsigned fixMOVZ(const MCInst &MI, unsigned EncodedValue,
175 const MCSubtargetInfo &STI) const;
176
EmitByte(unsigned char C,raw_ostream & OS) const177 void EmitByte(unsigned char C, raw_ostream &OS) const { OS << (char)C; }
178
EmitConstant(uint64_t Val,unsigned Size,raw_ostream & OS) const179 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
180 // Output the constant in little endian byte order.
181 for (unsigned i = 0; i != Size; ++i) {
182 EmitByte(Val & 255, OS);
183 Val >>= 8;
184 }
185 }
186
187 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
188 SmallVectorImpl<MCFixup> &Fixups,
189 const MCSubtargetInfo &STI) const override;
190
191 unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue,
192 const MCSubtargetInfo &STI) const;
193
194 template<int hasRs, int hasRt2> unsigned
195 fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue,
196 const MCSubtargetInfo &STI) const;
197
198 unsigned fixOneOperandFPComparison(const MCInst &MI, unsigned EncodedValue,
199 const MCSubtargetInfo &STI) const;
200 };
201
202 } // end anonymous namespace
203
createAArch64MCCodeEmitter(const MCInstrInfo & MCII,const MCRegisterInfo & MRI,MCContext & Ctx)204 MCCodeEmitter *llvm::createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
205 const MCRegisterInfo &MRI,
206 MCContext &Ctx) {
207 return new AArch64MCCodeEmitter(MCII, Ctx);
208 }
209
210 /// getMachineOpValue - Return binary encoding of operand. If the machine
211 /// operand requires relocation, record the relocation and return zero.
212 unsigned
getMachineOpValue(const MCInst & MI,const MCOperand & MO,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const213 AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
214 SmallVectorImpl<MCFixup> &Fixups,
215 const MCSubtargetInfo &STI) const {
216 if (MO.isReg())
217 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
218
219 assert(MO.isImm() && "did not expect relocated expression");
220 return static_cast<unsigned>(MO.getImm());
221 }
222
223 template<unsigned FixupKind> uint32_t
getLdStUImm12OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const224 AArch64MCCodeEmitter::getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
225 SmallVectorImpl<MCFixup> &Fixups,
226 const MCSubtargetInfo &STI) const {
227 const MCOperand &MO = MI.getOperand(OpIdx);
228 uint32_t ImmVal = 0;
229
230 if (MO.isImm())
231 ImmVal = static_cast<uint32_t>(MO.getImm());
232 else {
233 assert(MO.isExpr() && "unable to encode load/store imm operand");
234 MCFixupKind Kind = MCFixupKind(FixupKind);
235 Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Kind, MI.getLoc()));
236 ++MCNumFixups;
237 }
238
239 return ImmVal;
240 }
241
242 /// getAdrLabelOpValue - Return encoding info for 21-bit immediate ADR label
243 /// target.
244 uint32_t
getAdrLabelOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const245 AArch64MCCodeEmitter::getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
246 SmallVectorImpl<MCFixup> &Fixups,
247 const MCSubtargetInfo &STI) const {
248 const MCOperand &MO = MI.getOperand(OpIdx);
249
250 // If the destination is an immediate, we have nothing to do.
251 if (MO.isImm())
252 return MO.getImm();
253 assert(MO.isExpr() && "Unexpected target type!");
254 const MCExpr *Expr = MO.getExpr();
255
256 MCFixupKind Kind = MI.getOpcode() == AArch64::ADR
257 ? MCFixupKind(AArch64::fixup_aarch64_pcrel_adr_imm21)
258 : MCFixupKind(AArch64::fixup_aarch64_pcrel_adrp_imm21);
259 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
260
261 MCNumFixups += 1;
262
263 // All of the information is in the fixup.
264 return 0;
265 }
266
267 /// getAddSubImmOpValue - Return encoding for the 12-bit immediate value and
268 /// the 2-bit shift field. The shift field is stored in bits 13-14 of the
269 /// return value.
270 uint32_t
getAddSubImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const271 AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
272 SmallVectorImpl<MCFixup> &Fixups,
273 const MCSubtargetInfo &STI) const {
274 // Suboperands are [imm, shifter].
275 const MCOperand &MO = MI.getOperand(OpIdx);
276 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
277 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL &&
278 "unexpected shift type for add/sub immediate");
279 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm());
280 assert((ShiftVal == 0 || ShiftVal == 12) &&
281 "unexpected shift value for add/sub immediate");
282 if (MO.isImm())
283 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << 12));
284 assert(MO.isExpr() && "Unable to encode MCOperand!");
285 const MCExpr *Expr = MO.getExpr();
286
287 // Encode the 12 bits of the fixup.
288 MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_add_imm12);
289 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
290
291 ++MCNumFixups;
292
293 return 0;
294 }
295
296 /// getCondBranchTargetOpValue - Return the encoded value for a conditional
297 /// branch target.
getCondBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const298 uint32_t AArch64MCCodeEmitter::getCondBranchTargetOpValue(
299 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
300 const MCSubtargetInfo &STI) const {
301 const MCOperand &MO = MI.getOperand(OpIdx);
302
303 // If the destination is an immediate, we have nothing to do.
304 if (MO.isImm())
305 return MO.getImm();
306 assert(MO.isExpr() && "Unexpected target type!");
307
308 MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_pcrel_branch19);
309 Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Kind, MI.getLoc()));
310
311 ++MCNumFixups;
312
313 // All of the information is in the fixup.
314 return 0;
315 }
316
317 /// getLoadLiteralOpValue - Return the encoded value for a load-literal
318 /// pc-relative address.
319 uint32_t
getLoadLiteralOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const320 AArch64MCCodeEmitter::getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
321 SmallVectorImpl<MCFixup> &Fixups,
322 const MCSubtargetInfo &STI) const {
323 const MCOperand &MO = MI.getOperand(OpIdx);
324
325 // If the destination is an immediate, we have nothing to do.
326 if (MO.isImm())
327 return MO.getImm();
328 assert(MO.isExpr() && "Unexpected target type!");
329
330 MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_ldr_pcrel_imm19);
331 Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Kind, MI.getLoc()));
332
333 ++MCNumFixups;
334
335 // All of the information is in the fixup.
336 return 0;
337 }
338
339 uint32_t
getMemExtendOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const340 AArch64MCCodeEmitter::getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
341 SmallVectorImpl<MCFixup> &Fixups,
342 const MCSubtargetInfo &STI) const {
343 unsigned SignExtend = MI.getOperand(OpIdx).getImm();
344 unsigned DoShift = MI.getOperand(OpIdx + 1).getImm();
345 return (SignExtend << 1) | DoShift;
346 }
347
348 uint32_t
getMoveWideImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const349 AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
350 SmallVectorImpl<MCFixup> &Fixups,
351 const MCSubtargetInfo &STI) const {
352 const MCOperand &MO = MI.getOperand(OpIdx);
353
354 if (MO.isImm())
355 return MO.getImm();
356 assert(MO.isExpr() && "Unexpected movz/movk immediate");
357
358 Fixups.push_back(MCFixup::Create(
359 0, MO.getExpr(), MCFixupKind(AArch64::fixup_aarch64_movw), MI.getLoc()));
360
361 ++MCNumFixups;
362
363 return 0;
364 }
365
366 /// getTestBranchTargetOpValue - Return the encoded value for a test-bit-and-
367 /// branch target.
getTestBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const368 uint32_t AArch64MCCodeEmitter::getTestBranchTargetOpValue(
369 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
370 const MCSubtargetInfo &STI) const {
371 const MCOperand &MO = MI.getOperand(OpIdx);
372
373 // If the destination is an immediate, we have nothing to do.
374 if (MO.isImm())
375 return MO.getImm();
376 assert(MO.isExpr() && "Unexpected ADR target type!");
377
378 MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_pcrel_branch14);
379 Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Kind, MI.getLoc()));
380
381 ++MCNumFixups;
382
383 // All of the information is in the fixup.
384 return 0;
385 }
386
387 /// getBranchTargetOpValue - Return the encoded value for an unconditional
388 /// branch target.
389 uint32_t
getBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const390 AArch64MCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
391 SmallVectorImpl<MCFixup> &Fixups,
392 const MCSubtargetInfo &STI) const {
393 const MCOperand &MO = MI.getOperand(OpIdx);
394
395 // If the destination is an immediate, we have nothing to do.
396 if (MO.isImm())
397 return MO.getImm();
398 assert(MO.isExpr() && "Unexpected ADR target type!");
399
400 MCFixupKind Kind = MI.getOpcode() == AArch64::BL
401 ? MCFixupKind(AArch64::fixup_aarch64_pcrel_call26)
402 : MCFixupKind(AArch64::fixup_aarch64_pcrel_branch26);
403 Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Kind, MI.getLoc()));
404
405 ++MCNumFixups;
406
407 // All of the information is in the fixup.
408 return 0;
409 }
410
411 /// getVecShifterOpValue - Return the encoded value for the vector shifter:
412 ///
413 /// 00 -> 0
414 /// 01 -> 8
415 /// 10 -> 16
416 /// 11 -> 24
417 uint32_t
getVecShifterOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const418 AArch64MCCodeEmitter::getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
419 SmallVectorImpl<MCFixup> &Fixups,
420 const MCSubtargetInfo &STI) const {
421 const MCOperand &MO = MI.getOperand(OpIdx);
422 assert(MO.isImm() && "Expected an immediate value for the shift amount!");
423
424 switch (MO.getImm()) {
425 default:
426 break;
427 case 0:
428 return 0;
429 case 8:
430 return 1;
431 case 16:
432 return 2;
433 case 24:
434 return 3;
435 }
436
437 llvm_unreachable("Invalid value for vector shift amount!");
438 }
439
440 uint32_t
getSIMDShift64OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const441 AArch64MCCodeEmitter::getSIMDShift64OpValue(const MCInst &MI, unsigned OpIdx,
442 SmallVectorImpl<MCFixup> &Fixups,
443 const MCSubtargetInfo &STI) const {
444 const MCOperand &MO = MI.getOperand(OpIdx);
445 assert(MO.isImm() && "Expected an immediate value for the shift amount!");
446 return 64 - (MO.getImm());
447 }
448
getSIMDShift64_32OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const449 uint32_t AArch64MCCodeEmitter::getSIMDShift64_32OpValue(
450 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
451 const MCSubtargetInfo &STI) const {
452 const MCOperand &MO = MI.getOperand(OpIdx);
453 assert(MO.isImm() && "Expected an immediate value for the shift amount!");
454 return 64 - (MO.getImm() | 32);
455 }
456
457 uint32_t
getSIMDShift32OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const458 AArch64MCCodeEmitter::getSIMDShift32OpValue(const MCInst &MI, unsigned OpIdx,
459 SmallVectorImpl<MCFixup> &Fixups,
460 const MCSubtargetInfo &STI) const {
461 const MCOperand &MO = MI.getOperand(OpIdx);
462 assert(MO.isImm() && "Expected an immediate value for the shift amount!");
463 return 32 - (MO.getImm() | 16);
464 }
465
466 uint32_t
getSIMDShift16OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const467 AArch64MCCodeEmitter::getSIMDShift16OpValue(const MCInst &MI, unsigned OpIdx,
468 SmallVectorImpl<MCFixup> &Fixups,
469 const MCSubtargetInfo &STI) const {
470 const MCOperand &MO = MI.getOperand(OpIdx);
471 assert(MO.isImm() && "Expected an immediate value for the shift amount!");
472 return 16 - (MO.getImm() | 8);
473 }
474
475 /// getFixedPointScaleOpValue - Return the encoded value for the
476 // FP-to-fixed-point scale factor.
getFixedPointScaleOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const477 uint32_t AArch64MCCodeEmitter::getFixedPointScaleOpValue(
478 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
479 const MCSubtargetInfo &STI) const {
480 const MCOperand &MO = MI.getOperand(OpIdx);
481 assert(MO.isImm() && "Expected an immediate value for the scale amount!");
482 return 64 - MO.getImm();
483 }
484
485 uint32_t
getVecShiftR64OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const486 AArch64MCCodeEmitter::getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx,
487 SmallVectorImpl<MCFixup> &Fixups,
488 const MCSubtargetInfo &STI) const {
489 const MCOperand &MO = MI.getOperand(OpIdx);
490 assert(MO.isImm() && "Expected an immediate value for the scale amount!");
491 return 64 - MO.getImm();
492 }
493
494 uint32_t
getVecShiftR32OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const495 AArch64MCCodeEmitter::getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx,
496 SmallVectorImpl<MCFixup> &Fixups,
497 const MCSubtargetInfo &STI) const {
498 const MCOperand &MO = MI.getOperand(OpIdx);
499 assert(MO.isImm() && "Expected an immediate value for the scale amount!");
500 return 32 - MO.getImm();
501 }
502
503 uint32_t
getVecShiftR16OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const504 AArch64MCCodeEmitter::getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx,
505 SmallVectorImpl<MCFixup> &Fixups,
506 const MCSubtargetInfo &STI) const {
507 const MCOperand &MO = MI.getOperand(OpIdx);
508 assert(MO.isImm() && "Expected an immediate value for the scale amount!");
509 return 16 - MO.getImm();
510 }
511
512 uint32_t
getVecShiftR8OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const513 AArch64MCCodeEmitter::getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx,
514 SmallVectorImpl<MCFixup> &Fixups,
515 const MCSubtargetInfo &STI) const {
516 const MCOperand &MO = MI.getOperand(OpIdx);
517 assert(MO.isImm() && "Expected an immediate value for the scale amount!");
518 return 8 - MO.getImm();
519 }
520
521 uint32_t
getVecShiftL64OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const522 AArch64MCCodeEmitter::getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx,
523 SmallVectorImpl<MCFixup> &Fixups,
524 const MCSubtargetInfo &STI) const {
525 const MCOperand &MO = MI.getOperand(OpIdx);
526 assert(MO.isImm() && "Expected an immediate value for the scale amount!");
527 return MO.getImm() - 64;
528 }
529
530 uint32_t
getVecShiftL32OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const531 AArch64MCCodeEmitter::getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx,
532 SmallVectorImpl<MCFixup> &Fixups,
533 const MCSubtargetInfo &STI) const {
534 const MCOperand &MO = MI.getOperand(OpIdx);
535 assert(MO.isImm() && "Expected an immediate value for the scale amount!");
536 return MO.getImm() - 32;
537 }
538
539 uint32_t
getVecShiftL16OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const540 AArch64MCCodeEmitter::getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx,
541 SmallVectorImpl<MCFixup> &Fixups,
542 const MCSubtargetInfo &STI) const {
543 const MCOperand &MO = MI.getOperand(OpIdx);
544 assert(MO.isImm() && "Expected an immediate value for the scale amount!");
545 return MO.getImm() - 16;
546 }
547
548 uint32_t
getVecShiftL8OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const549 AArch64MCCodeEmitter::getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,
550 SmallVectorImpl<MCFixup> &Fixups,
551 const MCSubtargetInfo &STI) const {
552 const MCOperand &MO = MI.getOperand(OpIdx);
553 assert(MO.isImm() && "Expected an immediate value for the scale amount!");
554 return MO.getImm() - 8;
555 }
556
557 /// getMoveVecShifterOpValue - Return the encoded value for the vector move
558 /// shifter (MSL).
getMoveVecShifterOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const559 uint32_t AArch64MCCodeEmitter::getMoveVecShifterOpValue(
560 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
561 const MCSubtargetInfo &STI) const {
562 const MCOperand &MO = MI.getOperand(OpIdx);
563 assert(MO.isImm() &&
564 "Expected an immediate value for the move shift amount!");
565 unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm());
566 assert((ShiftVal == 8 || ShiftVal == 16) && "Invalid shift amount!");
567 return ShiftVal == 8 ? 0 : 1;
568 }
569
fixMOVZ(const MCInst & MI,unsigned EncodedValue,const MCSubtargetInfo & STI) const570 unsigned AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue,
571 const MCSubtargetInfo &STI) const {
572 // If one of the signed fixup kinds is applied to a MOVZ instruction, the
573 // eventual result could be either a MOVZ or a MOVN. It's the MCCodeEmitter's
574 // job to ensure that any bits possibly affected by this are 0. This means we
575 // must zero out bit 30 (essentially emitting a MOVN).
576 MCOperand UImm16MO = MI.getOperand(1);
577
578 // Nothing to do if there's no fixup.
579 if (UImm16MO.isImm())
580 return EncodedValue;
581
582 const AArch64MCExpr *A64E = cast<AArch64MCExpr>(UImm16MO.getExpr());
583 switch (A64E->getKind()) {
584 case AArch64MCExpr::VK_DTPREL_G2:
585 case AArch64MCExpr::VK_DTPREL_G1:
586 case AArch64MCExpr::VK_DTPREL_G0:
587 case AArch64MCExpr::VK_GOTTPREL_G1:
588 case AArch64MCExpr::VK_TPREL_G2:
589 case AArch64MCExpr::VK_TPREL_G1:
590 case AArch64MCExpr::VK_TPREL_G0:
591 return EncodedValue & ~(1u << 30);
592 default:
593 // Nothing to do for an unsigned fixup.
594 return EncodedValue;
595 }
596
597
598 return EncodedValue & ~(1u << 30);
599 }
600
EncodeInstruction(const MCInst & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const601 void AArch64MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
602 SmallVectorImpl<MCFixup> &Fixups,
603 const MCSubtargetInfo &STI) const {
604 if (MI.getOpcode() == AArch64::TLSDESCCALL) {
605 // This is a directive which applies an R_AARCH64_TLSDESC_CALL to the
606 // following (BLR) instruction. It doesn't emit any code itself so it
607 // doesn't go through the normal TableGenerated channels.
608 MCFixupKind Fixup = MCFixupKind(AArch64::fixup_aarch64_tlsdesc_call);
609 Fixups.push_back(MCFixup::Create(0, MI.getOperand(0).getExpr(), Fixup));
610 return;
611 }
612
613 uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
614 EmitConstant(Binary, 4, OS);
615 ++MCNumEmitted; // Keep track of the # of mi's emitted.
616 }
617
618 unsigned
fixMulHigh(const MCInst & MI,unsigned EncodedValue,const MCSubtargetInfo & STI) const619 AArch64MCCodeEmitter::fixMulHigh(const MCInst &MI,
620 unsigned EncodedValue,
621 const MCSubtargetInfo &STI) const {
622 // The Ra field of SMULH and UMULH is unused: it should be assembled as 31
623 // (i.e. all bits 1) but is ignored by the processor.
624 EncodedValue |= 0x1f << 10;
625 return EncodedValue;
626 }
627
628 template<int hasRs, int hasRt2> unsigned
fixLoadStoreExclusive(const MCInst & MI,unsigned EncodedValue,const MCSubtargetInfo & STI) const629 AArch64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI,
630 unsigned EncodedValue,
631 const MCSubtargetInfo &STI) const {
632 if (!hasRs) EncodedValue |= 0x001F0000;
633 if (!hasRt2) EncodedValue |= 0x00007C00;
634
635 return EncodedValue;
636 }
637
fixOneOperandFPComparison(const MCInst & MI,unsigned EncodedValue,const MCSubtargetInfo & STI) const638 unsigned AArch64MCCodeEmitter::fixOneOperandFPComparison(
639 const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const {
640 // The Rm field of FCMP and friends is unused - it should be assembled
641 // as 0, but is ignored by the processor.
642 EncodedValue &= ~(0x1f << 16);
643 return EncodedValue;
644 }
645
646 #include "AArch64GenMCCodeEmitter.inc"
647