1 //===-- AMDIL.h - Top-level interface for AMDIL representation --*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //==-----------------------------------------------------------------------===//
9 //
10 // This file contains the entry points for global functions defined in the LLVM
11 // AMDGPU back-end.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef AMDIL_H_
16 #define AMDIL_H_
17 
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Target/TargetMachine.h"
20 
21 #define ARENA_SEGMENT_RESERVED_UAVS 12
22 #define DEFAULT_ARENA_UAV_ID 8
23 #define DEFAULT_RAW_UAV_ID 7
24 #define GLOBAL_RETURN_RAW_UAV_ID 11
25 #define HW_MAX_NUM_CB 8
26 #define MAX_NUM_UNIQUE_UAVS 8
27 #define OPENCL_MAX_NUM_ATOMIC_COUNTERS 8
28 #define OPENCL_MAX_READ_IMAGES 128
29 #define OPENCL_MAX_WRITE_IMAGES 8
30 #define OPENCL_MAX_SAMPLERS 16
31 
32 // The next two values can never be zero, as zero is the ID that is
33 // used to assert against.
34 #define DEFAULT_LDS_ID     1
35 #define DEFAULT_GDS_ID     1
36 #define DEFAULT_SCRATCH_ID 1
37 #define DEFAULT_VEC_SLOTS  8
38 
39 #define OCL_DEVICE_RV710        0x0001
40 #define OCL_DEVICE_RV730        0x0002
41 #define OCL_DEVICE_RV770        0x0004
42 #define OCL_DEVICE_CEDAR        0x0008
43 #define OCL_DEVICE_REDWOOD      0x0010
44 #define OCL_DEVICE_JUNIPER      0x0020
45 #define OCL_DEVICE_CYPRESS      0x0040
46 #define OCL_DEVICE_CAICOS       0x0080
47 #define OCL_DEVICE_TURKS        0x0100
48 #define OCL_DEVICE_BARTS        0x0200
49 #define OCL_DEVICE_CAYMAN       0x0400
50 #define OCL_DEVICE_ALL          0x3FFF
51 
52 /// The number of function ID's that are reserved for
53 /// internal compiler usage.
54 const unsigned int RESERVED_FUNCS = 1024;
55 
56 namespace llvm {
57 class AMDGPUInstrPrinter;
58 class FunctionPass;
59 class MCAsmInfo;
60 class raw_ostream;
61 class Target;
62 class TargetMachine;
63 
64 /// Instruction selection passes.
65 FunctionPass*
66   createAMDGPUISelDag(TargetMachine &TM);
67 FunctionPass*
68   createAMDGPUPeepholeOpt(TargetMachine &TM);
69 
70 /// Pre emit passes.
71 FunctionPass*
72   createAMDGPUCFGPreparationPass(TargetMachine &TM);
73 FunctionPass*
74   createAMDGPUCFGStructurizerPass(TargetMachine &TM);
75 
76 extern Target TheAMDGPUTarget;
77 } // end namespace llvm;
78 
79 /// Include device information enumerations
80 #include "AMDILDeviceInfo.h"
81 
82 namespace llvm {
83 /// OpenCL uses address spaces to differentiate between
84 /// various memory regions on the hardware. On the CPU
85 /// all of the address spaces point to the same memory,
86 /// however on the GPU, each address space points to
87 /// a seperate piece of memory that is unique from other
88 /// memory locations.
89 namespace AMDGPUAS {
90 enum AddressSpaces {
91   PRIVATE_ADDRESS  = 0, // Address space for private memory.
92   GLOBAL_ADDRESS   = 1, // Address space for global memory (RAT0, VTX0).
93   CONSTANT_ADDRESS = 2, // Address space for constant memory.
94   LOCAL_ADDRESS    = 3, // Address space for local memory.
95   REGION_ADDRESS   = 4, // Address space for region memory.
96   ADDRESS_NONE     = 5, // Address space for unknown memory.
97   PARAM_D_ADDRESS  = 6, // Address space for direct addressible parameter memory (CONST0)
98   PARAM_I_ADDRESS  = 7, // Address space for indirect addressible parameter memory (VTX1)
99   USER_SGPR_ADDRESS = 8, // Address space for USER_SGPRS on SI
100   LAST_ADDRESS     = 9
101 };
102 
103 } // namespace AMDGPUAS
104 
105 } // end namespace llvm
106 #endif // AMDIL_H_
107