1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "llvm/MC/MCDisassembler.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixedLenDisassembler.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/LEB128.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include <vector>
26 
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "arm-disassembler"
30 
31 typedef MCDisassembler::DecodeStatus DecodeStatus;
32 
33 namespace {
34   // Handles the condition code status of instructions in IT blocks
35   class ITStatus
36   {
37     public:
38       // Returns the condition code for instruction in IT block
getITCC()39       unsigned getITCC() {
40         unsigned CC = ARMCC::AL;
41         if (instrInITBlock())
42           CC = ITStates.back();
43         return CC;
44       }
45 
46       // Advances the IT block state to the next T or E
advanceITState()47       void advanceITState() {
48         ITStates.pop_back();
49       }
50 
51       // Returns true if the current instruction is in an IT block
instrInITBlock()52       bool instrInITBlock() {
53         return !ITStates.empty();
54       }
55 
56       // Returns true if current instruction is the last instruction in an IT block
instrLastInITBlock()57       bool instrLastInITBlock() {
58         return ITStates.size() == 1;
59       }
60 
61       // Called when decoding an IT instruction. Sets the IT state for the following
62       // instructions that for the IT block. Firstcond and Mask correspond to the
63       // fields in the IT instruction encoding.
setITState(char Firstcond,char Mask)64       void setITState(char Firstcond, char Mask) {
65         // (3 - the number of trailing zeros) is the number of then / else.
66         unsigned CondBit0 = Firstcond & 1;
67         unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
68         unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
69         assert(NumTZ <= 3 && "Invalid IT mask!");
70         // push condition codes onto the stack the correct order for the pops
71         for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
72           bool T = ((Mask >> Pos) & 1) == CondBit0;
73           if (T)
74             ITStates.push_back(CCBits);
75           else
76             ITStates.push_back(CCBits ^ 1);
77         }
78         ITStates.push_back(CCBits);
79       }
80 
81     private:
82       std::vector<unsigned char> ITStates;
83   };
84 }
85 
86 namespace {
87 /// ARM disassembler for all ARM platforms.
88 class ARMDisassembler : public MCDisassembler {
89 public:
ARMDisassembler(const MCSubtargetInfo & STI,MCContext & Ctx)90   ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
91     MCDisassembler(STI, Ctx) {
92   }
93 
~ARMDisassembler()94   ~ARMDisassembler() override {}
95 
96   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
97                               ArrayRef<uint8_t> Bytes, uint64_t Address,
98                               raw_ostream &VStream,
99                               raw_ostream &CStream) const override;
100 };
101 
102 /// Thumb disassembler for all Thumb platforms.
103 class ThumbDisassembler : public MCDisassembler {
104 public:
ThumbDisassembler(const MCSubtargetInfo & STI,MCContext & Ctx)105   ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
106     MCDisassembler(STI, Ctx) {
107   }
108 
~ThumbDisassembler()109   ~ThumbDisassembler() override {}
110 
111   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
112                               ArrayRef<uint8_t> Bytes, uint64_t Address,
113                               raw_ostream &VStream,
114                               raw_ostream &CStream) const override;
115 
116 private:
117   mutable ITStatus ITBlock;
118   DecodeStatus AddThumbPredicate(MCInst&) const;
119   void UpdateThumbVFPPredicate(MCInst&) const;
120 };
121 }
122 
Check(DecodeStatus & Out,DecodeStatus In)123 static bool Check(DecodeStatus &Out, DecodeStatus In) {
124   switch (In) {
125     case MCDisassembler::Success:
126       // Out stays the same.
127       return true;
128     case MCDisassembler::SoftFail:
129       Out = In;
130       return true;
131     case MCDisassembler::Fail:
132       Out = In;
133       return false;
134   }
135   llvm_unreachable("Invalid DecodeStatus!");
136 }
137 
138 
139 // Forward declare these because the autogenerated code will reference them.
140 // Definitions are further down.
141 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
142                                    uint64_t Address, const void *Decoder);
143 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
144                                                unsigned RegNo, uint64_t Address,
145                                                const void *Decoder);
146 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
147                                                unsigned RegNo, uint64_t Address,
148                                                const void *Decoder);
149 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
150                                    uint64_t Address, const void *Decoder);
151 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
152                                    uint64_t Address, const void *Decoder);
153 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
154                                    uint64_t Address, const void *Decoder);
155 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
156                                    uint64_t Address, const void *Decoder);
157 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
158                                    uint64_t Address, const void *Decoder);
159 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
160                                    uint64_t Address, const void *Decoder);
161 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
162                                    uint64_t Address, const void *Decoder);
163 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
164                                                 unsigned RegNo,
165                                                 uint64_t Address,
166                                                 const void *Decoder);
167 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
168                                    uint64_t Address, const void *Decoder);
169 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
170                                    uint64_t Address, const void *Decoder);
171 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
172                                unsigned RegNo, uint64_t Address,
173                                const void *Decoder);
174 
175 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
176                                uint64_t Address, const void *Decoder);
177 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
178                                uint64_t Address, const void *Decoder);
179 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
180                                uint64_t Address, const void *Decoder);
181 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
182                                uint64_t Address, const void *Decoder);
183 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
184                                uint64_t Address, const void *Decoder);
185 
186 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
187                                uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
189                                uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
191                                                   unsigned Insn,
192                                                   uint64_t Address,
193                                                   const void *Decoder);
194 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
195                                uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
197                                uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
199                                uint64_t Address, const void *Decoder);
200 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
201                                uint64_t Address, const void *Decoder);
202 
203 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
204                                                   unsigned Insn,
205                                                   uint64_t Adddress,
206                                                   const void *Decoder);
207 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
208                                uint64_t Address, const void *Decoder);
209 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
210                                uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
212                                uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
214                                uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
216                                uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
218                                uint64_t Address, const void *Decoder);
219 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
220                                uint64_t Address, const void *Decoder);
221 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
222                                uint64_t Address, const void *Decoder);
223 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
224                                uint64_t Address, const void *Decoder);
225 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
226                                uint64_t Address, const void *Decoder);
227 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
228                                uint64_t Address, const void *Decoder);
229 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
230                                uint64_t Address, const void *Decoder);
231 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
232                                uint64_t Address, const void *Decoder);
233 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
234                                uint64_t Address, const void *Decoder);
235 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
236                                uint64_t Address, const void *Decoder);
237 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
238                                uint64_t Address, const void *Decoder);
239 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
240                                uint64_t Address, const void *Decoder);
241 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
242                                uint64_t Address, const void *Decoder);
243 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
244                                uint64_t Address, const void *Decoder);
245 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
246                                uint64_t Address, const void *Decoder);
247 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
248                                uint64_t Address, const void *Decoder);
249 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
250                                uint64_t Address, const void *Decoder);
251 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
252                                uint64_t Address, const void *Decoder);
253 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
254                                uint64_t Address, const void *Decoder);
255 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
256                                uint64_t Address, const void *Decoder);
257 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
258                                uint64_t Address, const void *Decoder);
259 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
260                                uint64_t Address, const void *Decoder);
261 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
262                                uint64_t Address, const void *Decoder);
263 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
264                                uint64_t Address, const void *Decoder);
265 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
266                                uint64_t Address, const void *Decoder);
267 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
268                                uint64_t Address, const void *Decoder);
269 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
270                                uint64_t Address, const void *Decoder);
271 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
272                                uint64_t Address, const void *Decoder);
273 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
274                                uint64_t Address, const void *Decoder);
275 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
276                                uint64_t Address, const void *Decoder);
277 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
278                                uint64_t Address, const void *Decoder);
279 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
280                                uint64_t Address, const void *Decoder);
281 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
282                                uint64_t Address, const void *Decoder);
283 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
284                                uint64_t Address, const void *Decoder);
285 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
286                                uint64_t Address, const void *Decoder);
287 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
288                                uint64_t Address, const void *Decoder);
289 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
290                                uint64_t Address, const void *Decoder);
291 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
292                                uint64_t Address, const void *Decoder);
293 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
294                                uint64_t Address, const void *Decoder);
295 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
296                                uint64_t Address, const void *Decoder);
297 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
298                                uint64_t Address, const void *Decoder);
299 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
300                                uint64_t Address, const void *Decoder);
301 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
302                                uint64_t Address, const void *Decoder);
303 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
304                                uint64_t Address, const void *Decoder);
305 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
306                                uint64_t Address, const void *Decoder);
307 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
308                                uint64_t Address, const void *Decoder);
309 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
310                                uint64_t Address, const void *Decoder);
311 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
312                                uint64_t Address, const void *Decoder);
313 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
314                                 uint64_t Address, const void *Decoder);
315 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
316                                 uint64_t Address, const void *Decoder);
317 
318 
319 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
320                                uint64_t Address, const void *Decoder);
321 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
322                                uint64_t Address, const void *Decoder);
323 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
324                                uint64_t Address, const void *Decoder);
325 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
326                                uint64_t Address, const void *Decoder);
327 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
328                                uint64_t Address, const void *Decoder);
329 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
330                                uint64_t Address, const void *Decoder);
331 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
332                                uint64_t Address, const void *Decoder);
333 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
334                                uint64_t Address, const void *Decoder);
335 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
336                                uint64_t Address, const void *Decoder);
337 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
338                                uint64_t Address, const void *Decoder);
339 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
340                                uint64_t Address, const void* Decoder);
341 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
342                                uint64_t Address, const void* Decoder);
343 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
344                                uint64_t Address, const void* Decoder);
345 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
346                                uint64_t Address, const void* Decoder);
347 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
348                                uint64_t Address, const void *Decoder);
349 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
350                                uint64_t Address, const void *Decoder);
351 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
352                                uint64_t Address, const void *Decoder);
353 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
354                                uint64_t Address, const void *Decoder);
355 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
356                                uint64_t Address, const void *Decoder);
357 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
358                                uint64_t Address, const void *Decoder);
359 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
360                                 uint64_t Address, const void *Decoder);
361 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
362                                 uint64_t Address, const void *Decoder);
363 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
364                                 uint64_t Address, const void *Decoder);
365 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
366                                 uint64_t Address, const void *Decoder);
367 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
368                                 uint64_t Address, const void *Decoder);
369 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
370                                 uint64_t Address, const void *Decoder);
371 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
372                                 uint64_t Address, const void *Decoder);
373 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
374                                 uint64_t Address, const void *Decoder);
375 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
376                                 uint64_t Address, const void *Decoder);
377 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
378                                 uint64_t Address, const void *Decoder);
379 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
380                                 uint64_t Address, const void *Decoder);
381 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
382                                uint64_t Address, const void *Decoder);
383 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
384                                uint64_t Address, const void *Decoder);
385 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
386                                 uint64_t Address, const void *Decoder);
387 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
388                                 uint64_t Address, const void *Decoder);
389 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
390                                 uint64_t Address, const void *Decoder);
391 
392 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
393                                 uint64_t Address, const void *Decoder);
394 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
395                                 uint64_t Address, const void *Decoder);
396 #include "ARMGenDisassemblerTables.inc"
397 
createARMDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)398 static MCDisassembler *createARMDisassembler(const Target &T,
399                                              const MCSubtargetInfo &STI,
400                                              MCContext &Ctx) {
401   return new ARMDisassembler(STI, Ctx);
402 }
403 
createThumbDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)404 static MCDisassembler *createThumbDisassembler(const Target &T,
405                                                const MCSubtargetInfo &STI,
406                                                MCContext &Ctx) {
407   return new ThumbDisassembler(STI, Ctx);
408 }
409 
410 // Post-decoding checks
checkDecodedInstruction(MCInst & MI,uint64_t & Size,uint64_t Address,raw_ostream & OS,raw_ostream & CS,uint32_t Insn,DecodeStatus Result)411 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
412                                             uint64_t Address, raw_ostream &OS,
413                                             raw_ostream &CS,
414                                             uint32_t Insn,
415                                             DecodeStatus Result)
416 {
417   switch (MI.getOpcode()) {
418     case ARM::HVC: {
419       // HVC is undefined if condition = 0xf otherwise upredictable
420       // if condition != 0xe
421       uint32_t Cond = (Insn >> 28) & 0xF;
422       if (Cond == 0xF)
423         return MCDisassembler::Fail;
424       if (Cond != 0xE)
425         return MCDisassembler::SoftFail;
426       return Result;
427     }
428     default: return Result;
429   }
430 }
431 
getInstruction(MCInst & MI,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & OS,raw_ostream & CS) const432 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
433                                              ArrayRef<uint8_t> Bytes,
434                                              uint64_t Address, raw_ostream &OS,
435                                              raw_ostream &CS) const {
436   CommentStream = &CS;
437 
438   assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
439          "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
440          "mode!");
441 
442   // We want to read exactly 4 bytes of data.
443   if (Bytes.size() < 4) {
444     Size = 0;
445     return MCDisassembler::Fail;
446   }
447 
448   // Encoded as a small-endian 32-bit word in the stream.
449   uint32_t Insn =
450       (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
451 
452   // Calling the auto-generated decoder function.
453   DecodeStatus Result =
454       decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
455   if (Result != MCDisassembler::Fail) {
456     Size = 4;
457     return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
458   }
459 
460   // VFP and NEON instructions, similarly, are shared between ARM
461   // and Thumb modes.
462   MI.clear();
463   Result = decodeInstruction(DecoderTableVFP32, MI, Insn, Address, this, STI);
464   if (Result != MCDisassembler::Fail) {
465     Size = 4;
466     return Result;
467   }
468 
469   MI.clear();
470   Result = decodeInstruction(DecoderTableVFPV832, MI, Insn, Address, this, STI);
471   if (Result != MCDisassembler::Fail) {
472     Size = 4;
473     return Result;
474   }
475 
476   MI.clear();
477   Result =
478       decodeInstruction(DecoderTableNEONData32, MI, Insn, Address, this, STI);
479   if (Result != MCDisassembler::Fail) {
480     Size = 4;
481     // Add a fake predicate operand, because we share these instruction
482     // definitions with Thumb2 where these instructions are predicable.
483     if (!DecodePredicateOperand(MI, 0xE, Address, this))
484       return MCDisassembler::Fail;
485     return Result;
486   }
487 
488   MI.clear();
489   Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, Insn, Address,
490                              this, STI);
491   if (Result != MCDisassembler::Fail) {
492     Size = 4;
493     // Add a fake predicate operand, because we share these instruction
494     // definitions with Thumb2 where these instructions are predicable.
495     if (!DecodePredicateOperand(MI, 0xE, Address, this))
496       return MCDisassembler::Fail;
497     return Result;
498   }
499 
500   MI.clear();
501   Result =
502       decodeInstruction(DecoderTableNEONDup32, MI, Insn, Address, this, STI);
503   if (Result != MCDisassembler::Fail) {
504     Size = 4;
505     // Add a fake predicate operand, because we share these instruction
506     // definitions with Thumb2 where these instructions are predicable.
507     if (!DecodePredicateOperand(MI, 0xE, Address, this))
508       return MCDisassembler::Fail;
509     return Result;
510   }
511 
512   MI.clear();
513   Result =
514       decodeInstruction(DecoderTablev8NEON32, MI, Insn, Address, this, STI);
515   if (Result != MCDisassembler::Fail) {
516     Size = 4;
517     return Result;
518   }
519 
520   MI.clear();
521   Result =
522       decodeInstruction(DecoderTablev8Crypto32, MI, Insn, Address, this, STI);
523   if (Result != MCDisassembler::Fail) {
524     Size = 4;
525     return Result;
526   }
527 
528   MI.clear();
529   Size = 0;
530   return MCDisassembler::Fail;
531 }
532 
533 namespace llvm {
534 extern const MCInstrDesc ARMInsts[];
535 }
536 
537 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
538 /// immediate Value in the MCInst.  The immediate Value has had any PC
539 /// adjustment made by the caller.  If the instruction is a branch instruction
540 /// then isBranch is true, else false.  If the getOpInfo() function was set as
541 /// part of the setupForSymbolicDisassembly() call then that function is called
542 /// to get any symbolic information at the Address for this instruction.  If
543 /// that returns non-zero then the symbolic information it returns is used to
544 /// create an MCExpr and that is added as an operand to the MCInst.  If
545 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
546 /// Value is done and if a symbol is found an MCExpr is created with that, else
547 /// an MCExpr with Value is created.  This function returns true if it adds an
548 /// operand to the MCInst and false otherwise.
tryAddingSymbolicOperand(uint64_t Address,int32_t Value,bool isBranch,uint64_t InstSize,MCInst & MI,const void * Decoder)549 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
550                                      bool isBranch, uint64_t InstSize,
551                                      MCInst &MI, const void *Decoder) {
552   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
553   // FIXME: Does it make sense for value to be negative?
554   return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
555                                        /* Offset */ 0, InstSize);
556 }
557 
558 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
559 /// referenced by a load instruction with the base register that is the Pc.
560 /// These can often be values in a literal pool near the Address of the
561 /// instruction.  The Address of the instruction and its immediate Value are
562 /// used as a possible literal pool entry.  The SymbolLookUp call back will
563 /// return the name of a symbol referenced by the literal pool's entry if
564 /// the referenced address is that of a symbol.  Or it will return a pointer to
565 /// a literal 'C' string if the referenced address of the literal pool's entry
566 /// is an address into a section with 'C' string literals.
tryAddingPcLoadReferenceComment(uint64_t Address,int Value,const void * Decoder)567 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
568                                             const void *Decoder) {
569   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
570   Dis->tryAddingPcLoadReferenceComment(Value, Address);
571 }
572 
573 // Thumb1 instructions don't have explicit S bits.  Rather, they
574 // implicitly set CPSR.  Since it's not represented in the encoding, the
575 // auto-generated decoder won't inject the CPSR operand.  We need to fix
576 // that as a post-pass.
AddThumb1SBit(MCInst & MI,bool InITBlock)577 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
578   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
579   unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
580   MCInst::iterator I = MI.begin();
581   for (unsigned i = 0; i < NumOps; ++i, ++I) {
582     if (I == MI.end()) break;
583     if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
584       if (i > 0 && OpInfo[i-1].isPredicate()) continue;
585       MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
586       return;
587     }
588   }
589 
590   MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
591 }
592 
593 // Most Thumb instructions don't have explicit predicates in the
594 // encoding, but rather get their predicates from IT context.  We need
595 // to fix up the predicate operands using this context information as a
596 // post-pass.
597 MCDisassembler::DecodeStatus
AddThumbPredicate(MCInst & MI) const598 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
599   MCDisassembler::DecodeStatus S = Success;
600 
601   // A few instructions actually have predicates encoded in them.  Don't
602   // try to overwrite it if we're seeing one of those.
603   switch (MI.getOpcode()) {
604     case ARM::tBcc:
605     case ARM::t2Bcc:
606     case ARM::tCBZ:
607     case ARM::tCBNZ:
608     case ARM::tCPS:
609     case ARM::t2CPS3p:
610     case ARM::t2CPS2p:
611     case ARM::t2CPS1p:
612     case ARM::tMOVSr:
613     case ARM::tSETEND:
614       // Some instructions (mostly conditional branches) are not
615       // allowed in IT blocks.
616       if (ITBlock.instrInITBlock())
617         S = SoftFail;
618       else
619         return Success;
620       break;
621     case ARM::tB:
622     case ARM::t2B:
623     case ARM::t2TBB:
624     case ARM::t2TBH:
625       // Some instructions (mostly unconditional branches) can
626       // only appears at the end of, or outside of, an IT.
627       if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
628         S = SoftFail;
629       break;
630     default:
631       break;
632   }
633 
634   // If we're in an IT block, base the predicate on that.  Otherwise,
635   // assume a predicate of AL.
636   unsigned CC;
637   CC = ITBlock.getITCC();
638   if (CC == 0xF)
639     CC = ARMCC::AL;
640   if (ITBlock.instrInITBlock())
641     ITBlock.advanceITState();
642 
643   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
644   unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
645   MCInst::iterator I = MI.begin();
646   for (unsigned i = 0; i < NumOps; ++i, ++I) {
647     if (I == MI.end()) break;
648     if (OpInfo[i].isPredicate()) {
649       I = MI.insert(I, MCOperand::CreateImm(CC));
650       ++I;
651       if (CC == ARMCC::AL)
652         MI.insert(I, MCOperand::CreateReg(0));
653       else
654         MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
655       return S;
656     }
657   }
658 
659   I = MI.insert(I, MCOperand::CreateImm(CC));
660   ++I;
661   if (CC == ARMCC::AL)
662     MI.insert(I, MCOperand::CreateReg(0));
663   else
664     MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
665 
666   return S;
667 }
668 
669 // Thumb VFP instructions are a special case.  Because we share their
670 // encodings between ARM and Thumb modes, and they are predicable in ARM
671 // mode, the auto-generated decoder will give them an (incorrect)
672 // predicate operand.  We need to rewrite these operands based on the IT
673 // context as a post-pass.
UpdateThumbVFPPredicate(MCInst & MI) const674 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
675   unsigned CC;
676   CC = ITBlock.getITCC();
677   if (ITBlock.instrInITBlock())
678     ITBlock.advanceITState();
679 
680   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
681   MCInst::iterator I = MI.begin();
682   unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
683   for (unsigned i = 0; i < NumOps; ++i, ++I) {
684     if (OpInfo[i].isPredicate() ) {
685       I->setImm(CC);
686       ++I;
687       if (CC == ARMCC::AL)
688         I->setReg(0);
689       else
690         I->setReg(ARM::CPSR);
691       return;
692     }
693   }
694 }
695 
getInstruction(MCInst & MI,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & OS,raw_ostream & CS) const696 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
697                                                ArrayRef<uint8_t> Bytes,
698                                                uint64_t Address,
699                                                raw_ostream &OS,
700                                                raw_ostream &CS) const {
701   CommentStream = &CS;
702 
703   assert((STI.getFeatureBits() & ARM::ModeThumb) &&
704          "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
705 
706   // We want to read exactly 2 bytes of data.
707   if (Bytes.size() < 2) {
708     Size = 0;
709     return MCDisassembler::Fail;
710   }
711 
712   uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
713   DecodeStatus Result =
714       decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
715   if (Result != MCDisassembler::Fail) {
716     Size = 2;
717     Check(Result, AddThumbPredicate(MI));
718     return Result;
719   }
720 
721   MI.clear();
722   Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
723                              STI);
724   if (Result) {
725     Size = 2;
726     bool InITBlock = ITBlock.instrInITBlock();
727     Check(Result, AddThumbPredicate(MI));
728     AddThumb1SBit(MI, InITBlock);
729     return Result;
730   }
731 
732   MI.clear();
733   Result =
734       decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
735   if (Result != MCDisassembler::Fail) {
736     Size = 2;
737 
738     // Nested IT blocks are UNPREDICTABLE.  Must be checked before we add
739     // the Thumb predicate.
740     if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
741       Result = MCDisassembler::SoftFail;
742 
743     Check(Result, AddThumbPredicate(MI));
744 
745     // If we find an IT instruction, we need to parse its condition
746     // code and mask operands so that we can apply them correctly
747     // to the subsequent instructions.
748     if (MI.getOpcode() == ARM::t2IT) {
749 
750       unsigned Firstcond = MI.getOperand(0).getImm();
751       unsigned Mask = MI.getOperand(1).getImm();
752       ITBlock.setITState(Firstcond, Mask);
753     }
754 
755     return Result;
756   }
757 
758   // We want to read exactly 4 bytes of data.
759   if (Bytes.size() < 4) {
760     Size = 0;
761     return MCDisassembler::Fail;
762   }
763 
764   uint32_t Insn32 =
765       (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
766   MI.clear();
767   Result =
768       decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
769   if (Result != MCDisassembler::Fail) {
770     Size = 4;
771     bool InITBlock = ITBlock.instrInITBlock();
772     Check(Result, AddThumbPredicate(MI));
773     AddThumb1SBit(MI, InITBlock);
774     return Result;
775   }
776 
777   MI.clear();
778   Result =
779       decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
780   if (Result != MCDisassembler::Fail) {
781     Size = 4;
782     Check(Result, AddThumbPredicate(MI));
783     return Result;
784   }
785 
786   if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
787     MI.clear();
788     Result =
789         decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
790     if (Result != MCDisassembler::Fail) {
791       Size = 4;
792       UpdateThumbVFPPredicate(MI);
793       return Result;
794     }
795   }
796 
797   MI.clear();
798   Result =
799       decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
800   if (Result != MCDisassembler::Fail) {
801     Size = 4;
802     return Result;
803   }
804 
805   if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
806     MI.clear();
807     Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
808                                STI);
809     if (Result != MCDisassembler::Fail) {
810       Size = 4;
811       Check(Result, AddThumbPredicate(MI));
812       return Result;
813     }
814   }
815 
816   if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
817     MI.clear();
818     uint32_t NEONLdStInsn = Insn32;
819     NEONLdStInsn &= 0xF0FFFFFF;
820     NEONLdStInsn |= 0x04000000;
821     Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
822                                Address, this, STI);
823     if (Result != MCDisassembler::Fail) {
824       Size = 4;
825       Check(Result, AddThumbPredicate(MI));
826       return Result;
827     }
828   }
829 
830   if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
831     MI.clear();
832     uint32_t NEONDataInsn = Insn32;
833     NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
834     NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
835     NEONDataInsn |= 0x12000000; // Set bits 28 and 25
836     Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
837                                Address, this, STI);
838     if (Result != MCDisassembler::Fail) {
839       Size = 4;
840       Check(Result, AddThumbPredicate(MI));
841       return Result;
842     }
843 
844     MI.clear();
845     uint32_t NEONCryptoInsn = Insn32;
846     NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
847     NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
848     NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
849     Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
850                                Address, this, STI);
851     if (Result != MCDisassembler::Fail) {
852       Size = 4;
853       return Result;
854     }
855 
856     MI.clear();
857     uint32_t NEONv8Insn = Insn32;
858     NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
859     Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
860                                this, STI);
861     if (Result != MCDisassembler::Fail) {
862       Size = 4;
863       return Result;
864     }
865   }
866 
867   MI.clear();
868   Size = 0;
869   return MCDisassembler::Fail;
870 }
871 
872 
LLVMInitializeARMDisassembler()873 extern "C" void LLVMInitializeARMDisassembler() {
874   TargetRegistry::RegisterMCDisassembler(TheARMLETarget,
875                                          createARMDisassembler);
876   TargetRegistry::RegisterMCDisassembler(TheARMBETarget,
877                                          createARMDisassembler);
878   TargetRegistry::RegisterMCDisassembler(TheThumbLETarget,
879                                          createThumbDisassembler);
880   TargetRegistry::RegisterMCDisassembler(TheThumbBETarget,
881                                          createThumbDisassembler);
882 }
883 
884 static const uint16_t GPRDecoderTable[] = {
885   ARM::R0, ARM::R1, ARM::R2, ARM::R3,
886   ARM::R4, ARM::R5, ARM::R6, ARM::R7,
887   ARM::R8, ARM::R9, ARM::R10, ARM::R11,
888   ARM::R12, ARM::SP, ARM::LR, ARM::PC
889 };
890 
DecodeGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)891 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
892                                    uint64_t Address, const void *Decoder) {
893   if (RegNo > 15)
894     return MCDisassembler::Fail;
895 
896   unsigned Register = GPRDecoderTable[RegNo];
897   Inst.addOperand(MCOperand::CreateReg(Register));
898   return MCDisassembler::Success;
899 }
900 
901 static DecodeStatus
DecodeGPRnopcRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)902 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
903                            uint64_t Address, const void *Decoder) {
904   DecodeStatus S = MCDisassembler::Success;
905 
906   if (RegNo == 15)
907     S = MCDisassembler::SoftFail;
908 
909   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
910 
911   return S;
912 }
913 
914 static DecodeStatus
DecodeGPRwithAPSRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)915 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
916                                uint64_t Address, const void *Decoder) {
917   DecodeStatus S = MCDisassembler::Success;
918 
919   if (RegNo == 15)
920   {
921     Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
922     return MCDisassembler::Success;
923   }
924 
925   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
926   return S;
927 }
928 
DecodetGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)929 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
930                                    uint64_t Address, const void *Decoder) {
931   if (RegNo > 7)
932     return MCDisassembler::Fail;
933   return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
934 }
935 
936 static const uint16_t GPRPairDecoderTable[] = {
937   ARM::R0_R1, ARM::R2_R3,   ARM::R4_R5,  ARM::R6_R7,
938   ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
939 };
940 
DecodeGPRPairRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)941 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
942                                    uint64_t Address, const void *Decoder) {
943   DecodeStatus S = MCDisassembler::Success;
944 
945   if (RegNo > 13)
946     return MCDisassembler::Fail;
947 
948   if ((RegNo & 1) || RegNo == 0xe)
949      S = MCDisassembler::SoftFail;
950 
951   unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
952   Inst.addOperand(MCOperand::CreateReg(RegisterPair));
953   return S;
954 }
955 
DecodetcGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)956 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
957                                    uint64_t Address, const void *Decoder) {
958   unsigned Register = 0;
959   switch (RegNo) {
960     case 0:
961       Register = ARM::R0;
962       break;
963     case 1:
964       Register = ARM::R1;
965       break;
966     case 2:
967       Register = ARM::R2;
968       break;
969     case 3:
970       Register = ARM::R3;
971       break;
972     case 9:
973       Register = ARM::R9;
974       break;
975     case 12:
976       Register = ARM::R12;
977       break;
978     default:
979       return MCDisassembler::Fail;
980     }
981 
982   Inst.addOperand(MCOperand::CreateReg(Register));
983   return MCDisassembler::Success;
984 }
985 
DecoderGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)986 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
987                                    uint64_t Address, const void *Decoder) {
988   DecodeStatus S = MCDisassembler::Success;
989   if (RegNo == 13 || RegNo == 15)
990     S = MCDisassembler::SoftFail;
991   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
992   return S;
993 }
994 
995 static const uint16_t SPRDecoderTable[] = {
996      ARM::S0,  ARM::S1,  ARM::S2,  ARM::S3,
997      ARM::S4,  ARM::S5,  ARM::S6,  ARM::S7,
998      ARM::S8,  ARM::S9, ARM::S10, ARM::S11,
999     ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1000     ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1001     ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1002     ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1003     ARM::S28, ARM::S29, ARM::S30, ARM::S31
1004 };
1005 
DecodeSPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1006 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
1007                                    uint64_t Address, const void *Decoder) {
1008   if (RegNo > 31)
1009     return MCDisassembler::Fail;
1010 
1011   unsigned Register = SPRDecoderTable[RegNo];
1012   Inst.addOperand(MCOperand::CreateReg(Register));
1013   return MCDisassembler::Success;
1014 }
1015 
1016 static const uint16_t DPRDecoderTable[] = {
1017      ARM::D0,  ARM::D1,  ARM::D2,  ARM::D3,
1018      ARM::D4,  ARM::D5,  ARM::D6,  ARM::D7,
1019      ARM::D8,  ARM::D9, ARM::D10, ARM::D11,
1020     ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1021     ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1022     ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1023     ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1024     ARM::D28, ARM::D29, ARM::D30, ARM::D31
1025 };
1026 
DecodeDPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1027 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1028                                    uint64_t Address, const void *Decoder) {
1029   uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
1030                                                           .getFeatureBits();
1031   bool hasD16 = featureBits & ARM::FeatureD16;
1032 
1033   if (RegNo > 31 || (hasD16 && RegNo > 15))
1034     return MCDisassembler::Fail;
1035 
1036   unsigned Register = DPRDecoderTable[RegNo];
1037   Inst.addOperand(MCOperand::CreateReg(Register));
1038   return MCDisassembler::Success;
1039 }
1040 
DecodeDPR_8RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1041 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1042                                    uint64_t Address, const void *Decoder) {
1043   if (RegNo > 7)
1044     return MCDisassembler::Fail;
1045   return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1046 }
1047 
1048 static DecodeStatus
DecodeDPR_VFP2RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1049 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1050                             uint64_t Address, const void *Decoder) {
1051   if (RegNo > 15)
1052     return MCDisassembler::Fail;
1053   return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1054 }
1055 
1056 static const uint16_t QPRDecoderTable[] = {
1057      ARM::Q0,  ARM::Q1,  ARM::Q2,  ARM::Q3,
1058      ARM::Q4,  ARM::Q5,  ARM::Q6,  ARM::Q7,
1059      ARM::Q8,  ARM::Q9, ARM::Q10, ARM::Q11,
1060     ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1061 };
1062 
1063 
DecodeQPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1064 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1065                                    uint64_t Address, const void *Decoder) {
1066   if (RegNo > 31 || (RegNo & 1) != 0)
1067     return MCDisassembler::Fail;
1068   RegNo >>= 1;
1069 
1070   unsigned Register = QPRDecoderTable[RegNo];
1071   Inst.addOperand(MCOperand::CreateReg(Register));
1072   return MCDisassembler::Success;
1073 }
1074 
1075 static const uint16_t DPairDecoderTable[] = {
1076   ARM::Q0,  ARM::D1_D2,   ARM::Q1,  ARM::D3_D4,   ARM::Q2,  ARM::D5_D6,
1077   ARM::Q3,  ARM::D7_D8,   ARM::Q4,  ARM::D9_D10,  ARM::Q5,  ARM::D11_D12,
1078   ARM::Q6,  ARM::D13_D14, ARM::Q7,  ARM::D15_D16, ARM::Q8,  ARM::D17_D18,
1079   ARM::Q9,  ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1080   ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1081   ARM::Q15
1082 };
1083 
DecodeDPairRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1084 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1085                                    uint64_t Address, const void *Decoder) {
1086   if (RegNo > 30)
1087     return MCDisassembler::Fail;
1088 
1089   unsigned Register = DPairDecoderTable[RegNo];
1090   Inst.addOperand(MCOperand::CreateReg(Register));
1091   return MCDisassembler::Success;
1092 }
1093 
1094 static const uint16_t DPairSpacedDecoderTable[] = {
1095   ARM::D0_D2,   ARM::D1_D3,   ARM::D2_D4,   ARM::D3_D5,
1096   ARM::D4_D6,   ARM::D5_D7,   ARM::D6_D8,   ARM::D7_D9,
1097   ARM::D8_D10,  ARM::D9_D11,  ARM::D10_D12, ARM::D11_D13,
1098   ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1099   ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1100   ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1101   ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1102   ARM::D28_D30, ARM::D29_D31
1103 };
1104 
DecodeDPairSpacedRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1105 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1106                                                    unsigned RegNo,
1107                                                    uint64_t Address,
1108                                                    const void *Decoder) {
1109   if (RegNo > 29)
1110     return MCDisassembler::Fail;
1111 
1112   unsigned Register = DPairSpacedDecoderTable[RegNo];
1113   Inst.addOperand(MCOperand::CreateReg(Register));
1114   return MCDisassembler::Success;
1115 }
1116 
DecodePredicateOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1117 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1118                                uint64_t Address, const void *Decoder) {
1119   if (Val == 0xF) return MCDisassembler::Fail;
1120   // AL predicate is not allowed on Thumb1 branches.
1121   if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1122     return MCDisassembler::Fail;
1123   Inst.addOperand(MCOperand::CreateImm(Val));
1124   if (Val == ARMCC::AL) {
1125     Inst.addOperand(MCOperand::CreateReg(0));
1126   } else
1127     Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1128   return MCDisassembler::Success;
1129 }
1130 
DecodeCCOutOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1131 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1132                                uint64_t Address, const void *Decoder) {
1133   if (Val)
1134     Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1135   else
1136     Inst.addOperand(MCOperand::CreateReg(0));
1137   return MCDisassembler::Success;
1138 }
1139 
DecodeSORegImmOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1140 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1141                                uint64_t Address, const void *Decoder) {
1142   DecodeStatus S = MCDisassembler::Success;
1143 
1144   unsigned Rm = fieldFromInstruction(Val, 0, 4);
1145   unsigned type = fieldFromInstruction(Val, 5, 2);
1146   unsigned imm = fieldFromInstruction(Val, 7, 5);
1147 
1148   // Register-immediate
1149   if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1150     return MCDisassembler::Fail;
1151 
1152   ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1153   switch (type) {
1154     case 0:
1155       Shift = ARM_AM::lsl;
1156       break;
1157     case 1:
1158       Shift = ARM_AM::lsr;
1159       break;
1160     case 2:
1161       Shift = ARM_AM::asr;
1162       break;
1163     case 3:
1164       Shift = ARM_AM::ror;
1165       break;
1166   }
1167 
1168   if (Shift == ARM_AM::ror && imm == 0)
1169     Shift = ARM_AM::rrx;
1170 
1171   unsigned Op = Shift | (imm << 3);
1172   Inst.addOperand(MCOperand::CreateImm(Op));
1173 
1174   return S;
1175 }
1176 
DecodeSORegRegOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1177 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1178                                uint64_t Address, const void *Decoder) {
1179   DecodeStatus S = MCDisassembler::Success;
1180 
1181   unsigned Rm = fieldFromInstruction(Val, 0, 4);
1182   unsigned type = fieldFromInstruction(Val, 5, 2);
1183   unsigned Rs = fieldFromInstruction(Val, 8, 4);
1184 
1185   // Register-register
1186   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1187     return MCDisassembler::Fail;
1188   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1189     return MCDisassembler::Fail;
1190 
1191   ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1192   switch (type) {
1193     case 0:
1194       Shift = ARM_AM::lsl;
1195       break;
1196     case 1:
1197       Shift = ARM_AM::lsr;
1198       break;
1199     case 2:
1200       Shift = ARM_AM::asr;
1201       break;
1202     case 3:
1203       Shift = ARM_AM::ror;
1204       break;
1205   }
1206 
1207   Inst.addOperand(MCOperand::CreateImm(Shift));
1208 
1209   return S;
1210 }
1211 
DecodeRegListOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1212 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1213                                  uint64_t Address, const void *Decoder) {
1214   DecodeStatus S = MCDisassembler::Success;
1215 
1216   bool NeedDisjointWriteback = false;
1217   unsigned WritebackReg = 0;
1218   switch (Inst.getOpcode()) {
1219   default:
1220     break;
1221   case ARM::LDMIA_UPD:
1222   case ARM::LDMDB_UPD:
1223   case ARM::LDMIB_UPD:
1224   case ARM::LDMDA_UPD:
1225   case ARM::t2LDMIA_UPD:
1226   case ARM::t2LDMDB_UPD:
1227   case ARM::t2STMIA_UPD:
1228   case ARM::t2STMDB_UPD:
1229     NeedDisjointWriteback = true;
1230     WritebackReg = Inst.getOperand(0).getReg();
1231     break;
1232   }
1233 
1234   // Empty register lists are not allowed.
1235   if (Val == 0) return MCDisassembler::Fail;
1236   for (unsigned i = 0; i < 16; ++i) {
1237     if (Val & (1 << i)) {
1238       if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1239         return MCDisassembler::Fail;
1240       // Writeback not allowed if Rn is in the target list.
1241       if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1242         Check(S, MCDisassembler::SoftFail);
1243     }
1244   }
1245 
1246   return S;
1247 }
1248 
DecodeSPRRegListOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1249 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1250                                  uint64_t Address, const void *Decoder) {
1251   DecodeStatus S = MCDisassembler::Success;
1252 
1253   unsigned Vd = fieldFromInstruction(Val, 8, 5);
1254   unsigned regs = fieldFromInstruction(Val, 0, 8);
1255 
1256   // In case of unpredictable encoding, tweak the operands.
1257   if (regs == 0 || (Vd + regs) > 32) {
1258     regs = Vd + regs > 32 ? 32 - Vd : regs;
1259     regs = std::max( 1u, regs);
1260     S = MCDisassembler::SoftFail;
1261   }
1262 
1263   if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1264     return MCDisassembler::Fail;
1265   for (unsigned i = 0; i < (regs - 1); ++i) {
1266     if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1267       return MCDisassembler::Fail;
1268   }
1269 
1270   return S;
1271 }
1272 
DecodeDPRRegListOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1273 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1274                                  uint64_t Address, const void *Decoder) {
1275   DecodeStatus S = MCDisassembler::Success;
1276 
1277   unsigned Vd = fieldFromInstruction(Val, 8, 5);
1278   unsigned regs = fieldFromInstruction(Val, 1, 7);
1279 
1280   // In case of unpredictable encoding, tweak the operands.
1281   if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1282     regs = Vd + regs > 32 ? 32 - Vd : regs;
1283     regs = std::max( 1u, regs);
1284     regs = std::min(16u, regs);
1285     S = MCDisassembler::SoftFail;
1286   }
1287 
1288   if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1289       return MCDisassembler::Fail;
1290   for (unsigned i = 0; i < (regs - 1); ++i) {
1291     if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1292       return MCDisassembler::Fail;
1293   }
1294 
1295   return S;
1296 }
1297 
DecodeBitfieldMaskOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1298 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1299                                       uint64_t Address, const void *Decoder) {
1300   // This operand encodes a mask of contiguous zeros between a specified MSB
1301   // and LSB.  To decode it, we create the mask of all bits MSB-and-lower,
1302   // the mask of all bits LSB-and-lower, and then xor them to create
1303   // the mask of that's all ones on [msb, lsb].  Finally we not it to
1304   // create the final mask.
1305   unsigned msb = fieldFromInstruction(Val, 5, 5);
1306   unsigned lsb = fieldFromInstruction(Val, 0, 5);
1307 
1308   DecodeStatus S = MCDisassembler::Success;
1309   if (lsb > msb) {
1310     Check(S, MCDisassembler::SoftFail);
1311     // The check above will cause the warning for the "potentially undefined
1312     // instruction encoding" but we can't build a bad MCOperand value here
1313     // with a lsb > msb or else printing the MCInst will cause a crash.
1314     lsb = msb;
1315   }
1316 
1317   uint32_t msb_mask = 0xFFFFFFFF;
1318   if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1319   uint32_t lsb_mask = (1U << lsb) - 1;
1320 
1321   Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1322   return S;
1323 }
1324 
DecodeCopMemInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1325 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1326                                   uint64_t Address, const void *Decoder) {
1327   DecodeStatus S = MCDisassembler::Success;
1328 
1329   unsigned pred = fieldFromInstruction(Insn, 28, 4);
1330   unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1331   unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1332   unsigned imm = fieldFromInstruction(Insn, 0, 8);
1333   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1334   unsigned U = fieldFromInstruction(Insn, 23, 1);
1335 
1336   switch (Inst.getOpcode()) {
1337     case ARM::LDC_OFFSET:
1338     case ARM::LDC_PRE:
1339     case ARM::LDC_POST:
1340     case ARM::LDC_OPTION:
1341     case ARM::LDCL_OFFSET:
1342     case ARM::LDCL_PRE:
1343     case ARM::LDCL_POST:
1344     case ARM::LDCL_OPTION:
1345     case ARM::STC_OFFSET:
1346     case ARM::STC_PRE:
1347     case ARM::STC_POST:
1348     case ARM::STC_OPTION:
1349     case ARM::STCL_OFFSET:
1350     case ARM::STCL_PRE:
1351     case ARM::STCL_POST:
1352     case ARM::STCL_OPTION:
1353     case ARM::t2LDC_OFFSET:
1354     case ARM::t2LDC_PRE:
1355     case ARM::t2LDC_POST:
1356     case ARM::t2LDC_OPTION:
1357     case ARM::t2LDCL_OFFSET:
1358     case ARM::t2LDCL_PRE:
1359     case ARM::t2LDCL_POST:
1360     case ARM::t2LDCL_OPTION:
1361     case ARM::t2STC_OFFSET:
1362     case ARM::t2STC_PRE:
1363     case ARM::t2STC_POST:
1364     case ARM::t2STC_OPTION:
1365     case ARM::t2STCL_OFFSET:
1366     case ARM::t2STCL_PRE:
1367     case ARM::t2STCL_POST:
1368     case ARM::t2STCL_OPTION:
1369       if (coproc == 0xA || coproc == 0xB)
1370         return MCDisassembler::Fail;
1371       break;
1372     default:
1373       break;
1374   }
1375 
1376   uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
1377                                                           .getFeatureBits();
1378   if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
1379     return MCDisassembler::Fail;
1380 
1381   Inst.addOperand(MCOperand::CreateImm(coproc));
1382   Inst.addOperand(MCOperand::CreateImm(CRd));
1383   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1384     return MCDisassembler::Fail;
1385 
1386   switch (Inst.getOpcode()) {
1387     case ARM::t2LDC2_OFFSET:
1388     case ARM::t2LDC2L_OFFSET:
1389     case ARM::t2LDC2_PRE:
1390     case ARM::t2LDC2L_PRE:
1391     case ARM::t2STC2_OFFSET:
1392     case ARM::t2STC2L_OFFSET:
1393     case ARM::t2STC2_PRE:
1394     case ARM::t2STC2L_PRE:
1395     case ARM::LDC2_OFFSET:
1396     case ARM::LDC2L_OFFSET:
1397     case ARM::LDC2_PRE:
1398     case ARM::LDC2L_PRE:
1399     case ARM::STC2_OFFSET:
1400     case ARM::STC2L_OFFSET:
1401     case ARM::STC2_PRE:
1402     case ARM::STC2L_PRE:
1403     case ARM::t2LDC_OFFSET:
1404     case ARM::t2LDCL_OFFSET:
1405     case ARM::t2LDC_PRE:
1406     case ARM::t2LDCL_PRE:
1407     case ARM::t2STC_OFFSET:
1408     case ARM::t2STCL_OFFSET:
1409     case ARM::t2STC_PRE:
1410     case ARM::t2STCL_PRE:
1411     case ARM::LDC_OFFSET:
1412     case ARM::LDCL_OFFSET:
1413     case ARM::LDC_PRE:
1414     case ARM::LDCL_PRE:
1415     case ARM::STC_OFFSET:
1416     case ARM::STCL_OFFSET:
1417     case ARM::STC_PRE:
1418     case ARM::STCL_PRE:
1419       imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1420       Inst.addOperand(MCOperand::CreateImm(imm));
1421       break;
1422     case ARM::t2LDC2_POST:
1423     case ARM::t2LDC2L_POST:
1424     case ARM::t2STC2_POST:
1425     case ARM::t2STC2L_POST:
1426     case ARM::LDC2_POST:
1427     case ARM::LDC2L_POST:
1428     case ARM::STC2_POST:
1429     case ARM::STC2L_POST:
1430     case ARM::t2LDC_POST:
1431     case ARM::t2LDCL_POST:
1432     case ARM::t2STC_POST:
1433     case ARM::t2STCL_POST:
1434     case ARM::LDC_POST:
1435     case ARM::LDCL_POST:
1436     case ARM::STC_POST:
1437     case ARM::STCL_POST:
1438       imm |= U << 8;
1439       // fall through.
1440     default:
1441       // The 'option' variant doesn't encode 'U' in the immediate since
1442       // the immediate is unsigned [0,255].
1443       Inst.addOperand(MCOperand::CreateImm(imm));
1444       break;
1445   }
1446 
1447   switch (Inst.getOpcode()) {
1448     case ARM::LDC_OFFSET:
1449     case ARM::LDC_PRE:
1450     case ARM::LDC_POST:
1451     case ARM::LDC_OPTION:
1452     case ARM::LDCL_OFFSET:
1453     case ARM::LDCL_PRE:
1454     case ARM::LDCL_POST:
1455     case ARM::LDCL_OPTION:
1456     case ARM::STC_OFFSET:
1457     case ARM::STC_PRE:
1458     case ARM::STC_POST:
1459     case ARM::STC_OPTION:
1460     case ARM::STCL_OFFSET:
1461     case ARM::STCL_PRE:
1462     case ARM::STCL_POST:
1463     case ARM::STCL_OPTION:
1464       if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1465         return MCDisassembler::Fail;
1466       break;
1467     default:
1468       break;
1469   }
1470 
1471   return S;
1472 }
1473 
1474 static DecodeStatus
DecodeAddrMode2IdxInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1475 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1476                               uint64_t Address, const void *Decoder) {
1477   DecodeStatus S = MCDisassembler::Success;
1478 
1479   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1480   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1481   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1482   unsigned imm = fieldFromInstruction(Insn, 0, 12);
1483   unsigned pred = fieldFromInstruction(Insn, 28, 4);
1484   unsigned reg = fieldFromInstruction(Insn, 25, 1);
1485   unsigned P = fieldFromInstruction(Insn, 24, 1);
1486   unsigned W = fieldFromInstruction(Insn, 21, 1);
1487 
1488   // On stores, the writeback operand precedes Rt.
1489   switch (Inst.getOpcode()) {
1490     case ARM::STR_POST_IMM:
1491     case ARM::STR_POST_REG:
1492     case ARM::STRB_POST_IMM:
1493     case ARM::STRB_POST_REG:
1494     case ARM::STRT_POST_REG:
1495     case ARM::STRT_POST_IMM:
1496     case ARM::STRBT_POST_REG:
1497     case ARM::STRBT_POST_IMM:
1498       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1499         return MCDisassembler::Fail;
1500       break;
1501     default:
1502       break;
1503   }
1504 
1505   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1506     return MCDisassembler::Fail;
1507 
1508   // On loads, the writeback operand comes after Rt.
1509   switch (Inst.getOpcode()) {
1510     case ARM::LDR_POST_IMM:
1511     case ARM::LDR_POST_REG:
1512     case ARM::LDRB_POST_IMM:
1513     case ARM::LDRB_POST_REG:
1514     case ARM::LDRBT_POST_REG:
1515     case ARM::LDRBT_POST_IMM:
1516     case ARM::LDRT_POST_REG:
1517     case ARM::LDRT_POST_IMM:
1518       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1519         return MCDisassembler::Fail;
1520       break;
1521     default:
1522       break;
1523   }
1524 
1525   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1526     return MCDisassembler::Fail;
1527 
1528   ARM_AM::AddrOpc Op = ARM_AM::add;
1529   if (!fieldFromInstruction(Insn, 23, 1))
1530     Op = ARM_AM::sub;
1531 
1532   bool writeback = (P == 0) || (W == 1);
1533   unsigned idx_mode = 0;
1534   if (P && writeback)
1535     idx_mode = ARMII::IndexModePre;
1536   else if (!P && writeback)
1537     idx_mode = ARMII::IndexModePost;
1538 
1539   if (writeback && (Rn == 15 || Rn == Rt))
1540     S = MCDisassembler::SoftFail; // UNPREDICTABLE
1541 
1542   if (reg) {
1543     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1544       return MCDisassembler::Fail;
1545     ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1546     switch( fieldFromInstruction(Insn, 5, 2)) {
1547       case 0:
1548         Opc = ARM_AM::lsl;
1549         break;
1550       case 1:
1551         Opc = ARM_AM::lsr;
1552         break;
1553       case 2:
1554         Opc = ARM_AM::asr;
1555         break;
1556       case 3:
1557         Opc = ARM_AM::ror;
1558         break;
1559       default:
1560         return MCDisassembler::Fail;
1561     }
1562     unsigned amt = fieldFromInstruction(Insn, 7, 5);
1563     if (Opc == ARM_AM::ror && amt == 0)
1564       Opc = ARM_AM::rrx;
1565     unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1566 
1567     Inst.addOperand(MCOperand::CreateImm(imm));
1568   } else {
1569     Inst.addOperand(MCOperand::CreateReg(0));
1570     unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1571     Inst.addOperand(MCOperand::CreateImm(tmp));
1572   }
1573 
1574   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1575     return MCDisassembler::Fail;
1576 
1577   return S;
1578 }
1579 
DecodeSORegMemOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1580 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1581                                   uint64_t Address, const void *Decoder) {
1582   DecodeStatus S = MCDisassembler::Success;
1583 
1584   unsigned Rn = fieldFromInstruction(Val, 13, 4);
1585   unsigned Rm = fieldFromInstruction(Val,  0, 4);
1586   unsigned type = fieldFromInstruction(Val, 5, 2);
1587   unsigned imm = fieldFromInstruction(Val, 7, 5);
1588   unsigned U = fieldFromInstruction(Val, 12, 1);
1589 
1590   ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1591   switch (type) {
1592     case 0:
1593       ShOp = ARM_AM::lsl;
1594       break;
1595     case 1:
1596       ShOp = ARM_AM::lsr;
1597       break;
1598     case 2:
1599       ShOp = ARM_AM::asr;
1600       break;
1601     case 3:
1602       ShOp = ARM_AM::ror;
1603       break;
1604   }
1605 
1606   if (ShOp == ARM_AM::ror && imm == 0)
1607     ShOp = ARM_AM::rrx;
1608 
1609   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1610     return MCDisassembler::Fail;
1611   if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1612     return MCDisassembler::Fail;
1613   unsigned shift;
1614   if (U)
1615     shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1616   else
1617     shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1618   Inst.addOperand(MCOperand::CreateImm(shift));
1619 
1620   return S;
1621 }
1622 
1623 static DecodeStatus
DecodeAddrMode3Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1624 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1625                            uint64_t Address, const void *Decoder) {
1626   DecodeStatus S = MCDisassembler::Success;
1627 
1628   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1629   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1630   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1631   unsigned type = fieldFromInstruction(Insn, 22, 1);
1632   unsigned imm = fieldFromInstruction(Insn, 8, 4);
1633   unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1634   unsigned pred = fieldFromInstruction(Insn, 28, 4);
1635   unsigned W = fieldFromInstruction(Insn, 21, 1);
1636   unsigned P = fieldFromInstruction(Insn, 24, 1);
1637   unsigned Rt2 = Rt + 1;
1638 
1639   bool writeback = (W == 1) | (P == 0);
1640 
1641   // For {LD,ST}RD, Rt must be even, else undefined.
1642   switch (Inst.getOpcode()) {
1643     case ARM::STRD:
1644     case ARM::STRD_PRE:
1645     case ARM::STRD_POST:
1646     case ARM::LDRD:
1647     case ARM::LDRD_PRE:
1648     case ARM::LDRD_POST:
1649       if (Rt & 0x1) S = MCDisassembler::SoftFail;
1650       break;
1651     default:
1652       break;
1653   }
1654   switch (Inst.getOpcode()) {
1655     case ARM::STRD:
1656     case ARM::STRD_PRE:
1657     case ARM::STRD_POST:
1658       if (P == 0 && W == 1)
1659         S = MCDisassembler::SoftFail;
1660 
1661       if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1662         S = MCDisassembler::SoftFail;
1663       if (type && Rm == 15)
1664         S = MCDisassembler::SoftFail;
1665       if (Rt2 == 15)
1666         S = MCDisassembler::SoftFail;
1667       if (!type && fieldFromInstruction(Insn, 8, 4))
1668         S = MCDisassembler::SoftFail;
1669       break;
1670     case ARM::STRH:
1671     case ARM::STRH_PRE:
1672     case ARM::STRH_POST:
1673       if (Rt == 15)
1674         S = MCDisassembler::SoftFail;
1675       if (writeback && (Rn == 15 || Rn == Rt))
1676         S = MCDisassembler::SoftFail;
1677       if (!type && Rm == 15)
1678         S = MCDisassembler::SoftFail;
1679       break;
1680     case ARM::LDRD:
1681     case ARM::LDRD_PRE:
1682     case ARM::LDRD_POST:
1683       if (type && Rn == 15){
1684         if (Rt2 == 15)
1685           S = MCDisassembler::SoftFail;
1686         break;
1687       }
1688       if (P == 0 && W == 1)
1689         S = MCDisassembler::SoftFail;
1690       if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1691         S = MCDisassembler::SoftFail;
1692       if (!type && writeback && Rn == 15)
1693         S = MCDisassembler::SoftFail;
1694       if (writeback && (Rn == Rt || Rn == Rt2))
1695         S = MCDisassembler::SoftFail;
1696       break;
1697     case ARM::LDRH:
1698     case ARM::LDRH_PRE:
1699     case ARM::LDRH_POST:
1700       if (type && Rn == 15){
1701         if (Rt == 15)
1702           S = MCDisassembler::SoftFail;
1703         break;
1704       }
1705       if (Rt == 15)
1706         S = MCDisassembler::SoftFail;
1707       if (!type && Rm == 15)
1708         S = MCDisassembler::SoftFail;
1709       if (!type && writeback && (Rn == 15 || Rn == Rt))
1710         S = MCDisassembler::SoftFail;
1711       break;
1712     case ARM::LDRSH:
1713     case ARM::LDRSH_PRE:
1714     case ARM::LDRSH_POST:
1715     case ARM::LDRSB:
1716     case ARM::LDRSB_PRE:
1717     case ARM::LDRSB_POST:
1718       if (type && Rn == 15){
1719         if (Rt == 15)
1720           S = MCDisassembler::SoftFail;
1721         break;
1722       }
1723       if (type && (Rt == 15 || (writeback && Rn == Rt)))
1724         S = MCDisassembler::SoftFail;
1725       if (!type && (Rt == 15 || Rm == 15))
1726         S = MCDisassembler::SoftFail;
1727       if (!type && writeback && (Rn == 15 || Rn == Rt))
1728         S = MCDisassembler::SoftFail;
1729       break;
1730     default:
1731       break;
1732   }
1733 
1734   if (writeback) { // Writeback
1735     if (P)
1736       U |= ARMII::IndexModePre << 9;
1737     else
1738       U |= ARMII::IndexModePost << 9;
1739 
1740     // On stores, the writeback operand precedes Rt.
1741     switch (Inst.getOpcode()) {
1742     case ARM::STRD:
1743     case ARM::STRD_PRE:
1744     case ARM::STRD_POST:
1745     case ARM::STRH:
1746     case ARM::STRH_PRE:
1747     case ARM::STRH_POST:
1748       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1749         return MCDisassembler::Fail;
1750       break;
1751     default:
1752       break;
1753     }
1754   }
1755 
1756   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1757     return MCDisassembler::Fail;
1758   switch (Inst.getOpcode()) {
1759     case ARM::STRD:
1760     case ARM::STRD_PRE:
1761     case ARM::STRD_POST:
1762     case ARM::LDRD:
1763     case ARM::LDRD_PRE:
1764     case ARM::LDRD_POST:
1765       if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1766         return MCDisassembler::Fail;
1767       break;
1768     default:
1769       break;
1770   }
1771 
1772   if (writeback) {
1773     // On loads, the writeback operand comes after Rt.
1774     switch (Inst.getOpcode()) {
1775     case ARM::LDRD:
1776     case ARM::LDRD_PRE:
1777     case ARM::LDRD_POST:
1778     case ARM::LDRH:
1779     case ARM::LDRH_PRE:
1780     case ARM::LDRH_POST:
1781     case ARM::LDRSH:
1782     case ARM::LDRSH_PRE:
1783     case ARM::LDRSH_POST:
1784     case ARM::LDRSB:
1785     case ARM::LDRSB_PRE:
1786     case ARM::LDRSB_POST:
1787     case ARM::LDRHTr:
1788     case ARM::LDRSBTr:
1789       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1790         return MCDisassembler::Fail;
1791       break;
1792     default:
1793       break;
1794     }
1795   }
1796 
1797   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1798     return MCDisassembler::Fail;
1799 
1800   if (type) {
1801     Inst.addOperand(MCOperand::CreateReg(0));
1802     Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1803   } else {
1804     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1805     return MCDisassembler::Fail;
1806     Inst.addOperand(MCOperand::CreateImm(U));
1807   }
1808 
1809   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1810     return MCDisassembler::Fail;
1811 
1812   return S;
1813 }
1814 
DecodeRFEInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1815 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1816                                  uint64_t Address, const void *Decoder) {
1817   DecodeStatus S = MCDisassembler::Success;
1818 
1819   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1820   unsigned mode = fieldFromInstruction(Insn, 23, 2);
1821 
1822   switch (mode) {
1823     case 0:
1824       mode = ARM_AM::da;
1825       break;
1826     case 1:
1827       mode = ARM_AM::ia;
1828       break;
1829     case 2:
1830       mode = ARM_AM::db;
1831       break;
1832     case 3:
1833       mode = ARM_AM::ib;
1834       break;
1835   }
1836 
1837   Inst.addOperand(MCOperand::CreateImm(mode));
1838   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1839     return MCDisassembler::Fail;
1840 
1841   return S;
1842 }
1843 
DecodeQADDInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1844 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1845                                uint64_t Address, const void *Decoder) {
1846   DecodeStatus S = MCDisassembler::Success;
1847 
1848   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1849   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1850   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1851   unsigned pred = fieldFromInstruction(Insn, 28, 4);
1852 
1853   if (pred == 0xF)
1854     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1855 
1856   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1857     return MCDisassembler::Fail;
1858   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1859     return MCDisassembler::Fail;
1860   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1861     return MCDisassembler::Fail;
1862   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1863     return MCDisassembler::Fail;
1864   return S;
1865 }
1866 
DecodeMemMultipleWritebackInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1867 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1868                                   unsigned Insn,
1869                                   uint64_t Address, const void *Decoder) {
1870   DecodeStatus S = MCDisassembler::Success;
1871 
1872   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1873   unsigned pred = fieldFromInstruction(Insn, 28, 4);
1874   unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1875 
1876   if (pred == 0xF) {
1877     // Ambiguous with RFE and SRS
1878     switch (Inst.getOpcode()) {
1879       case ARM::LDMDA:
1880         Inst.setOpcode(ARM::RFEDA);
1881         break;
1882       case ARM::LDMDA_UPD:
1883         Inst.setOpcode(ARM::RFEDA_UPD);
1884         break;
1885       case ARM::LDMDB:
1886         Inst.setOpcode(ARM::RFEDB);
1887         break;
1888       case ARM::LDMDB_UPD:
1889         Inst.setOpcode(ARM::RFEDB_UPD);
1890         break;
1891       case ARM::LDMIA:
1892         Inst.setOpcode(ARM::RFEIA);
1893         break;
1894       case ARM::LDMIA_UPD:
1895         Inst.setOpcode(ARM::RFEIA_UPD);
1896         break;
1897       case ARM::LDMIB:
1898         Inst.setOpcode(ARM::RFEIB);
1899         break;
1900       case ARM::LDMIB_UPD:
1901         Inst.setOpcode(ARM::RFEIB_UPD);
1902         break;
1903       case ARM::STMDA:
1904         Inst.setOpcode(ARM::SRSDA);
1905         break;
1906       case ARM::STMDA_UPD:
1907         Inst.setOpcode(ARM::SRSDA_UPD);
1908         break;
1909       case ARM::STMDB:
1910         Inst.setOpcode(ARM::SRSDB);
1911         break;
1912       case ARM::STMDB_UPD:
1913         Inst.setOpcode(ARM::SRSDB_UPD);
1914         break;
1915       case ARM::STMIA:
1916         Inst.setOpcode(ARM::SRSIA);
1917         break;
1918       case ARM::STMIA_UPD:
1919         Inst.setOpcode(ARM::SRSIA_UPD);
1920         break;
1921       case ARM::STMIB:
1922         Inst.setOpcode(ARM::SRSIB);
1923         break;
1924       case ARM::STMIB_UPD:
1925         Inst.setOpcode(ARM::SRSIB_UPD);
1926         break;
1927       default:
1928         return MCDisassembler::Fail;
1929     }
1930 
1931     // For stores (which become SRS's, the only operand is the mode.
1932     if (fieldFromInstruction(Insn, 20, 1) == 0) {
1933       // Check SRS encoding constraints
1934       if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1935             fieldFromInstruction(Insn, 20, 1) == 0))
1936         return MCDisassembler::Fail;
1937 
1938       Inst.addOperand(
1939           MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
1940       return S;
1941     }
1942 
1943     return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1944   }
1945 
1946   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1947     return MCDisassembler::Fail;
1948   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1949     return MCDisassembler::Fail; // Tied
1950   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1951     return MCDisassembler::Fail;
1952   if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1953     return MCDisassembler::Fail;
1954 
1955   return S;
1956 }
1957 
DecodeCPSInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1958 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1959                                  uint64_t Address, const void *Decoder) {
1960   unsigned imod = fieldFromInstruction(Insn, 18, 2);
1961   unsigned M = fieldFromInstruction(Insn, 17, 1);
1962   unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1963   unsigned mode = fieldFromInstruction(Insn, 0, 5);
1964 
1965   DecodeStatus S = MCDisassembler::Success;
1966 
1967   // This decoder is called from multiple location that do not check
1968   // the full encoding is valid before they do.
1969   if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1970       fieldFromInstruction(Insn, 16, 1) != 0 ||
1971       fieldFromInstruction(Insn, 20, 8) != 0x10)
1972     return MCDisassembler::Fail;
1973 
1974   // imod == '01' --> UNPREDICTABLE
1975   // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1976   // return failure here.  The '01' imod value is unprintable, so there's
1977   // nothing useful we could do even if we returned UNPREDICTABLE.
1978 
1979   if (imod == 1) return MCDisassembler::Fail;
1980 
1981   if (imod && M) {
1982     Inst.setOpcode(ARM::CPS3p);
1983     Inst.addOperand(MCOperand::CreateImm(imod));
1984     Inst.addOperand(MCOperand::CreateImm(iflags));
1985     Inst.addOperand(MCOperand::CreateImm(mode));
1986   } else if (imod && !M) {
1987     Inst.setOpcode(ARM::CPS2p);
1988     Inst.addOperand(MCOperand::CreateImm(imod));
1989     Inst.addOperand(MCOperand::CreateImm(iflags));
1990     if (mode) S = MCDisassembler::SoftFail;
1991   } else if (!imod && M) {
1992     Inst.setOpcode(ARM::CPS1p);
1993     Inst.addOperand(MCOperand::CreateImm(mode));
1994     if (iflags) S = MCDisassembler::SoftFail;
1995   } else {
1996     // imod == '00' && M == '0' --> UNPREDICTABLE
1997     Inst.setOpcode(ARM::CPS1p);
1998     Inst.addOperand(MCOperand::CreateImm(mode));
1999     S = MCDisassembler::SoftFail;
2000   }
2001 
2002   return S;
2003 }
2004 
DecodeT2CPSInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2005 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
2006                                  uint64_t Address, const void *Decoder) {
2007   unsigned imod = fieldFromInstruction(Insn, 9, 2);
2008   unsigned M = fieldFromInstruction(Insn, 8, 1);
2009   unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2010   unsigned mode = fieldFromInstruction(Insn, 0, 5);
2011 
2012   DecodeStatus S = MCDisassembler::Success;
2013 
2014   // imod == '01' --> UNPREDICTABLE
2015   // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2016   // return failure here.  The '01' imod value is unprintable, so there's
2017   // nothing useful we could do even if we returned UNPREDICTABLE.
2018 
2019   if (imod == 1) return MCDisassembler::Fail;
2020 
2021   if (imod && M) {
2022     Inst.setOpcode(ARM::t2CPS3p);
2023     Inst.addOperand(MCOperand::CreateImm(imod));
2024     Inst.addOperand(MCOperand::CreateImm(iflags));
2025     Inst.addOperand(MCOperand::CreateImm(mode));
2026   } else if (imod && !M) {
2027     Inst.setOpcode(ARM::t2CPS2p);
2028     Inst.addOperand(MCOperand::CreateImm(imod));
2029     Inst.addOperand(MCOperand::CreateImm(iflags));
2030     if (mode) S = MCDisassembler::SoftFail;
2031   } else if (!imod && M) {
2032     Inst.setOpcode(ARM::t2CPS1p);
2033     Inst.addOperand(MCOperand::CreateImm(mode));
2034     if (iflags) S = MCDisassembler::SoftFail;
2035   } else {
2036     // imod == '00' && M == '0' --> this is a HINT instruction
2037     int imm = fieldFromInstruction(Insn, 0, 8);
2038     // HINT are defined only for immediate in [0..4]
2039     if(imm > 4) return MCDisassembler::Fail;
2040     Inst.setOpcode(ARM::t2HINT);
2041     Inst.addOperand(MCOperand::CreateImm(imm));
2042   }
2043 
2044   return S;
2045 }
2046 
DecodeT2MOVTWInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2047 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2048                                  uint64_t Address, const void *Decoder) {
2049   DecodeStatus S = MCDisassembler::Success;
2050 
2051   unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2052   unsigned imm = 0;
2053 
2054   imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2055   imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2056   imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2057   imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2058 
2059   if (Inst.getOpcode() == ARM::t2MOVTi16)
2060     if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2061       return MCDisassembler::Fail;
2062   if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2063     return MCDisassembler::Fail;
2064 
2065   if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2066     Inst.addOperand(MCOperand::CreateImm(imm));
2067 
2068   return S;
2069 }
2070 
DecodeArmMOVTWInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2071 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2072                                  uint64_t Address, const void *Decoder) {
2073   DecodeStatus S = MCDisassembler::Success;
2074 
2075   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2076   unsigned pred = fieldFromInstruction(Insn, 28, 4);
2077   unsigned imm = 0;
2078 
2079   imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2080   imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2081 
2082   if (Inst.getOpcode() == ARM::MOVTi16)
2083     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2084       return MCDisassembler::Fail;
2085 
2086   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2087     return MCDisassembler::Fail;
2088 
2089   if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2090     Inst.addOperand(MCOperand::CreateImm(imm));
2091 
2092   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2093     return MCDisassembler::Fail;
2094 
2095   return S;
2096 }
2097 
DecodeSMLAInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2098 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2099                                  uint64_t Address, const void *Decoder) {
2100   DecodeStatus S = MCDisassembler::Success;
2101 
2102   unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2103   unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2104   unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2105   unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2106   unsigned pred = fieldFromInstruction(Insn, 28, 4);
2107 
2108   if (pred == 0xF)
2109     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2110 
2111   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2112     return MCDisassembler::Fail;
2113   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2114     return MCDisassembler::Fail;
2115   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2116     return MCDisassembler::Fail;
2117   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2118     return MCDisassembler::Fail;
2119 
2120   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2121     return MCDisassembler::Fail;
2122 
2123   return S;
2124 }
2125 
DecodeTSTInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2126 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2127                                   uint64_t Address, const void *Decoder) {
2128   DecodeStatus S = MCDisassembler::Success;
2129 
2130   unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2131   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2132   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2133 
2134   if (Pred == 0xF)
2135     return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2136 
2137   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2138     return MCDisassembler::Fail;
2139   if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2140     return MCDisassembler::Fail;
2141   if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2142     return MCDisassembler::Fail;
2143 
2144   return S;
2145 }
2146 
DecodeSETPANInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2147 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2148                                   uint64_t Address, const void *Decoder) {
2149   DecodeStatus S = MCDisassembler::Success;
2150 
2151   unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2152 
2153   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2154   uint64_t FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2155   if ((FeatureBits & ARM::HasV8_1aOps) == 0 ||
2156       (FeatureBits & ARM::HasV8Ops) == 0 )
2157     return MCDisassembler::Fail;
2158 
2159   // Decoder can be called from DecodeTST, which does not check the full
2160   // encoding is valid.
2161   if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2162       fieldFromInstruction(Insn, 4,4) != 0)
2163     return MCDisassembler::Fail;
2164   if (fieldFromInstruction(Insn, 10,10) != 0 ||
2165       fieldFromInstruction(Insn, 0,4) != 0)
2166     S = MCDisassembler::SoftFail;
2167 
2168   Inst.setOpcode(ARM::SETPAN);
2169   Inst.addOperand(MCOperand::CreateImm(Imm));
2170 
2171   return S;
2172 }
2173 
DecodeAddrModeImm12Operand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)2174 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2175                            uint64_t Address, const void *Decoder) {
2176   DecodeStatus S = MCDisassembler::Success;
2177 
2178   unsigned add = fieldFromInstruction(Val, 12, 1);
2179   unsigned imm = fieldFromInstruction(Val, 0, 12);
2180   unsigned Rn = fieldFromInstruction(Val, 13, 4);
2181 
2182   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2183     return MCDisassembler::Fail;
2184 
2185   if (!add) imm *= -1;
2186   if (imm == 0 && !add) imm = INT32_MIN;
2187   Inst.addOperand(MCOperand::CreateImm(imm));
2188   if (Rn == 15)
2189     tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2190 
2191   return S;
2192 }
2193 
DecodeAddrMode5Operand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)2194 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2195                                    uint64_t Address, const void *Decoder) {
2196   DecodeStatus S = MCDisassembler::Success;
2197 
2198   unsigned Rn = fieldFromInstruction(Val, 9, 4);
2199   unsigned U = fieldFromInstruction(Val, 8, 1);
2200   unsigned imm = fieldFromInstruction(Val, 0, 8);
2201 
2202   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2203     return MCDisassembler::Fail;
2204 
2205   if (U)
2206     Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2207   else
2208     Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2209 
2210   return S;
2211 }
2212 
DecodeAddrMode7Operand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)2213 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2214                                    uint64_t Address, const void *Decoder) {
2215   return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2216 }
2217 
2218 static DecodeStatus
DecodeT2BInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2219 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2220                      uint64_t Address, const void *Decoder) {
2221   DecodeStatus Status = MCDisassembler::Success;
2222 
2223   // Note the J1 and J2 values are from the encoded instruction.  So here
2224   // change them to I1 and I2 values via as documented:
2225   // I1 = NOT(J1 EOR S);
2226   // I2 = NOT(J2 EOR S);
2227   // and build the imm32 with one trailing zero as documented:
2228   // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2229   unsigned S = fieldFromInstruction(Insn, 26, 1);
2230   unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2231   unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2232   unsigned I1 = !(J1 ^ S);
2233   unsigned I2 = !(J2 ^ S);
2234   unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2235   unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2236   unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2237   int imm32 = SignExtend32<25>(tmp << 1);
2238   if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2239                                 true, 4, Inst, Decoder))
2240     Inst.addOperand(MCOperand::CreateImm(imm32));
2241 
2242   return Status;
2243 }
2244 
2245 static DecodeStatus
DecodeBranchImmInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2246 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2247                            uint64_t Address, const void *Decoder) {
2248   DecodeStatus S = MCDisassembler::Success;
2249 
2250   unsigned pred = fieldFromInstruction(Insn, 28, 4);
2251   unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2252 
2253   if (pred == 0xF) {
2254     Inst.setOpcode(ARM::BLXi);
2255     imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2256     if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2257                                   true, 4, Inst, Decoder))
2258     Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2259     return S;
2260   }
2261 
2262   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2263                                 true, 4, Inst, Decoder))
2264     Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2265   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2266     return MCDisassembler::Fail;
2267 
2268   return S;
2269 }
2270 
2271 
DecodeAddrMode6Operand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)2272 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2273                                    uint64_t Address, const void *Decoder) {
2274   DecodeStatus S = MCDisassembler::Success;
2275 
2276   unsigned Rm = fieldFromInstruction(Val, 0, 4);
2277   unsigned align = fieldFromInstruction(Val, 4, 2);
2278 
2279   if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2280     return MCDisassembler::Fail;
2281   if (!align)
2282     Inst.addOperand(MCOperand::CreateImm(0));
2283   else
2284     Inst.addOperand(MCOperand::CreateImm(4 << align));
2285 
2286   return S;
2287 }
2288 
DecodeVLDInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2289 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2290                                    uint64_t Address, const void *Decoder) {
2291   DecodeStatus S = MCDisassembler::Success;
2292 
2293   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2294   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2295   unsigned wb = fieldFromInstruction(Insn, 16, 4);
2296   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2297   Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2298   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2299 
2300   // First output register
2301   switch (Inst.getOpcode()) {
2302   case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2303   case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2304   case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2305   case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2306   case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2307   case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2308   case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2309   case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2310   case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2311     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2312       return MCDisassembler::Fail;
2313     break;
2314   case ARM::VLD2b16:
2315   case ARM::VLD2b32:
2316   case ARM::VLD2b8:
2317   case ARM::VLD2b16wb_fixed:
2318   case ARM::VLD2b16wb_register:
2319   case ARM::VLD2b32wb_fixed:
2320   case ARM::VLD2b32wb_register:
2321   case ARM::VLD2b8wb_fixed:
2322   case ARM::VLD2b8wb_register:
2323     if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2324       return MCDisassembler::Fail;
2325     break;
2326   default:
2327     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2328       return MCDisassembler::Fail;
2329   }
2330 
2331   // Second output register
2332   switch (Inst.getOpcode()) {
2333     case ARM::VLD3d8:
2334     case ARM::VLD3d16:
2335     case ARM::VLD3d32:
2336     case ARM::VLD3d8_UPD:
2337     case ARM::VLD3d16_UPD:
2338     case ARM::VLD3d32_UPD:
2339     case ARM::VLD4d8:
2340     case ARM::VLD4d16:
2341     case ARM::VLD4d32:
2342     case ARM::VLD4d8_UPD:
2343     case ARM::VLD4d16_UPD:
2344     case ARM::VLD4d32_UPD:
2345       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2346         return MCDisassembler::Fail;
2347       break;
2348     case ARM::VLD3q8:
2349     case ARM::VLD3q16:
2350     case ARM::VLD3q32:
2351     case ARM::VLD3q8_UPD:
2352     case ARM::VLD3q16_UPD:
2353     case ARM::VLD3q32_UPD:
2354     case ARM::VLD4q8:
2355     case ARM::VLD4q16:
2356     case ARM::VLD4q32:
2357     case ARM::VLD4q8_UPD:
2358     case ARM::VLD4q16_UPD:
2359     case ARM::VLD4q32_UPD:
2360       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2361         return MCDisassembler::Fail;
2362     default:
2363       break;
2364   }
2365 
2366   // Third output register
2367   switch(Inst.getOpcode()) {
2368     case ARM::VLD3d8:
2369     case ARM::VLD3d16:
2370     case ARM::VLD3d32:
2371     case ARM::VLD3d8_UPD:
2372     case ARM::VLD3d16_UPD:
2373     case ARM::VLD3d32_UPD:
2374     case ARM::VLD4d8:
2375     case ARM::VLD4d16:
2376     case ARM::VLD4d32:
2377     case ARM::VLD4d8_UPD:
2378     case ARM::VLD4d16_UPD:
2379     case ARM::VLD4d32_UPD:
2380       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2381         return MCDisassembler::Fail;
2382       break;
2383     case ARM::VLD3q8:
2384     case ARM::VLD3q16:
2385     case ARM::VLD3q32:
2386     case ARM::VLD3q8_UPD:
2387     case ARM::VLD3q16_UPD:
2388     case ARM::VLD3q32_UPD:
2389     case ARM::VLD4q8:
2390     case ARM::VLD4q16:
2391     case ARM::VLD4q32:
2392     case ARM::VLD4q8_UPD:
2393     case ARM::VLD4q16_UPD:
2394     case ARM::VLD4q32_UPD:
2395       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2396         return MCDisassembler::Fail;
2397       break;
2398     default:
2399       break;
2400   }
2401 
2402   // Fourth output register
2403   switch (Inst.getOpcode()) {
2404     case ARM::VLD4d8:
2405     case ARM::VLD4d16:
2406     case ARM::VLD4d32:
2407     case ARM::VLD4d8_UPD:
2408     case ARM::VLD4d16_UPD:
2409     case ARM::VLD4d32_UPD:
2410       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2411         return MCDisassembler::Fail;
2412       break;
2413     case ARM::VLD4q8:
2414     case ARM::VLD4q16:
2415     case ARM::VLD4q32:
2416     case ARM::VLD4q8_UPD:
2417     case ARM::VLD4q16_UPD:
2418     case ARM::VLD4q32_UPD:
2419       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2420         return MCDisassembler::Fail;
2421       break;
2422     default:
2423       break;
2424   }
2425 
2426   // Writeback operand
2427   switch (Inst.getOpcode()) {
2428     case ARM::VLD1d8wb_fixed:
2429     case ARM::VLD1d16wb_fixed:
2430     case ARM::VLD1d32wb_fixed:
2431     case ARM::VLD1d64wb_fixed:
2432     case ARM::VLD1d8wb_register:
2433     case ARM::VLD1d16wb_register:
2434     case ARM::VLD1d32wb_register:
2435     case ARM::VLD1d64wb_register:
2436     case ARM::VLD1q8wb_fixed:
2437     case ARM::VLD1q16wb_fixed:
2438     case ARM::VLD1q32wb_fixed:
2439     case ARM::VLD1q64wb_fixed:
2440     case ARM::VLD1q8wb_register:
2441     case ARM::VLD1q16wb_register:
2442     case ARM::VLD1q32wb_register:
2443     case ARM::VLD1q64wb_register:
2444     case ARM::VLD1d8Twb_fixed:
2445     case ARM::VLD1d8Twb_register:
2446     case ARM::VLD1d16Twb_fixed:
2447     case ARM::VLD1d16Twb_register:
2448     case ARM::VLD1d32Twb_fixed:
2449     case ARM::VLD1d32Twb_register:
2450     case ARM::VLD1d64Twb_fixed:
2451     case ARM::VLD1d64Twb_register:
2452     case ARM::VLD1d8Qwb_fixed:
2453     case ARM::VLD1d8Qwb_register:
2454     case ARM::VLD1d16Qwb_fixed:
2455     case ARM::VLD1d16Qwb_register:
2456     case ARM::VLD1d32Qwb_fixed:
2457     case ARM::VLD1d32Qwb_register:
2458     case ARM::VLD1d64Qwb_fixed:
2459     case ARM::VLD1d64Qwb_register:
2460     case ARM::VLD2d8wb_fixed:
2461     case ARM::VLD2d16wb_fixed:
2462     case ARM::VLD2d32wb_fixed:
2463     case ARM::VLD2q8wb_fixed:
2464     case ARM::VLD2q16wb_fixed:
2465     case ARM::VLD2q32wb_fixed:
2466     case ARM::VLD2d8wb_register:
2467     case ARM::VLD2d16wb_register:
2468     case ARM::VLD2d32wb_register:
2469     case ARM::VLD2q8wb_register:
2470     case ARM::VLD2q16wb_register:
2471     case ARM::VLD2q32wb_register:
2472     case ARM::VLD2b8wb_fixed:
2473     case ARM::VLD2b16wb_fixed:
2474     case ARM::VLD2b32wb_fixed:
2475     case ARM::VLD2b8wb_register:
2476     case ARM::VLD2b16wb_register:
2477     case ARM::VLD2b32wb_register:
2478       Inst.addOperand(MCOperand::CreateImm(0));
2479       break;
2480     case ARM::VLD3d8_UPD:
2481     case ARM::VLD3d16_UPD:
2482     case ARM::VLD3d32_UPD:
2483     case ARM::VLD3q8_UPD:
2484     case ARM::VLD3q16_UPD:
2485     case ARM::VLD3q32_UPD:
2486     case ARM::VLD4d8_UPD:
2487     case ARM::VLD4d16_UPD:
2488     case ARM::VLD4d32_UPD:
2489     case ARM::VLD4q8_UPD:
2490     case ARM::VLD4q16_UPD:
2491     case ARM::VLD4q32_UPD:
2492       if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2493         return MCDisassembler::Fail;
2494       break;
2495     default:
2496       break;
2497   }
2498 
2499   // AddrMode6 Base (register+alignment)
2500   if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2501     return MCDisassembler::Fail;
2502 
2503   // AddrMode6 Offset (register)
2504   switch (Inst.getOpcode()) {
2505   default:
2506     // The below have been updated to have explicit am6offset split
2507     // between fixed and register offset. For those instructions not
2508     // yet updated, we need to add an additional reg0 operand for the
2509     // fixed variant.
2510     //
2511     // The fixed offset encodes as Rm == 0xd, so we check for that.
2512     if (Rm == 0xd) {
2513       Inst.addOperand(MCOperand::CreateReg(0));
2514       break;
2515     }
2516     // Fall through to handle the register offset variant.
2517   case ARM::VLD1d8wb_fixed:
2518   case ARM::VLD1d16wb_fixed:
2519   case ARM::VLD1d32wb_fixed:
2520   case ARM::VLD1d64wb_fixed:
2521   case ARM::VLD1d8Twb_fixed:
2522   case ARM::VLD1d16Twb_fixed:
2523   case ARM::VLD1d32Twb_fixed:
2524   case ARM::VLD1d64Twb_fixed:
2525   case ARM::VLD1d8Qwb_fixed:
2526   case ARM::VLD1d16Qwb_fixed:
2527   case ARM::VLD1d32Qwb_fixed:
2528   case ARM::VLD1d64Qwb_fixed:
2529   case ARM::VLD1d8wb_register:
2530   case ARM::VLD1d16wb_register:
2531   case ARM::VLD1d32wb_register:
2532   case ARM::VLD1d64wb_register:
2533   case ARM::VLD1q8wb_fixed:
2534   case ARM::VLD1q16wb_fixed:
2535   case ARM::VLD1q32wb_fixed:
2536   case ARM::VLD1q64wb_fixed:
2537   case ARM::VLD1q8wb_register:
2538   case ARM::VLD1q16wb_register:
2539   case ARM::VLD1q32wb_register:
2540   case ARM::VLD1q64wb_register:
2541     // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2542     // variant encodes Rm == 0xf. Anything else is a register offset post-
2543     // increment and we need to add the register operand to the instruction.
2544     if (Rm != 0xD && Rm != 0xF &&
2545         !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2546       return MCDisassembler::Fail;
2547     break;
2548   case ARM::VLD2d8wb_fixed:
2549   case ARM::VLD2d16wb_fixed:
2550   case ARM::VLD2d32wb_fixed:
2551   case ARM::VLD2b8wb_fixed:
2552   case ARM::VLD2b16wb_fixed:
2553   case ARM::VLD2b32wb_fixed:
2554   case ARM::VLD2q8wb_fixed:
2555   case ARM::VLD2q16wb_fixed:
2556   case ARM::VLD2q32wb_fixed:
2557     break;
2558   }
2559 
2560   return S;
2561 }
2562 
DecodeVLDST1Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2563 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2564                                    uint64_t Address, const void *Decoder) {
2565   unsigned type = fieldFromInstruction(Insn, 8, 4);
2566   unsigned align = fieldFromInstruction(Insn, 4, 2);
2567   if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2568   if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2569   if (type == 10 && align == 3) return MCDisassembler::Fail;
2570 
2571   unsigned load = fieldFromInstruction(Insn, 21, 1);
2572   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2573               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2574 }
2575 
DecodeVLDST2Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2576 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2577                                    uint64_t Address, const void *Decoder) {
2578   unsigned size = fieldFromInstruction(Insn, 6, 2);
2579   if (size == 3) return MCDisassembler::Fail;
2580 
2581   unsigned type = fieldFromInstruction(Insn, 8, 4);
2582   unsigned align = fieldFromInstruction(Insn, 4, 2);
2583   if (type == 8 && align == 3) return MCDisassembler::Fail;
2584   if (type == 9 && align == 3) return MCDisassembler::Fail;
2585 
2586   unsigned load = fieldFromInstruction(Insn, 21, 1);
2587   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2588               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2589 }
2590 
DecodeVLDST3Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2591 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2592                                    uint64_t Address, const void *Decoder) {
2593   unsigned size = fieldFromInstruction(Insn, 6, 2);
2594   if (size == 3) return MCDisassembler::Fail;
2595 
2596   unsigned align = fieldFromInstruction(Insn, 4, 2);
2597   if (align & 2) return MCDisassembler::Fail;
2598 
2599   unsigned load = fieldFromInstruction(Insn, 21, 1);
2600   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2601               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2602 }
2603 
DecodeVLDST4Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2604 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2605                                    uint64_t Address, const void *Decoder) {
2606   unsigned size = fieldFromInstruction(Insn, 6, 2);
2607   if (size == 3) return MCDisassembler::Fail;
2608 
2609   unsigned load = fieldFromInstruction(Insn, 21, 1);
2610   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2611               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2612 }
2613 
DecodeVSTInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2614 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2615                                  uint64_t Address, const void *Decoder) {
2616   DecodeStatus S = MCDisassembler::Success;
2617 
2618   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2619   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2620   unsigned wb = fieldFromInstruction(Insn, 16, 4);
2621   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2622   Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2623   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2624 
2625   // Writeback Operand
2626   switch (Inst.getOpcode()) {
2627     case ARM::VST1d8wb_fixed:
2628     case ARM::VST1d16wb_fixed:
2629     case ARM::VST1d32wb_fixed:
2630     case ARM::VST1d64wb_fixed:
2631     case ARM::VST1d8wb_register:
2632     case ARM::VST1d16wb_register:
2633     case ARM::VST1d32wb_register:
2634     case ARM::VST1d64wb_register:
2635     case ARM::VST1q8wb_fixed:
2636     case ARM::VST1q16wb_fixed:
2637     case ARM::VST1q32wb_fixed:
2638     case ARM::VST1q64wb_fixed:
2639     case ARM::VST1q8wb_register:
2640     case ARM::VST1q16wb_register:
2641     case ARM::VST1q32wb_register:
2642     case ARM::VST1q64wb_register:
2643     case ARM::VST1d8Twb_fixed:
2644     case ARM::VST1d16Twb_fixed:
2645     case ARM::VST1d32Twb_fixed:
2646     case ARM::VST1d64Twb_fixed:
2647     case ARM::VST1d8Twb_register:
2648     case ARM::VST1d16Twb_register:
2649     case ARM::VST1d32Twb_register:
2650     case ARM::VST1d64Twb_register:
2651     case ARM::VST1d8Qwb_fixed:
2652     case ARM::VST1d16Qwb_fixed:
2653     case ARM::VST1d32Qwb_fixed:
2654     case ARM::VST1d64Qwb_fixed:
2655     case ARM::VST1d8Qwb_register:
2656     case ARM::VST1d16Qwb_register:
2657     case ARM::VST1d32Qwb_register:
2658     case ARM::VST1d64Qwb_register:
2659     case ARM::VST2d8wb_fixed:
2660     case ARM::VST2d16wb_fixed:
2661     case ARM::VST2d32wb_fixed:
2662     case ARM::VST2d8wb_register:
2663     case ARM::VST2d16wb_register:
2664     case ARM::VST2d32wb_register:
2665     case ARM::VST2q8wb_fixed:
2666     case ARM::VST2q16wb_fixed:
2667     case ARM::VST2q32wb_fixed:
2668     case ARM::VST2q8wb_register:
2669     case ARM::VST2q16wb_register:
2670     case ARM::VST2q32wb_register:
2671     case ARM::VST2b8wb_fixed:
2672     case ARM::VST2b16wb_fixed:
2673     case ARM::VST2b32wb_fixed:
2674     case ARM::VST2b8wb_register:
2675     case ARM::VST2b16wb_register:
2676     case ARM::VST2b32wb_register:
2677       if (Rm == 0xF)
2678         return MCDisassembler::Fail;
2679       Inst.addOperand(MCOperand::CreateImm(0));
2680       break;
2681     case ARM::VST3d8_UPD:
2682     case ARM::VST3d16_UPD:
2683     case ARM::VST3d32_UPD:
2684     case ARM::VST3q8_UPD:
2685     case ARM::VST3q16_UPD:
2686     case ARM::VST3q32_UPD:
2687     case ARM::VST4d8_UPD:
2688     case ARM::VST4d16_UPD:
2689     case ARM::VST4d32_UPD:
2690     case ARM::VST4q8_UPD:
2691     case ARM::VST4q16_UPD:
2692     case ARM::VST4q32_UPD:
2693       if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2694         return MCDisassembler::Fail;
2695       break;
2696     default:
2697       break;
2698   }
2699 
2700   // AddrMode6 Base (register+alignment)
2701   if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2702     return MCDisassembler::Fail;
2703 
2704   // AddrMode6 Offset (register)
2705   switch (Inst.getOpcode()) {
2706     default:
2707       if (Rm == 0xD)
2708         Inst.addOperand(MCOperand::CreateReg(0));
2709       else if (Rm != 0xF) {
2710         if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2711           return MCDisassembler::Fail;
2712       }
2713       break;
2714     case ARM::VST1d8wb_fixed:
2715     case ARM::VST1d16wb_fixed:
2716     case ARM::VST1d32wb_fixed:
2717     case ARM::VST1d64wb_fixed:
2718     case ARM::VST1q8wb_fixed:
2719     case ARM::VST1q16wb_fixed:
2720     case ARM::VST1q32wb_fixed:
2721     case ARM::VST1q64wb_fixed:
2722     case ARM::VST1d8Twb_fixed:
2723     case ARM::VST1d16Twb_fixed:
2724     case ARM::VST1d32Twb_fixed:
2725     case ARM::VST1d64Twb_fixed:
2726     case ARM::VST1d8Qwb_fixed:
2727     case ARM::VST1d16Qwb_fixed:
2728     case ARM::VST1d32Qwb_fixed:
2729     case ARM::VST1d64Qwb_fixed:
2730     case ARM::VST2d8wb_fixed:
2731     case ARM::VST2d16wb_fixed:
2732     case ARM::VST2d32wb_fixed:
2733     case ARM::VST2q8wb_fixed:
2734     case ARM::VST2q16wb_fixed:
2735     case ARM::VST2q32wb_fixed:
2736     case ARM::VST2b8wb_fixed:
2737     case ARM::VST2b16wb_fixed:
2738     case ARM::VST2b32wb_fixed:
2739       break;
2740   }
2741 
2742 
2743   // First input register
2744   switch (Inst.getOpcode()) {
2745   case ARM::VST1q16:
2746   case ARM::VST1q32:
2747   case ARM::VST1q64:
2748   case ARM::VST1q8:
2749   case ARM::VST1q16wb_fixed:
2750   case ARM::VST1q16wb_register:
2751   case ARM::VST1q32wb_fixed:
2752   case ARM::VST1q32wb_register:
2753   case ARM::VST1q64wb_fixed:
2754   case ARM::VST1q64wb_register:
2755   case ARM::VST1q8wb_fixed:
2756   case ARM::VST1q8wb_register:
2757   case ARM::VST2d16:
2758   case ARM::VST2d32:
2759   case ARM::VST2d8:
2760   case ARM::VST2d16wb_fixed:
2761   case ARM::VST2d16wb_register:
2762   case ARM::VST2d32wb_fixed:
2763   case ARM::VST2d32wb_register:
2764   case ARM::VST2d8wb_fixed:
2765   case ARM::VST2d8wb_register:
2766     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2767       return MCDisassembler::Fail;
2768     break;
2769   case ARM::VST2b16:
2770   case ARM::VST2b32:
2771   case ARM::VST2b8:
2772   case ARM::VST2b16wb_fixed:
2773   case ARM::VST2b16wb_register:
2774   case ARM::VST2b32wb_fixed:
2775   case ARM::VST2b32wb_register:
2776   case ARM::VST2b8wb_fixed:
2777   case ARM::VST2b8wb_register:
2778     if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2779       return MCDisassembler::Fail;
2780     break;
2781   default:
2782     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2783       return MCDisassembler::Fail;
2784   }
2785 
2786   // Second input register
2787   switch (Inst.getOpcode()) {
2788     case ARM::VST3d8:
2789     case ARM::VST3d16:
2790     case ARM::VST3d32:
2791     case ARM::VST3d8_UPD:
2792     case ARM::VST3d16_UPD:
2793     case ARM::VST3d32_UPD:
2794     case ARM::VST4d8:
2795     case ARM::VST4d16:
2796     case ARM::VST4d32:
2797     case ARM::VST4d8_UPD:
2798     case ARM::VST4d16_UPD:
2799     case ARM::VST4d32_UPD:
2800       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2801         return MCDisassembler::Fail;
2802       break;
2803     case ARM::VST3q8:
2804     case ARM::VST3q16:
2805     case ARM::VST3q32:
2806     case ARM::VST3q8_UPD:
2807     case ARM::VST3q16_UPD:
2808     case ARM::VST3q32_UPD:
2809     case ARM::VST4q8:
2810     case ARM::VST4q16:
2811     case ARM::VST4q32:
2812     case ARM::VST4q8_UPD:
2813     case ARM::VST4q16_UPD:
2814     case ARM::VST4q32_UPD:
2815       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2816         return MCDisassembler::Fail;
2817       break;
2818     default:
2819       break;
2820   }
2821 
2822   // Third input register
2823   switch (Inst.getOpcode()) {
2824     case ARM::VST3d8:
2825     case ARM::VST3d16:
2826     case ARM::VST3d32:
2827     case ARM::VST3d8_UPD:
2828     case ARM::VST3d16_UPD:
2829     case ARM::VST3d32_UPD:
2830     case ARM::VST4d8:
2831     case ARM::VST4d16:
2832     case ARM::VST4d32:
2833     case ARM::VST4d8_UPD:
2834     case ARM::VST4d16_UPD:
2835     case ARM::VST4d32_UPD:
2836       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2837         return MCDisassembler::Fail;
2838       break;
2839     case ARM::VST3q8:
2840     case ARM::VST3q16:
2841     case ARM::VST3q32:
2842     case ARM::VST3q8_UPD:
2843     case ARM::VST3q16_UPD:
2844     case ARM::VST3q32_UPD:
2845     case ARM::VST4q8:
2846     case ARM::VST4q16:
2847     case ARM::VST4q32:
2848     case ARM::VST4q8_UPD:
2849     case ARM::VST4q16_UPD:
2850     case ARM::VST4q32_UPD:
2851       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2852         return MCDisassembler::Fail;
2853       break;
2854     default:
2855       break;
2856   }
2857 
2858   // Fourth input register
2859   switch (Inst.getOpcode()) {
2860     case ARM::VST4d8:
2861     case ARM::VST4d16:
2862     case ARM::VST4d32:
2863     case ARM::VST4d8_UPD:
2864     case ARM::VST4d16_UPD:
2865     case ARM::VST4d32_UPD:
2866       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2867         return MCDisassembler::Fail;
2868       break;
2869     case ARM::VST4q8:
2870     case ARM::VST4q16:
2871     case ARM::VST4q32:
2872     case ARM::VST4q8_UPD:
2873     case ARM::VST4q16_UPD:
2874     case ARM::VST4q32_UPD:
2875       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2876         return MCDisassembler::Fail;
2877       break;
2878     default:
2879       break;
2880   }
2881 
2882   return S;
2883 }
2884 
DecodeVLD1DupInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2885 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2886                                     uint64_t Address, const void *Decoder) {
2887   DecodeStatus S = MCDisassembler::Success;
2888 
2889   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2890   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2891   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2892   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2893   unsigned align = fieldFromInstruction(Insn, 4, 1);
2894   unsigned size = fieldFromInstruction(Insn, 6, 2);
2895 
2896   if (size == 0 && align == 1)
2897     return MCDisassembler::Fail;
2898   align *= (1 << size);
2899 
2900   switch (Inst.getOpcode()) {
2901   case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2902   case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2903   case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2904   case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2905     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2906       return MCDisassembler::Fail;
2907     break;
2908   default:
2909     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2910       return MCDisassembler::Fail;
2911     break;
2912   }
2913   if (Rm != 0xF) {
2914     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2915       return MCDisassembler::Fail;
2916   }
2917 
2918   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2919     return MCDisassembler::Fail;
2920   Inst.addOperand(MCOperand::CreateImm(align));
2921 
2922   // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2923   // variant encodes Rm == 0xf. Anything else is a register offset post-
2924   // increment and we need to add the register operand to the instruction.
2925   if (Rm != 0xD && Rm != 0xF &&
2926       !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2927     return MCDisassembler::Fail;
2928 
2929   return S;
2930 }
2931 
DecodeVLD2DupInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2932 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2933                                     uint64_t Address, const void *Decoder) {
2934   DecodeStatus S = MCDisassembler::Success;
2935 
2936   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2937   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2938   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2939   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2940   unsigned align = fieldFromInstruction(Insn, 4, 1);
2941   unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2942   align *= 2*size;
2943 
2944   switch (Inst.getOpcode()) {
2945   case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2946   case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2947   case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2948   case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2949     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2950       return MCDisassembler::Fail;
2951     break;
2952   case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2953   case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2954   case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2955   case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2956     if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2957       return MCDisassembler::Fail;
2958     break;
2959   default:
2960     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2961       return MCDisassembler::Fail;
2962     break;
2963   }
2964 
2965   if (Rm != 0xF)
2966     Inst.addOperand(MCOperand::CreateImm(0));
2967 
2968   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2969     return MCDisassembler::Fail;
2970   Inst.addOperand(MCOperand::CreateImm(align));
2971 
2972   if (Rm != 0xD && Rm != 0xF) {
2973     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2974       return MCDisassembler::Fail;
2975   }
2976 
2977   return S;
2978 }
2979 
DecodeVLD3DupInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2980 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2981                                     uint64_t Address, const void *Decoder) {
2982   DecodeStatus S = MCDisassembler::Success;
2983 
2984   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2985   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2986   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2987   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2988   unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2989 
2990   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2991     return MCDisassembler::Fail;
2992   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2993     return MCDisassembler::Fail;
2994   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2995     return MCDisassembler::Fail;
2996   if (Rm != 0xF) {
2997     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2998       return MCDisassembler::Fail;
2999   }
3000 
3001   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3002     return MCDisassembler::Fail;
3003   Inst.addOperand(MCOperand::CreateImm(0));
3004 
3005   if (Rm == 0xD)
3006     Inst.addOperand(MCOperand::CreateReg(0));
3007   else if (Rm != 0xF) {
3008     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3009       return MCDisassembler::Fail;
3010   }
3011 
3012   return S;
3013 }
3014 
DecodeVLD4DupInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3015 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
3016                                     uint64_t Address, const void *Decoder) {
3017   DecodeStatus S = MCDisassembler::Success;
3018 
3019   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3020   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3021   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3022   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3023   unsigned size = fieldFromInstruction(Insn, 6, 2);
3024   unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3025   unsigned align = fieldFromInstruction(Insn, 4, 1);
3026 
3027   if (size == 0x3) {
3028     if (align == 0)
3029       return MCDisassembler::Fail;
3030     align = 16;
3031   } else {
3032     if (size == 2) {
3033       align *= 8;
3034     } else {
3035       size = 1 << size;
3036       align *= 4*size;
3037     }
3038   }
3039 
3040   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3041     return MCDisassembler::Fail;
3042   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3043     return MCDisassembler::Fail;
3044   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3045     return MCDisassembler::Fail;
3046   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3047     return MCDisassembler::Fail;
3048   if (Rm != 0xF) {
3049     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3050       return MCDisassembler::Fail;
3051   }
3052 
3053   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3054     return MCDisassembler::Fail;
3055   Inst.addOperand(MCOperand::CreateImm(align));
3056 
3057   if (Rm == 0xD)
3058     Inst.addOperand(MCOperand::CreateReg(0));
3059   else if (Rm != 0xF) {
3060     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3061       return MCDisassembler::Fail;
3062   }
3063 
3064   return S;
3065 }
3066 
3067 static DecodeStatus
DecodeNEONModImmInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3068 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
3069                             uint64_t Address, const void *Decoder) {
3070   DecodeStatus S = MCDisassembler::Success;
3071 
3072   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3073   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3074   unsigned imm = fieldFromInstruction(Insn, 0, 4);
3075   imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3076   imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3077   imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3078   imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3079   unsigned Q = fieldFromInstruction(Insn, 6, 1);
3080 
3081   if (Q) {
3082     if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3083     return MCDisassembler::Fail;
3084   } else {
3085     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3086     return MCDisassembler::Fail;
3087   }
3088 
3089   Inst.addOperand(MCOperand::CreateImm(imm));
3090 
3091   switch (Inst.getOpcode()) {
3092     case ARM::VORRiv4i16:
3093     case ARM::VORRiv2i32:
3094     case ARM::VBICiv4i16:
3095     case ARM::VBICiv2i32:
3096       if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3097         return MCDisassembler::Fail;
3098       break;
3099     case ARM::VORRiv8i16:
3100     case ARM::VORRiv4i32:
3101     case ARM::VBICiv8i16:
3102     case ARM::VBICiv4i32:
3103       if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3104         return MCDisassembler::Fail;
3105       break;
3106     default:
3107       break;
3108   }
3109 
3110   return S;
3111 }
3112 
DecodeVSHLMaxInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3113 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3114                                         uint64_t Address, const void *Decoder) {
3115   DecodeStatus S = MCDisassembler::Success;
3116 
3117   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3118   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3119   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3120   Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3121   unsigned size = fieldFromInstruction(Insn, 18, 2);
3122 
3123   if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3124     return MCDisassembler::Fail;
3125   if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3126     return MCDisassembler::Fail;
3127   Inst.addOperand(MCOperand::CreateImm(8 << size));
3128 
3129   return S;
3130 }
3131 
DecodeShiftRight8Imm(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3132 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3133                                uint64_t Address, const void *Decoder) {
3134   Inst.addOperand(MCOperand::CreateImm(8 - Val));
3135   return MCDisassembler::Success;
3136 }
3137 
DecodeShiftRight16Imm(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3138 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3139                                uint64_t Address, const void *Decoder) {
3140   Inst.addOperand(MCOperand::CreateImm(16 - Val));
3141   return MCDisassembler::Success;
3142 }
3143 
DecodeShiftRight32Imm(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3144 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3145                                uint64_t Address, const void *Decoder) {
3146   Inst.addOperand(MCOperand::CreateImm(32 - Val));
3147   return MCDisassembler::Success;
3148 }
3149 
DecodeShiftRight64Imm(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3150 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3151                                uint64_t Address, const void *Decoder) {
3152   Inst.addOperand(MCOperand::CreateImm(64 - Val));
3153   return MCDisassembler::Success;
3154 }
3155 
DecodeTBLInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3156 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3157                                uint64_t Address, const void *Decoder) {
3158   DecodeStatus S = MCDisassembler::Success;
3159 
3160   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3161   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3162   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3163   Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3164   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3165   Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3166   unsigned op = fieldFromInstruction(Insn, 6, 1);
3167 
3168   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3169     return MCDisassembler::Fail;
3170   if (op) {
3171     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3172     return MCDisassembler::Fail; // Writeback
3173   }
3174 
3175   switch (Inst.getOpcode()) {
3176   case ARM::VTBL2:
3177   case ARM::VTBX2:
3178     if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3179       return MCDisassembler::Fail;
3180     break;
3181   default:
3182     if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3183       return MCDisassembler::Fail;
3184   }
3185 
3186   if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3187     return MCDisassembler::Fail;
3188 
3189   return S;
3190 }
3191 
DecodeThumbAddSpecialReg(MCInst & Inst,uint16_t Insn,uint64_t Address,const void * Decoder)3192 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3193                                      uint64_t Address, const void *Decoder) {
3194   DecodeStatus S = MCDisassembler::Success;
3195 
3196   unsigned dst = fieldFromInstruction(Insn, 8, 3);
3197   unsigned imm = fieldFromInstruction(Insn, 0, 8);
3198 
3199   if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3200     return MCDisassembler::Fail;
3201 
3202   switch(Inst.getOpcode()) {
3203     default:
3204       return MCDisassembler::Fail;
3205     case ARM::tADR:
3206       break; // tADR does not explicitly represent the PC as an operand.
3207     case ARM::tADDrSPi:
3208       Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3209       break;
3210   }
3211 
3212   Inst.addOperand(MCOperand::CreateImm(imm));
3213   return S;
3214 }
3215 
DecodeThumbBROperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3216 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3217                                  uint64_t Address, const void *Decoder) {
3218   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3219                                 true, 2, Inst, Decoder))
3220     Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
3221   return MCDisassembler::Success;
3222 }
3223 
DecodeT2BROperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3224 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3225                                  uint64_t Address, const void *Decoder) {
3226   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3227                                 true, 4, Inst, Decoder))
3228     Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
3229   return MCDisassembler::Success;
3230 }
3231 
DecodeThumbCmpBROperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3232 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3233                                  uint64_t Address, const void *Decoder) {
3234   if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3235                                 true, 2, Inst, Decoder))
3236     Inst.addOperand(MCOperand::CreateImm(Val << 1));
3237   return MCDisassembler::Success;
3238 }
3239 
DecodeThumbAddrModeRR(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3240 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3241                                  uint64_t Address, const void *Decoder) {
3242   DecodeStatus S = MCDisassembler::Success;
3243 
3244   unsigned Rn = fieldFromInstruction(Val, 0, 3);
3245   unsigned Rm = fieldFromInstruction(Val, 3, 3);
3246 
3247   if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3248     return MCDisassembler::Fail;
3249   if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3250     return MCDisassembler::Fail;
3251 
3252   return S;
3253 }
3254 
DecodeThumbAddrModeIS(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3255 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3256                                   uint64_t Address, const void *Decoder) {
3257   DecodeStatus S = MCDisassembler::Success;
3258 
3259   unsigned Rn = fieldFromInstruction(Val, 0, 3);
3260   unsigned imm = fieldFromInstruction(Val, 3, 5);
3261 
3262   if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3263     return MCDisassembler::Fail;
3264   Inst.addOperand(MCOperand::CreateImm(imm));
3265 
3266   return S;
3267 }
3268 
DecodeThumbAddrModePC(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3269 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3270                                   uint64_t Address, const void *Decoder) {
3271   unsigned imm = Val << 2;
3272 
3273   Inst.addOperand(MCOperand::CreateImm(imm));
3274   tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3275 
3276   return MCDisassembler::Success;
3277 }
3278 
DecodeThumbAddrModeSP(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3279 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3280                                   uint64_t Address, const void *Decoder) {
3281   Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3282   Inst.addOperand(MCOperand::CreateImm(Val));
3283 
3284   return MCDisassembler::Success;
3285 }
3286 
DecodeT2AddrModeSOReg(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3287 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3288                                   uint64_t Address, const void *Decoder) {
3289   DecodeStatus S = MCDisassembler::Success;
3290 
3291   unsigned Rn = fieldFromInstruction(Val, 6, 4);
3292   unsigned Rm = fieldFromInstruction(Val, 2, 4);
3293   unsigned imm = fieldFromInstruction(Val, 0, 2);
3294 
3295   // Thumb stores cannot use PC as dest register.
3296   switch (Inst.getOpcode()) {
3297   case ARM::t2STRHs:
3298   case ARM::t2STRBs:
3299   case ARM::t2STRs:
3300     if (Rn == 15)
3301       return MCDisassembler::Fail;
3302   default:
3303     break;
3304   }
3305 
3306   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3307     return MCDisassembler::Fail;
3308   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3309     return MCDisassembler::Fail;
3310   Inst.addOperand(MCOperand::CreateImm(imm));
3311 
3312   return S;
3313 }
3314 
DecodeT2LoadShift(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3315 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3316                               uint64_t Address, const void *Decoder) {
3317   DecodeStatus S = MCDisassembler::Success;
3318 
3319   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3320   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3321 
3322   uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3323                                                           .getFeatureBits();
3324   bool hasMP = featureBits & ARM::FeatureMP;
3325   bool hasV7Ops = featureBits & ARM::HasV7Ops;
3326 
3327   if (Rn == 15) {
3328     switch (Inst.getOpcode()) {
3329     case ARM::t2LDRBs:
3330       Inst.setOpcode(ARM::t2LDRBpci);
3331       break;
3332     case ARM::t2LDRHs:
3333       Inst.setOpcode(ARM::t2LDRHpci);
3334       break;
3335     case ARM::t2LDRSHs:
3336       Inst.setOpcode(ARM::t2LDRSHpci);
3337       break;
3338     case ARM::t2LDRSBs:
3339       Inst.setOpcode(ARM::t2LDRSBpci);
3340       break;
3341     case ARM::t2LDRs:
3342       Inst.setOpcode(ARM::t2LDRpci);
3343       break;
3344     case ARM::t2PLDs:
3345       Inst.setOpcode(ARM::t2PLDpci);
3346       break;
3347     case ARM::t2PLIs:
3348       Inst.setOpcode(ARM::t2PLIpci);
3349       break;
3350     default:
3351       return MCDisassembler::Fail;
3352     }
3353 
3354     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3355   }
3356 
3357   if (Rt == 15) {
3358     switch (Inst.getOpcode()) {
3359     case ARM::t2LDRSHs:
3360       return MCDisassembler::Fail;
3361     case ARM::t2LDRHs:
3362       Inst.setOpcode(ARM::t2PLDWs);
3363       break;
3364     case ARM::t2LDRSBs:
3365       Inst.setOpcode(ARM::t2PLIs);
3366     default:
3367       break;
3368     }
3369   }
3370 
3371   switch (Inst.getOpcode()) {
3372     case ARM::t2PLDs:
3373       break;
3374     case ARM::t2PLIs:
3375       if (!hasV7Ops)
3376         return MCDisassembler::Fail;
3377       break;
3378     case ARM::t2PLDWs:
3379       if (!hasV7Ops || !hasMP)
3380         return MCDisassembler::Fail;
3381       break;
3382     default:
3383       if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3384         return MCDisassembler::Fail;
3385   }
3386 
3387   unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3388   addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3389   addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3390   if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3391     return MCDisassembler::Fail;
3392 
3393   return S;
3394 }
3395 
DecodeT2LoadImm8(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3396 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3397                                 uint64_t Address, const void* Decoder) {
3398   DecodeStatus S = MCDisassembler::Success;
3399 
3400   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3401   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3402   unsigned U = fieldFromInstruction(Insn, 9, 1);
3403   unsigned imm = fieldFromInstruction(Insn, 0, 8);
3404   imm |= (U << 8);
3405   imm |= (Rn << 9);
3406   unsigned add = fieldFromInstruction(Insn, 9, 1);
3407 
3408   uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3409                                                           .getFeatureBits();
3410   bool hasMP = featureBits & ARM::FeatureMP;
3411   bool hasV7Ops = featureBits & ARM::HasV7Ops;
3412 
3413   if (Rn == 15) {
3414     switch (Inst.getOpcode()) {
3415     case ARM::t2LDRi8:
3416       Inst.setOpcode(ARM::t2LDRpci);
3417       break;
3418     case ARM::t2LDRBi8:
3419       Inst.setOpcode(ARM::t2LDRBpci);
3420       break;
3421     case ARM::t2LDRSBi8:
3422       Inst.setOpcode(ARM::t2LDRSBpci);
3423       break;
3424     case ARM::t2LDRHi8:
3425       Inst.setOpcode(ARM::t2LDRHpci);
3426       break;
3427     case ARM::t2LDRSHi8:
3428       Inst.setOpcode(ARM::t2LDRSHpci);
3429       break;
3430     case ARM::t2PLDi8:
3431       Inst.setOpcode(ARM::t2PLDpci);
3432       break;
3433     case ARM::t2PLIi8:
3434       Inst.setOpcode(ARM::t2PLIpci);
3435       break;
3436     default:
3437       return MCDisassembler::Fail;
3438     }
3439     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3440   }
3441 
3442   if (Rt == 15) {
3443     switch (Inst.getOpcode()) {
3444     case ARM::t2LDRSHi8:
3445       return MCDisassembler::Fail;
3446     case ARM::t2LDRHi8:
3447       if (!add)
3448         Inst.setOpcode(ARM::t2PLDWi8);
3449       break;
3450     case ARM::t2LDRSBi8:
3451       Inst.setOpcode(ARM::t2PLIi8);
3452       break;
3453     default:
3454       break;
3455     }
3456   }
3457 
3458   switch (Inst.getOpcode()) {
3459   case ARM::t2PLDi8:
3460     break;
3461   case ARM::t2PLIi8:
3462     if (!hasV7Ops)
3463       return MCDisassembler::Fail;
3464     break;
3465   case ARM::t2PLDWi8:
3466       if (!hasV7Ops || !hasMP)
3467         return MCDisassembler::Fail;
3468       break;
3469   default:
3470     if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3471       return MCDisassembler::Fail;
3472   }
3473 
3474   if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3475     return MCDisassembler::Fail;
3476   return S;
3477 }
3478 
DecodeT2LoadImm12(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3479 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3480                                 uint64_t Address, const void* Decoder) {
3481   DecodeStatus S = MCDisassembler::Success;
3482 
3483   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3484   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3485   unsigned imm = fieldFromInstruction(Insn, 0, 12);
3486   imm |= (Rn << 13);
3487 
3488   uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3489                                                           .getFeatureBits();
3490   bool hasMP = (featureBits & ARM::FeatureMP);
3491   bool hasV7Ops = (featureBits & ARM::HasV7Ops);
3492 
3493   if (Rn == 15) {
3494     switch (Inst.getOpcode()) {
3495     case ARM::t2LDRi12:
3496       Inst.setOpcode(ARM::t2LDRpci);
3497       break;
3498     case ARM::t2LDRHi12:
3499       Inst.setOpcode(ARM::t2LDRHpci);
3500       break;
3501     case ARM::t2LDRSHi12:
3502       Inst.setOpcode(ARM::t2LDRSHpci);
3503       break;
3504     case ARM::t2LDRBi12:
3505       Inst.setOpcode(ARM::t2LDRBpci);
3506       break;
3507     case ARM::t2LDRSBi12:
3508       Inst.setOpcode(ARM::t2LDRSBpci);
3509       break;
3510     case ARM::t2PLDi12:
3511       Inst.setOpcode(ARM::t2PLDpci);
3512       break;
3513     case ARM::t2PLIi12:
3514       Inst.setOpcode(ARM::t2PLIpci);
3515       break;
3516     default:
3517       return MCDisassembler::Fail;
3518     }
3519     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3520   }
3521 
3522   if (Rt == 15) {
3523     switch (Inst.getOpcode()) {
3524     case ARM::t2LDRSHi12:
3525       return MCDisassembler::Fail;
3526     case ARM::t2LDRHi12:
3527       Inst.setOpcode(ARM::t2PLDWi12);
3528       break;
3529     case ARM::t2LDRSBi12:
3530       Inst.setOpcode(ARM::t2PLIi12);
3531       break;
3532     default:
3533       break;
3534     }
3535   }
3536 
3537   switch (Inst.getOpcode()) {
3538   case ARM::t2PLDi12:
3539     break;
3540   case ARM::t2PLIi12:
3541     if (!hasV7Ops)
3542       return MCDisassembler::Fail;
3543     break;
3544   case ARM::t2PLDWi12:
3545       if (!hasV7Ops || !hasMP)
3546         return MCDisassembler::Fail;
3547       break;
3548   default:
3549     if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3550       return MCDisassembler::Fail;
3551   }
3552 
3553   if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3554     return MCDisassembler::Fail;
3555   return S;
3556 }
3557 
DecodeT2LoadT(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3558 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3559                                 uint64_t Address, const void* Decoder) {
3560   DecodeStatus S = MCDisassembler::Success;
3561 
3562   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3563   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3564   unsigned imm = fieldFromInstruction(Insn, 0, 8);
3565   imm |= (Rn << 9);
3566 
3567   if (Rn == 15) {
3568     switch (Inst.getOpcode()) {
3569     case ARM::t2LDRT:
3570       Inst.setOpcode(ARM::t2LDRpci);
3571       break;
3572     case ARM::t2LDRBT:
3573       Inst.setOpcode(ARM::t2LDRBpci);
3574       break;
3575     case ARM::t2LDRHT:
3576       Inst.setOpcode(ARM::t2LDRHpci);
3577       break;
3578     case ARM::t2LDRSBT:
3579       Inst.setOpcode(ARM::t2LDRSBpci);
3580       break;
3581     case ARM::t2LDRSHT:
3582       Inst.setOpcode(ARM::t2LDRSHpci);
3583       break;
3584     default:
3585       return MCDisassembler::Fail;
3586     }
3587     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3588   }
3589 
3590   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3591     return MCDisassembler::Fail;
3592   if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3593     return MCDisassembler::Fail;
3594   return S;
3595 }
3596 
DecodeT2LoadLabel(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3597 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3598                                 uint64_t Address, const void* Decoder) {
3599   DecodeStatus S = MCDisassembler::Success;
3600 
3601   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3602   unsigned U = fieldFromInstruction(Insn, 23, 1);
3603   int imm = fieldFromInstruction(Insn, 0, 12);
3604 
3605   uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3606                                                           .getFeatureBits();
3607   bool hasV7Ops = (featureBits & ARM::HasV7Ops);
3608 
3609   if (Rt == 15) {
3610     switch (Inst.getOpcode()) {
3611       case ARM::t2LDRBpci:
3612       case ARM::t2LDRHpci:
3613         Inst.setOpcode(ARM::t2PLDpci);
3614         break;
3615       case ARM::t2LDRSBpci:
3616         Inst.setOpcode(ARM::t2PLIpci);
3617         break;
3618       case ARM::t2LDRSHpci:
3619         return MCDisassembler::Fail;
3620       default:
3621         break;
3622     }
3623   }
3624 
3625   switch(Inst.getOpcode()) {
3626   case ARM::t2PLDpci:
3627     break;
3628   case ARM::t2PLIpci:
3629     if (!hasV7Ops)
3630       return MCDisassembler::Fail;
3631     break;
3632   default:
3633     if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3634       return MCDisassembler::Fail;
3635   }
3636 
3637   if (!U) {
3638     // Special case for #-0.
3639     if (imm == 0)
3640       imm = INT32_MIN;
3641     else
3642       imm = -imm;
3643   }
3644   Inst.addOperand(MCOperand::CreateImm(imm));
3645 
3646   return S;
3647 }
3648 
DecodeT2Imm8S4(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3649 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3650                            uint64_t Address, const void *Decoder) {
3651   if (Val == 0)
3652     Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
3653   else {
3654     int imm = Val & 0xFF;
3655 
3656     if (!(Val & 0x100)) imm *= -1;
3657     Inst.addOperand(MCOperand::CreateImm(imm * 4));
3658   }
3659 
3660   return MCDisassembler::Success;
3661 }
3662 
DecodeT2AddrModeImm8s4(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3663 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3664                                    uint64_t Address, const void *Decoder) {
3665   DecodeStatus S = MCDisassembler::Success;
3666 
3667   unsigned Rn = fieldFromInstruction(Val, 9, 4);
3668   unsigned imm = fieldFromInstruction(Val, 0, 9);
3669 
3670   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3671     return MCDisassembler::Fail;
3672   if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3673     return MCDisassembler::Fail;
3674 
3675   return S;
3676 }
3677 
DecodeT2AddrModeImm0_1020s4(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3678 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3679                                    uint64_t Address, const void *Decoder) {
3680   DecodeStatus S = MCDisassembler::Success;
3681 
3682   unsigned Rn = fieldFromInstruction(Val, 8, 4);
3683   unsigned imm = fieldFromInstruction(Val, 0, 8);
3684 
3685   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3686     return MCDisassembler::Fail;
3687 
3688   Inst.addOperand(MCOperand::CreateImm(imm));
3689 
3690   return S;
3691 }
3692 
DecodeT2Imm8(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3693 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3694                          uint64_t Address, const void *Decoder) {
3695   int imm = Val & 0xFF;
3696   if (Val == 0)
3697     imm = INT32_MIN;
3698   else if (!(Val & 0x100))
3699     imm *= -1;
3700   Inst.addOperand(MCOperand::CreateImm(imm));
3701 
3702   return MCDisassembler::Success;
3703 }
3704 
3705 
DecodeT2AddrModeImm8(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3706 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3707                                  uint64_t Address, const void *Decoder) {
3708   DecodeStatus S = MCDisassembler::Success;
3709 
3710   unsigned Rn = fieldFromInstruction(Val, 9, 4);
3711   unsigned imm = fieldFromInstruction(Val, 0, 9);
3712 
3713   // Thumb stores cannot use PC as dest register.
3714   switch (Inst.getOpcode()) {
3715   case ARM::t2STRT:
3716   case ARM::t2STRBT:
3717   case ARM::t2STRHT:
3718   case ARM::t2STRi8:
3719   case ARM::t2STRHi8:
3720   case ARM::t2STRBi8:
3721     if (Rn == 15)
3722       return MCDisassembler::Fail;
3723     break;
3724   default:
3725     break;
3726   }
3727 
3728   // Some instructions always use an additive offset.
3729   switch (Inst.getOpcode()) {
3730     case ARM::t2LDRT:
3731     case ARM::t2LDRBT:
3732     case ARM::t2LDRHT:
3733     case ARM::t2LDRSBT:
3734     case ARM::t2LDRSHT:
3735     case ARM::t2STRT:
3736     case ARM::t2STRBT:
3737     case ARM::t2STRHT:
3738       imm |= 0x100;
3739       break;
3740     default:
3741       break;
3742   }
3743 
3744   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3745     return MCDisassembler::Fail;
3746   if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3747     return MCDisassembler::Fail;
3748 
3749   return S;
3750 }
3751 
DecodeT2LdStPre(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3752 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3753                                     uint64_t Address, const void *Decoder) {
3754   DecodeStatus S = MCDisassembler::Success;
3755 
3756   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3757   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3758   unsigned addr = fieldFromInstruction(Insn, 0, 8);
3759   addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3760   addr |= Rn << 9;
3761   unsigned load = fieldFromInstruction(Insn, 20, 1);
3762 
3763   if (Rn == 15) {
3764     switch (Inst.getOpcode()) {
3765     case ARM::t2LDR_PRE:
3766     case ARM::t2LDR_POST:
3767       Inst.setOpcode(ARM::t2LDRpci);
3768       break;
3769     case ARM::t2LDRB_PRE:
3770     case ARM::t2LDRB_POST:
3771       Inst.setOpcode(ARM::t2LDRBpci);
3772       break;
3773     case ARM::t2LDRH_PRE:
3774     case ARM::t2LDRH_POST:
3775       Inst.setOpcode(ARM::t2LDRHpci);
3776       break;
3777     case ARM::t2LDRSB_PRE:
3778     case ARM::t2LDRSB_POST:
3779       if (Rt == 15)
3780         Inst.setOpcode(ARM::t2PLIpci);
3781       else
3782         Inst.setOpcode(ARM::t2LDRSBpci);
3783       break;
3784     case ARM::t2LDRSH_PRE:
3785     case ARM::t2LDRSH_POST:
3786       Inst.setOpcode(ARM::t2LDRSHpci);
3787       break;
3788     default:
3789       return MCDisassembler::Fail;
3790     }
3791     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3792   }
3793 
3794   if (!load) {
3795     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3796       return MCDisassembler::Fail;
3797   }
3798 
3799   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3800     return MCDisassembler::Fail;
3801 
3802   if (load) {
3803     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3804       return MCDisassembler::Fail;
3805   }
3806 
3807   if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3808     return MCDisassembler::Fail;
3809 
3810   return S;
3811 }
3812 
DecodeT2AddrModeImm12(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3813 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3814                                   uint64_t Address, const void *Decoder) {
3815   DecodeStatus S = MCDisassembler::Success;
3816 
3817   unsigned Rn = fieldFromInstruction(Val, 13, 4);
3818   unsigned imm = fieldFromInstruction(Val, 0, 12);
3819 
3820   // Thumb stores cannot use PC as dest register.
3821   switch (Inst.getOpcode()) {
3822   case ARM::t2STRi12:
3823   case ARM::t2STRBi12:
3824   case ARM::t2STRHi12:
3825     if (Rn == 15)
3826       return MCDisassembler::Fail;
3827   default:
3828     break;
3829   }
3830 
3831   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3832     return MCDisassembler::Fail;
3833   Inst.addOperand(MCOperand::CreateImm(imm));
3834 
3835   return S;
3836 }
3837 
3838 
DecodeThumbAddSPImm(MCInst & Inst,uint16_t Insn,uint64_t Address,const void * Decoder)3839 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3840                                 uint64_t Address, const void *Decoder) {
3841   unsigned imm = fieldFromInstruction(Insn, 0, 7);
3842 
3843   Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3844   Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3845   Inst.addOperand(MCOperand::CreateImm(imm));
3846 
3847   return MCDisassembler::Success;
3848 }
3849 
DecodeThumbAddSPReg(MCInst & Inst,uint16_t Insn,uint64_t Address,const void * Decoder)3850 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3851                                 uint64_t Address, const void *Decoder) {
3852   DecodeStatus S = MCDisassembler::Success;
3853 
3854   if (Inst.getOpcode() == ARM::tADDrSP) {
3855     unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3856     Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3857 
3858     if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3859     return MCDisassembler::Fail;
3860     Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3861     if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3862     return MCDisassembler::Fail;
3863   } else if (Inst.getOpcode() == ARM::tADDspr) {
3864     unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3865 
3866     Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3867     Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3868     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3869     return MCDisassembler::Fail;
3870   }
3871 
3872   return S;
3873 }
3874 
DecodeThumbCPS(MCInst & Inst,uint16_t Insn,uint64_t Address,const void * Decoder)3875 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3876                            uint64_t Address, const void *Decoder) {
3877   unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3878   unsigned flags = fieldFromInstruction(Insn, 0, 3);
3879 
3880   Inst.addOperand(MCOperand::CreateImm(imod));
3881   Inst.addOperand(MCOperand::CreateImm(flags));
3882 
3883   return MCDisassembler::Success;
3884 }
3885 
DecodePostIdxReg(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3886 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3887                              uint64_t Address, const void *Decoder) {
3888   DecodeStatus S = MCDisassembler::Success;
3889   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3890   unsigned add = fieldFromInstruction(Insn, 4, 1);
3891 
3892   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3893     return MCDisassembler::Fail;
3894   Inst.addOperand(MCOperand::CreateImm(add));
3895 
3896   return S;
3897 }
3898 
DecodeThumbBLXOffset(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3899 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3900                                  uint64_t Address, const void *Decoder) {
3901   // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3902   // Note only one trailing zero not two.  Also the J1 and J2 values are from
3903   // the encoded instruction.  So here change to I1 and I2 values via:
3904   // I1 = NOT(J1 EOR S);
3905   // I2 = NOT(J2 EOR S);
3906   // and build the imm32 with two trailing zeros as documented:
3907   // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3908   unsigned S = (Val >> 23) & 1;
3909   unsigned J1 = (Val >> 22) & 1;
3910   unsigned J2 = (Val >> 21) & 1;
3911   unsigned I1 = !(J1 ^ S);
3912   unsigned I2 = !(J2 ^ S);
3913   unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3914   int imm32 = SignExtend32<25>(tmp << 1);
3915 
3916   if (!tryAddingSymbolicOperand(Address,
3917                                 (Address & ~2u) + imm32 + 4,
3918                                 true, 4, Inst, Decoder))
3919     Inst.addOperand(MCOperand::CreateImm(imm32));
3920   return MCDisassembler::Success;
3921 }
3922 
DecodeCoprocessor(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3923 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3924                               uint64_t Address, const void *Decoder) {
3925   if (Val == 0xA || Val == 0xB)
3926     return MCDisassembler::Fail;
3927 
3928   uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3929                                                           .getFeatureBits();
3930   if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
3931     return MCDisassembler::Fail;
3932 
3933   Inst.addOperand(MCOperand::CreateImm(Val));
3934   return MCDisassembler::Success;
3935 }
3936 
3937 static DecodeStatus
DecodeThumbTableBranch(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3938 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3939                        uint64_t Address, const void *Decoder) {
3940   DecodeStatus S = MCDisassembler::Success;
3941 
3942   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3943   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3944 
3945   if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3946   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3947     return MCDisassembler::Fail;
3948   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3949     return MCDisassembler::Fail;
3950   return S;
3951 }
3952 
3953 static DecodeStatus
DecodeThumb2BCCInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3954 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3955                            uint64_t Address, const void *Decoder) {
3956   DecodeStatus S = MCDisassembler::Success;
3957 
3958   unsigned pred = fieldFromInstruction(Insn, 22, 4);
3959   if (pred == 0xE || pred == 0xF) {
3960     unsigned opc = fieldFromInstruction(Insn, 4, 28);
3961     switch (opc) {
3962       default:
3963         return MCDisassembler::Fail;
3964       case 0xf3bf8f4:
3965         Inst.setOpcode(ARM::t2DSB);
3966         break;
3967       case 0xf3bf8f5:
3968         Inst.setOpcode(ARM::t2DMB);
3969         break;
3970       case 0xf3bf8f6:
3971         Inst.setOpcode(ARM::t2ISB);
3972         break;
3973     }
3974 
3975     unsigned imm = fieldFromInstruction(Insn, 0, 4);
3976     return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3977   }
3978 
3979   unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3980   brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3981   brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3982   brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3983   brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
3984 
3985   if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3986     return MCDisassembler::Fail;
3987   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3988     return MCDisassembler::Fail;
3989 
3990   return S;
3991 }
3992 
3993 // Decode a shifted immediate operand.  These basically consist
3994 // of an 8-bit value, and a 4-bit directive that specifies either
3995 // a splat operation or a rotation.
DecodeT2SOImm(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3996 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
3997                           uint64_t Address, const void *Decoder) {
3998   unsigned ctrl = fieldFromInstruction(Val, 10, 2);
3999   if (ctrl == 0) {
4000     unsigned byte = fieldFromInstruction(Val, 8, 2);
4001     unsigned imm = fieldFromInstruction(Val, 0, 8);
4002     switch (byte) {
4003       case 0:
4004         Inst.addOperand(MCOperand::CreateImm(imm));
4005         break;
4006       case 1:
4007         Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
4008         break;
4009       case 2:
4010         Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
4011         break;
4012       case 3:
4013         Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
4014                                              (imm << 8)  |  imm));
4015         break;
4016     }
4017   } else {
4018     unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4019     unsigned rot = fieldFromInstruction(Val, 7, 5);
4020     unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4021     Inst.addOperand(MCOperand::CreateImm(imm));
4022   }
4023 
4024   return MCDisassembler::Success;
4025 }
4026 
4027 static DecodeStatus
DecodeThumbBCCTargetOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4028 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
4029                             uint64_t Address, const void *Decoder){
4030   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
4031                                 true, 2, Inst, Decoder))
4032     Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
4033   return MCDisassembler::Success;
4034 }
4035 
DecodeThumbBLTargetOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4036 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
4037                                        uint64_t Address, const void *Decoder){
4038   // Val is passed in as S:J1:J2:imm10:imm11
4039   // Note no trailing zero after imm11.  Also the J1 and J2 values are from
4040   // the encoded instruction.  So here change to I1 and I2 values via:
4041   // I1 = NOT(J1 EOR S);
4042   // I2 = NOT(J2 EOR S);
4043   // and build the imm32 with one trailing zero as documented:
4044   // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
4045   unsigned S = (Val >> 23) & 1;
4046   unsigned J1 = (Val >> 22) & 1;
4047   unsigned J2 = (Val >> 21) & 1;
4048   unsigned I1 = !(J1 ^ S);
4049   unsigned I2 = !(J2 ^ S);
4050   unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4051   int imm32 = SignExtend32<25>(tmp << 1);
4052 
4053   if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
4054                                 true, 4, Inst, Decoder))
4055     Inst.addOperand(MCOperand::CreateImm(imm32));
4056   return MCDisassembler::Success;
4057 }
4058 
DecodeMemBarrierOption(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4059 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4060                                    uint64_t Address, const void *Decoder) {
4061   if (Val & ~0xf)
4062     return MCDisassembler::Fail;
4063 
4064   Inst.addOperand(MCOperand::CreateImm(Val));
4065   return MCDisassembler::Success;
4066 }
4067 
DecodeInstSyncBarrierOption(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4068 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4069                                         uint64_t Address, const void *Decoder) {
4070   if (Val & ~0xf)
4071     return MCDisassembler::Fail;
4072 
4073   Inst.addOperand(MCOperand::CreateImm(Val));
4074   return MCDisassembler::Success;
4075 }
4076 
DecodeMSRMask(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4077 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
4078                           uint64_t Address, const void *Decoder) {
4079   DecodeStatus S = MCDisassembler::Success;
4080   uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
4081                                                           .getFeatureBits();
4082   if (FeatureBits & ARM::FeatureMClass) {
4083     unsigned ValLow = Val & 0xff;
4084 
4085     // Validate the SYSm value first.
4086     switch (ValLow) {
4087     case  0: // apsr
4088     case  1: // iapsr
4089     case  2: // eapsr
4090     case  3: // xpsr
4091     case  5: // ipsr
4092     case  6: // epsr
4093     case  7: // iepsr
4094     case  8: // msp
4095     case  9: // psp
4096     case 16: // primask
4097     case 20: // control
4098       break;
4099     case 17: // basepri
4100     case 18: // basepri_max
4101     case 19: // faultmask
4102       if (!(FeatureBits & ARM::HasV7Ops))
4103         // Values basepri, basepri_max and faultmask are only valid for v7m.
4104         return MCDisassembler::Fail;
4105       break;
4106     default:
4107       return MCDisassembler::Fail;
4108     }
4109 
4110     if (Inst.getOpcode() == ARM::t2MSR_M) {
4111       unsigned Mask = fieldFromInstruction(Val, 10, 2);
4112       if (!(FeatureBits & ARM::HasV7Ops)) {
4113         // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4114         // unpredictable.
4115         if (Mask != 2)
4116           S = MCDisassembler::SoftFail;
4117       }
4118       else {
4119         // The ARMv7-M architecture stores an additional 2-bit mask value in
4120         // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4121         // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4122         // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4123         // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4124         // only if the processor includes the DSP extension.
4125         if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4126             (!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1)))
4127           S = MCDisassembler::SoftFail;
4128       }
4129     }
4130   } else {
4131     // A/R class
4132     if (Val == 0)
4133       return MCDisassembler::Fail;
4134   }
4135   Inst.addOperand(MCOperand::CreateImm(Val));
4136   return S;
4137 }
4138 
DecodeBankedReg(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4139 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4140                                     uint64_t Address, const void *Decoder) {
4141 
4142   unsigned R = fieldFromInstruction(Val, 5, 1);
4143   unsigned SysM = fieldFromInstruction(Val, 0, 5);
4144 
4145   // The table of encodings for these banked registers comes from B9.2.3 of the
4146   // ARM ARM. There are patterns, but nothing regular enough to make this logic
4147   // neater. So by fiat, these values are UNPREDICTABLE:
4148   if (!R) {
4149     if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4150         SysM == 0x1a || SysM == 0x1b)
4151       return MCDisassembler::SoftFail;
4152   } else {
4153     if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4154         SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4155       return MCDisassembler::SoftFail;
4156   }
4157 
4158   Inst.addOperand(MCOperand::CreateImm(Val));
4159   return MCDisassembler::Success;
4160 }
4161 
DecodeDoubleRegLoad(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4162 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4163                                         uint64_t Address, const void *Decoder) {
4164   DecodeStatus S = MCDisassembler::Success;
4165 
4166   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4167   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4168   unsigned pred = fieldFromInstruction(Insn, 28, 4);
4169 
4170   if (Rn == 0xF)
4171     S = MCDisassembler::SoftFail;
4172 
4173   if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4174     return MCDisassembler::Fail;
4175   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4176     return MCDisassembler::Fail;
4177   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4178     return MCDisassembler::Fail;
4179 
4180   return S;
4181 }
4182 
DecodeDoubleRegStore(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4183 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4184                                          uint64_t Address, const void *Decoder){
4185   DecodeStatus S = MCDisassembler::Success;
4186 
4187   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4188   unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4189   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4190   unsigned pred = fieldFromInstruction(Insn, 28, 4);
4191 
4192   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4193     return MCDisassembler::Fail;
4194 
4195   if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4196     S = MCDisassembler::SoftFail;
4197 
4198   if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4199     return MCDisassembler::Fail;
4200   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4201     return MCDisassembler::Fail;
4202   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4203     return MCDisassembler::Fail;
4204 
4205   return S;
4206 }
4207 
DecodeLDRPreImm(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4208 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4209                             uint64_t Address, const void *Decoder) {
4210   DecodeStatus S = MCDisassembler::Success;
4211 
4212   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4213   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4214   unsigned imm = fieldFromInstruction(Insn, 0, 12);
4215   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4216   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4217   unsigned pred = fieldFromInstruction(Insn, 28, 4);
4218 
4219   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4220 
4221   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4222     return MCDisassembler::Fail;
4223   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4224     return MCDisassembler::Fail;
4225   if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4226     return MCDisassembler::Fail;
4227   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4228     return MCDisassembler::Fail;
4229 
4230   return S;
4231 }
4232 
DecodeLDRPreReg(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4233 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4234                             uint64_t Address, const void *Decoder) {
4235   DecodeStatus S = MCDisassembler::Success;
4236 
4237   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4238   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4239   unsigned imm = fieldFromInstruction(Insn, 0, 12);
4240   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4241   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4242   unsigned pred = fieldFromInstruction(Insn, 28, 4);
4243   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4244 
4245   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4246   if (Rm == 0xF) S = MCDisassembler::SoftFail;
4247 
4248   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4249     return MCDisassembler::Fail;
4250   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4251     return MCDisassembler::Fail;
4252   if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4253     return MCDisassembler::Fail;
4254   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4255     return MCDisassembler::Fail;
4256 
4257   return S;
4258 }
4259 
4260 
DecodeSTRPreImm(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4261 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4262                             uint64_t Address, const void *Decoder) {
4263   DecodeStatus S = MCDisassembler::Success;
4264 
4265   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4266   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4267   unsigned imm = fieldFromInstruction(Insn, 0, 12);
4268   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4269   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4270   unsigned pred = fieldFromInstruction(Insn, 28, 4);
4271 
4272   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4273 
4274   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4275     return MCDisassembler::Fail;
4276   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4277     return MCDisassembler::Fail;
4278   if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4279     return MCDisassembler::Fail;
4280   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4281     return MCDisassembler::Fail;
4282 
4283   return S;
4284 }
4285 
DecodeSTRPreReg(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4286 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4287                             uint64_t Address, const void *Decoder) {
4288   DecodeStatus S = MCDisassembler::Success;
4289 
4290   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4291   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4292   unsigned imm = fieldFromInstruction(Insn, 0, 12);
4293   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4294   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4295   unsigned pred = fieldFromInstruction(Insn, 28, 4);
4296 
4297   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4298 
4299   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4300     return MCDisassembler::Fail;
4301   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4302     return MCDisassembler::Fail;
4303   if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4304     return MCDisassembler::Fail;
4305   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4306     return MCDisassembler::Fail;
4307 
4308   return S;
4309 }
4310 
DecodeVLD1LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4311 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4312                          uint64_t Address, const void *Decoder) {
4313   DecodeStatus S = MCDisassembler::Success;
4314 
4315   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4316   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4317   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4318   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4319   unsigned size = fieldFromInstruction(Insn, 10, 2);
4320 
4321   unsigned align = 0;
4322   unsigned index = 0;
4323   switch (size) {
4324     default:
4325       return MCDisassembler::Fail;
4326     case 0:
4327       if (fieldFromInstruction(Insn, 4, 1))
4328         return MCDisassembler::Fail; // UNDEFINED
4329       index = fieldFromInstruction(Insn, 5, 3);
4330       break;
4331     case 1:
4332       if (fieldFromInstruction(Insn, 5, 1))
4333         return MCDisassembler::Fail; // UNDEFINED
4334       index = fieldFromInstruction(Insn, 6, 2);
4335       if (fieldFromInstruction(Insn, 4, 1))
4336         align = 2;
4337       break;
4338     case 2:
4339       if (fieldFromInstruction(Insn, 6, 1))
4340         return MCDisassembler::Fail; // UNDEFINED
4341       index = fieldFromInstruction(Insn, 7, 1);
4342 
4343       switch (fieldFromInstruction(Insn, 4, 2)) {
4344         case 0 :
4345           align = 0; break;
4346         case 3:
4347           align = 4; break;
4348         default:
4349           return MCDisassembler::Fail;
4350       }
4351       break;
4352   }
4353 
4354   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4355     return MCDisassembler::Fail;
4356   if (Rm != 0xF) { // Writeback
4357     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4358       return MCDisassembler::Fail;
4359   }
4360   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4361     return MCDisassembler::Fail;
4362   Inst.addOperand(MCOperand::CreateImm(align));
4363   if (Rm != 0xF) {
4364     if (Rm != 0xD) {
4365       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4366         return MCDisassembler::Fail;
4367     } else
4368       Inst.addOperand(MCOperand::CreateReg(0));
4369   }
4370 
4371   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4372     return MCDisassembler::Fail;
4373   Inst.addOperand(MCOperand::CreateImm(index));
4374 
4375   return S;
4376 }
4377 
DecodeVST1LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4378 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4379                          uint64_t Address, const void *Decoder) {
4380   DecodeStatus S = MCDisassembler::Success;
4381 
4382   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4383   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4384   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4385   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4386   unsigned size = fieldFromInstruction(Insn, 10, 2);
4387 
4388   unsigned align = 0;
4389   unsigned index = 0;
4390   switch (size) {
4391     default:
4392       return MCDisassembler::Fail;
4393     case 0:
4394       if (fieldFromInstruction(Insn, 4, 1))
4395         return MCDisassembler::Fail; // UNDEFINED
4396       index = fieldFromInstruction(Insn, 5, 3);
4397       break;
4398     case 1:
4399       if (fieldFromInstruction(Insn, 5, 1))
4400         return MCDisassembler::Fail; // UNDEFINED
4401       index = fieldFromInstruction(Insn, 6, 2);
4402       if (fieldFromInstruction(Insn, 4, 1))
4403         align = 2;
4404       break;
4405     case 2:
4406       if (fieldFromInstruction(Insn, 6, 1))
4407         return MCDisassembler::Fail; // UNDEFINED
4408       index = fieldFromInstruction(Insn, 7, 1);
4409 
4410       switch (fieldFromInstruction(Insn, 4, 2)) {
4411         case 0:
4412           align = 0; break;
4413         case 3:
4414           align = 4; break;
4415         default:
4416           return MCDisassembler::Fail;
4417       }
4418       break;
4419   }
4420 
4421   if (Rm != 0xF) { // Writeback
4422     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4423     return MCDisassembler::Fail;
4424   }
4425   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4426     return MCDisassembler::Fail;
4427   Inst.addOperand(MCOperand::CreateImm(align));
4428   if (Rm != 0xF) {
4429     if (Rm != 0xD) {
4430       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4431     return MCDisassembler::Fail;
4432     } else
4433       Inst.addOperand(MCOperand::CreateReg(0));
4434   }
4435 
4436   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4437     return MCDisassembler::Fail;
4438   Inst.addOperand(MCOperand::CreateImm(index));
4439 
4440   return S;
4441 }
4442 
4443 
DecodeVLD2LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4444 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4445                          uint64_t Address, const void *Decoder) {
4446   DecodeStatus S = MCDisassembler::Success;
4447 
4448   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4449   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4450   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4451   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4452   unsigned size = fieldFromInstruction(Insn, 10, 2);
4453 
4454   unsigned align = 0;
4455   unsigned index = 0;
4456   unsigned inc = 1;
4457   switch (size) {
4458     default:
4459       return MCDisassembler::Fail;
4460     case 0:
4461       index = fieldFromInstruction(Insn, 5, 3);
4462       if (fieldFromInstruction(Insn, 4, 1))
4463         align = 2;
4464       break;
4465     case 1:
4466       index = fieldFromInstruction(Insn, 6, 2);
4467       if (fieldFromInstruction(Insn, 4, 1))
4468         align = 4;
4469       if (fieldFromInstruction(Insn, 5, 1))
4470         inc = 2;
4471       break;
4472     case 2:
4473       if (fieldFromInstruction(Insn, 5, 1))
4474         return MCDisassembler::Fail; // UNDEFINED
4475       index = fieldFromInstruction(Insn, 7, 1);
4476       if (fieldFromInstruction(Insn, 4, 1) != 0)
4477         align = 8;
4478       if (fieldFromInstruction(Insn, 6, 1))
4479         inc = 2;
4480       break;
4481   }
4482 
4483   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4484     return MCDisassembler::Fail;
4485   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4486     return MCDisassembler::Fail;
4487   if (Rm != 0xF) { // Writeback
4488     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4489       return MCDisassembler::Fail;
4490   }
4491   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4492     return MCDisassembler::Fail;
4493   Inst.addOperand(MCOperand::CreateImm(align));
4494   if (Rm != 0xF) {
4495     if (Rm != 0xD) {
4496       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4497         return MCDisassembler::Fail;
4498     } else
4499       Inst.addOperand(MCOperand::CreateReg(0));
4500   }
4501 
4502   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4503     return MCDisassembler::Fail;
4504   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4505     return MCDisassembler::Fail;
4506   Inst.addOperand(MCOperand::CreateImm(index));
4507 
4508   return S;
4509 }
4510 
DecodeVST2LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4511 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4512                          uint64_t Address, const void *Decoder) {
4513   DecodeStatus S = MCDisassembler::Success;
4514 
4515   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4516   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4517   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4518   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4519   unsigned size = fieldFromInstruction(Insn, 10, 2);
4520 
4521   unsigned align = 0;
4522   unsigned index = 0;
4523   unsigned inc = 1;
4524   switch (size) {
4525     default:
4526       return MCDisassembler::Fail;
4527     case 0:
4528       index = fieldFromInstruction(Insn, 5, 3);
4529       if (fieldFromInstruction(Insn, 4, 1))
4530         align = 2;
4531       break;
4532     case 1:
4533       index = fieldFromInstruction(Insn, 6, 2);
4534       if (fieldFromInstruction(Insn, 4, 1))
4535         align = 4;
4536       if (fieldFromInstruction(Insn, 5, 1))
4537         inc = 2;
4538       break;
4539     case 2:
4540       if (fieldFromInstruction(Insn, 5, 1))
4541         return MCDisassembler::Fail; // UNDEFINED
4542       index = fieldFromInstruction(Insn, 7, 1);
4543       if (fieldFromInstruction(Insn, 4, 1) != 0)
4544         align = 8;
4545       if (fieldFromInstruction(Insn, 6, 1))
4546         inc = 2;
4547       break;
4548   }
4549 
4550   if (Rm != 0xF) { // Writeback
4551     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4552       return MCDisassembler::Fail;
4553   }
4554   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4555     return MCDisassembler::Fail;
4556   Inst.addOperand(MCOperand::CreateImm(align));
4557   if (Rm != 0xF) {
4558     if (Rm != 0xD) {
4559       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4560         return MCDisassembler::Fail;
4561     } else
4562       Inst.addOperand(MCOperand::CreateReg(0));
4563   }
4564 
4565   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4566     return MCDisassembler::Fail;
4567   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4568     return MCDisassembler::Fail;
4569   Inst.addOperand(MCOperand::CreateImm(index));
4570 
4571   return S;
4572 }
4573 
4574 
DecodeVLD3LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4575 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4576                          uint64_t Address, const void *Decoder) {
4577   DecodeStatus S = MCDisassembler::Success;
4578 
4579   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4580   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4581   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4582   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4583   unsigned size = fieldFromInstruction(Insn, 10, 2);
4584 
4585   unsigned align = 0;
4586   unsigned index = 0;
4587   unsigned inc = 1;
4588   switch (size) {
4589     default:
4590       return MCDisassembler::Fail;
4591     case 0:
4592       if (fieldFromInstruction(Insn, 4, 1))
4593         return MCDisassembler::Fail; // UNDEFINED
4594       index = fieldFromInstruction(Insn, 5, 3);
4595       break;
4596     case 1:
4597       if (fieldFromInstruction(Insn, 4, 1))
4598         return MCDisassembler::Fail; // UNDEFINED
4599       index = fieldFromInstruction(Insn, 6, 2);
4600       if (fieldFromInstruction(Insn, 5, 1))
4601         inc = 2;
4602       break;
4603     case 2:
4604       if (fieldFromInstruction(Insn, 4, 2))
4605         return MCDisassembler::Fail; // UNDEFINED
4606       index = fieldFromInstruction(Insn, 7, 1);
4607       if (fieldFromInstruction(Insn, 6, 1))
4608         inc = 2;
4609       break;
4610   }
4611 
4612   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4613     return MCDisassembler::Fail;
4614   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4615     return MCDisassembler::Fail;
4616   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4617     return MCDisassembler::Fail;
4618 
4619   if (Rm != 0xF) { // Writeback
4620     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4621     return MCDisassembler::Fail;
4622   }
4623   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4624     return MCDisassembler::Fail;
4625   Inst.addOperand(MCOperand::CreateImm(align));
4626   if (Rm != 0xF) {
4627     if (Rm != 0xD) {
4628       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4629     return MCDisassembler::Fail;
4630     } else
4631       Inst.addOperand(MCOperand::CreateReg(0));
4632   }
4633 
4634   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4635     return MCDisassembler::Fail;
4636   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4637     return MCDisassembler::Fail;
4638   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4639     return MCDisassembler::Fail;
4640   Inst.addOperand(MCOperand::CreateImm(index));
4641 
4642   return S;
4643 }
4644 
DecodeVST3LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4645 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4646                          uint64_t Address, const void *Decoder) {
4647   DecodeStatus S = MCDisassembler::Success;
4648 
4649   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4650   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4651   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4652   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4653   unsigned size = fieldFromInstruction(Insn, 10, 2);
4654 
4655   unsigned align = 0;
4656   unsigned index = 0;
4657   unsigned inc = 1;
4658   switch (size) {
4659     default:
4660       return MCDisassembler::Fail;
4661     case 0:
4662       if (fieldFromInstruction(Insn, 4, 1))
4663         return MCDisassembler::Fail; // UNDEFINED
4664       index = fieldFromInstruction(Insn, 5, 3);
4665       break;
4666     case 1:
4667       if (fieldFromInstruction(Insn, 4, 1))
4668         return MCDisassembler::Fail; // UNDEFINED
4669       index = fieldFromInstruction(Insn, 6, 2);
4670       if (fieldFromInstruction(Insn, 5, 1))
4671         inc = 2;
4672       break;
4673     case 2:
4674       if (fieldFromInstruction(Insn, 4, 2))
4675         return MCDisassembler::Fail; // UNDEFINED
4676       index = fieldFromInstruction(Insn, 7, 1);
4677       if (fieldFromInstruction(Insn, 6, 1))
4678         inc = 2;
4679       break;
4680   }
4681 
4682   if (Rm != 0xF) { // Writeback
4683     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4684     return MCDisassembler::Fail;
4685   }
4686   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4687     return MCDisassembler::Fail;
4688   Inst.addOperand(MCOperand::CreateImm(align));
4689   if (Rm != 0xF) {
4690     if (Rm != 0xD) {
4691       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4692     return MCDisassembler::Fail;
4693     } else
4694       Inst.addOperand(MCOperand::CreateReg(0));
4695   }
4696 
4697   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4698     return MCDisassembler::Fail;
4699   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4700     return MCDisassembler::Fail;
4701   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4702     return MCDisassembler::Fail;
4703   Inst.addOperand(MCOperand::CreateImm(index));
4704 
4705   return S;
4706 }
4707 
4708 
DecodeVLD4LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4709 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4710                          uint64_t Address, const void *Decoder) {
4711   DecodeStatus S = MCDisassembler::Success;
4712 
4713   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4714   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4715   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4716   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4717   unsigned size = fieldFromInstruction(Insn, 10, 2);
4718 
4719   unsigned align = 0;
4720   unsigned index = 0;
4721   unsigned inc = 1;
4722   switch (size) {
4723     default:
4724       return MCDisassembler::Fail;
4725     case 0:
4726       if (fieldFromInstruction(Insn, 4, 1))
4727         align = 4;
4728       index = fieldFromInstruction(Insn, 5, 3);
4729       break;
4730     case 1:
4731       if (fieldFromInstruction(Insn, 4, 1))
4732         align = 8;
4733       index = fieldFromInstruction(Insn, 6, 2);
4734       if (fieldFromInstruction(Insn, 5, 1))
4735         inc = 2;
4736       break;
4737     case 2:
4738       switch (fieldFromInstruction(Insn, 4, 2)) {
4739         case 0:
4740           align = 0; break;
4741         case 3:
4742           return MCDisassembler::Fail;
4743         default:
4744           align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4745       }
4746 
4747       index = fieldFromInstruction(Insn, 7, 1);
4748       if (fieldFromInstruction(Insn, 6, 1))
4749         inc = 2;
4750       break;
4751   }
4752 
4753   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4754     return MCDisassembler::Fail;
4755   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4756     return MCDisassembler::Fail;
4757   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4758     return MCDisassembler::Fail;
4759   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4760     return MCDisassembler::Fail;
4761 
4762   if (Rm != 0xF) { // Writeback
4763     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4764       return MCDisassembler::Fail;
4765   }
4766   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4767     return MCDisassembler::Fail;
4768   Inst.addOperand(MCOperand::CreateImm(align));
4769   if (Rm != 0xF) {
4770     if (Rm != 0xD) {
4771       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4772         return MCDisassembler::Fail;
4773     } else
4774       Inst.addOperand(MCOperand::CreateReg(0));
4775   }
4776 
4777   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4778     return MCDisassembler::Fail;
4779   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4780     return MCDisassembler::Fail;
4781   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4782     return MCDisassembler::Fail;
4783   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4784     return MCDisassembler::Fail;
4785   Inst.addOperand(MCOperand::CreateImm(index));
4786 
4787   return S;
4788 }
4789 
DecodeVST4LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4790 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4791                          uint64_t Address, const void *Decoder) {
4792   DecodeStatus S = MCDisassembler::Success;
4793 
4794   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4795   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4796   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4797   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4798   unsigned size = fieldFromInstruction(Insn, 10, 2);
4799 
4800   unsigned align = 0;
4801   unsigned index = 0;
4802   unsigned inc = 1;
4803   switch (size) {
4804     default:
4805       return MCDisassembler::Fail;
4806     case 0:
4807       if (fieldFromInstruction(Insn, 4, 1))
4808         align = 4;
4809       index = fieldFromInstruction(Insn, 5, 3);
4810       break;
4811     case 1:
4812       if (fieldFromInstruction(Insn, 4, 1))
4813         align = 8;
4814       index = fieldFromInstruction(Insn, 6, 2);
4815       if (fieldFromInstruction(Insn, 5, 1))
4816         inc = 2;
4817       break;
4818     case 2:
4819       switch (fieldFromInstruction(Insn, 4, 2)) {
4820         case 0:
4821           align = 0; break;
4822         case 3:
4823           return MCDisassembler::Fail;
4824         default:
4825           align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4826       }
4827 
4828       index = fieldFromInstruction(Insn, 7, 1);
4829       if (fieldFromInstruction(Insn, 6, 1))
4830         inc = 2;
4831       break;
4832   }
4833 
4834   if (Rm != 0xF) { // Writeback
4835     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4836     return MCDisassembler::Fail;
4837   }
4838   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4839     return MCDisassembler::Fail;
4840   Inst.addOperand(MCOperand::CreateImm(align));
4841   if (Rm != 0xF) {
4842     if (Rm != 0xD) {
4843       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4844     return MCDisassembler::Fail;
4845     } else
4846       Inst.addOperand(MCOperand::CreateReg(0));
4847   }
4848 
4849   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4850     return MCDisassembler::Fail;
4851   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4852     return MCDisassembler::Fail;
4853   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4854     return MCDisassembler::Fail;
4855   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4856     return MCDisassembler::Fail;
4857   Inst.addOperand(MCOperand::CreateImm(index));
4858 
4859   return S;
4860 }
4861 
DecodeVMOVSRR(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4862 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4863                                   uint64_t Address, const void *Decoder) {
4864   DecodeStatus S = MCDisassembler::Success;
4865   unsigned Rt  = fieldFromInstruction(Insn, 12, 4);
4866   unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4867   unsigned Rm  = fieldFromInstruction(Insn,  5, 1);
4868   unsigned pred = fieldFromInstruction(Insn, 28, 4);
4869   Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4870 
4871   if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4872     S = MCDisassembler::SoftFail;
4873 
4874   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
4875     return MCDisassembler::Fail;
4876   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4877     return MCDisassembler::Fail;
4878   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
4879     return MCDisassembler::Fail;
4880   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4881     return MCDisassembler::Fail;
4882   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4883     return MCDisassembler::Fail;
4884 
4885   return S;
4886 }
4887 
DecodeVMOVRRS(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4888 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4889                                   uint64_t Address, const void *Decoder) {
4890   DecodeStatus S = MCDisassembler::Success;
4891   unsigned Rt  = fieldFromInstruction(Insn, 12, 4);
4892   unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4893   unsigned Rm  = fieldFromInstruction(Insn,  5, 1);
4894   unsigned pred = fieldFromInstruction(Insn, 28, 4);
4895   Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4896 
4897   if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4898     S = MCDisassembler::SoftFail;
4899 
4900   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
4901     return MCDisassembler::Fail;
4902   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4903     return MCDisassembler::Fail;
4904   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
4905     return MCDisassembler::Fail;
4906   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4907     return MCDisassembler::Fail;
4908   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4909     return MCDisassembler::Fail;
4910 
4911   return S;
4912 }
4913 
DecodeIT(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4914 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4915                              uint64_t Address, const void *Decoder) {
4916   DecodeStatus S = MCDisassembler::Success;
4917   unsigned pred = fieldFromInstruction(Insn, 4, 4);
4918   unsigned mask = fieldFromInstruction(Insn, 0, 4);
4919 
4920   if (pred == 0xF) {
4921     pred = 0xE;
4922     S = MCDisassembler::SoftFail;
4923   }
4924 
4925   if (mask == 0x0)
4926     return MCDisassembler::Fail;
4927 
4928   Inst.addOperand(MCOperand::CreateImm(pred));
4929   Inst.addOperand(MCOperand::CreateImm(mask));
4930   return S;
4931 }
4932 
4933 static DecodeStatus
DecodeT2LDRDPreInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4934 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4935                            uint64_t Address, const void *Decoder) {
4936   DecodeStatus S = MCDisassembler::Success;
4937 
4938   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4939   unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4940   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4941   unsigned addr = fieldFromInstruction(Insn, 0, 8);
4942   unsigned W = fieldFromInstruction(Insn, 21, 1);
4943   unsigned U = fieldFromInstruction(Insn, 23, 1);
4944   unsigned P = fieldFromInstruction(Insn, 24, 1);
4945   bool writeback = (W == 1) | (P == 0);
4946 
4947   addr |= (U << 8) | (Rn << 9);
4948 
4949   if (writeback && (Rn == Rt || Rn == Rt2))
4950     Check(S, MCDisassembler::SoftFail);
4951   if (Rt == Rt2)
4952     Check(S, MCDisassembler::SoftFail);
4953 
4954   // Rt
4955   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4956     return MCDisassembler::Fail;
4957   // Rt2
4958   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4959     return MCDisassembler::Fail;
4960   // Writeback operand
4961   if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4962     return MCDisassembler::Fail;
4963   // addr
4964   if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4965     return MCDisassembler::Fail;
4966 
4967   return S;
4968 }
4969 
4970 static DecodeStatus
DecodeT2STRDPreInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4971 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4972                            uint64_t Address, const void *Decoder) {
4973   DecodeStatus S = MCDisassembler::Success;
4974 
4975   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4976   unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4977   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4978   unsigned addr = fieldFromInstruction(Insn, 0, 8);
4979   unsigned W = fieldFromInstruction(Insn, 21, 1);
4980   unsigned U = fieldFromInstruction(Insn, 23, 1);
4981   unsigned P = fieldFromInstruction(Insn, 24, 1);
4982   bool writeback = (W == 1) | (P == 0);
4983 
4984   addr |= (U << 8) | (Rn << 9);
4985 
4986   if (writeback && (Rn == Rt || Rn == Rt2))
4987     Check(S, MCDisassembler::SoftFail);
4988 
4989   // Writeback operand
4990   if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4991     return MCDisassembler::Fail;
4992   // Rt
4993   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4994     return MCDisassembler::Fail;
4995   // Rt2
4996   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4997     return MCDisassembler::Fail;
4998   // addr
4999   if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5000     return MCDisassembler::Fail;
5001 
5002   return S;
5003 }
5004 
DecodeT2Adr(MCInst & Inst,uint32_t Insn,uint64_t Address,const void * Decoder)5005 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
5006                                 uint64_t Address, const void *Decoder) {
5007   unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5008   unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
5009   if (sign1 != sign2) return MCDisassembler::Fail;
5010 
5011   unsigned Val = fieldFromInstruction(Insn, 0, 8);
5012   Val |= fieldFromInstruction(Insn, 12, 3) << 8;
5013   Val |= fieldFromInstruction(Insn, 26, 1) << 11;
5014   Val |= sign1 << 12;
5015   Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
5016 
5017   return MCDisassembler::Success;
5018 }
5019 
DecodeT2ShifterImmOperand(MCInst & Inst,uint32_t Val,uint64_t Address,const void * Decoder)5020 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
5021                                               uint64_t Address,
5022                                               const void *Decoder) {
5023   DecodeStatus S = MCDisassembler::Success;
5024 
5025   // Shift of "asr #32" is not allowed in Thumb2 mode.
5026   if (Val == 0x20) S = MCDisassembler::Fail;
5027   Inst.addOperand(MCOperand::CreateImm(Val));
5028   return S;
5029 }
5030 
DecodeSwap(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5031 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
5032                                uint64_t Address, const void *Decoder) {
5033   unsigned Rt   = fieldFromInstruction(Insn, 12, 4);
5034   unsigned Rt2  = fieldFromInstruction(Insn, 0,  4);
5035   unsigned Rn   = fieldFromInstruction(Insn, 16, 4);
5036   unsigned pred = fieldFromInstruction(Insn, 28, 4);
5037 
5038   if (pred == 0xF)
5039     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
5040 
5041   DecodeStatus S = MCDisassembler::Success;
5042 
5043   if (Rt == Rn || Rn == Rt2)
5044     S = MCDisassembler::SoftFail;
5045 
5046   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5047     return MCDisassembler::Fail;
5048   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5049     return MCDisassembler::Fail;
5050   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5051     return MCDisassembler::Fail;
5052   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5053     return MCDisassembler::Fail;
5054 
5055   return S;
5056 }
5057 
DecodeVCVTD(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5058 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
5059                                 uint64_t Address, const void *Decoder) {
5060   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5061   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5062   unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5063   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5064   unsigned imm = fieldFromInstruction(Insn, 16, 6);
5065   unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5066   unsigned op = fieldFromInstruction(Insn, 5, 1);
5067 
5068   DecodeStatus S = MCDisassembler::Success;
5069 
5070   // VMOVv2f32 is ambiguous with these decodings.
5071   if (!(imm & 0x38) && cmode == 0xF) {
5072     if (op == 1) return MCDisassembler::Fail;
5073     Inst.setOpcode(ARM::VMOVv2f32);
5074     return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5075   }
5076 
5077   if (!(imm & 0x20)) return MCDisassembler::Fail;
5078 
5079   if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5080     return MCDisassembler::Fail;
5081   if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5082     return MCDisassembler::Fail;
5083   Inst.addOperand(MCOperand::CreateImm(64 - imm));
5084 
5085   return S;
5086 }
5087 
DecodeVCVTQ(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5088 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
5089                                 uint64_t Address, const void *Decoder) {
5090   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5091   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5092   unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5093   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5094   unsigned imm = fieldFromInstruction(Insn, 16, 6);
5095   unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5096   unsigned op = fieldFromInstruction(Insn, 5, 1);
5097 
5098   DecodeStatus S = MCDisassembler::Success;
5099 
5100   // VMOVv4f32 is ambiguous with these decodings.
5101   if (!(imm & 0x38) && cmode == 0xF) {
5102     if (op == 1) return MCDisassembler::Fail;
5103     Inst.setOpcode(ARM::VMOVv4f32);
5104     return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5105   }
5106 
5107   if (!(imm & 0x20)) return MCDisassembler::Fail;
5108 
5109   if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5110     return MCDisassembler::Fail;
5111   if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5112     return MCDisassembler::Fail;
5113   Inst.addOperand(MCOperand::CreateImm(64 - imm));
5114 
5115   return S;
5116 }
5117 
DecodeLDR(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)5118 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
5119                                 uint64_t Address, const void *Decoder) {
5120   DecodeStatus S = MCDisassembler::Success;
5121 
5122   unsigned Rn = fieldFromInstruction(Val, 16, 4);
5123   unsigned Rt = fieldFromInstruction(Val, 12, 4);
5124   unsigned Rm = fieldFromInstruction(Val, 0, 4);
5125   Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5126   unsigned Cond = fieldFromInstruction(Val, 28, 4);
5127 
5128   if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5129     S = MCDisassembler::SoftFail;
5130 
5131   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5132     return MCDisassembler::Fail;
5133   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5134     return MCDisassembler::Fail;
5135   if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5136     return MCDisassembler::Fail;
5137   if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5138     return MCDisassembler::Fail;
5139   if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5140     return MCDisassembler::Fail;
5141 
5142   return S;
5143 }
5144 
DecodeMRRC2(llvm::MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)5145 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
5146                                 uint64_t Address, const void *Decoder) {
5147 
5148   DecodeStatus S = MCDisassembler::Success;
5149 
5150   unsigned CRm = fieldFromInstruction(Val, 0, 4);
5151   unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5152   unsigned cop = fieldFromInstruction(Val, 8, 4);
5153   unsigned Rt = fieldFromInstruction(Val, 12, 4);
5154   unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5155 
5156   if ((cop & ~0x1) == 0xa)
5157     return MCDisassembler::Fail;
5158 
5159   if (Rt == Rt2)
5160     S = MCDisassembler::SoftFail;
5161 
5162   Inst.addOperand(MCOperand::CreateImm(cop));
5163   Inst.addOperand(MCOperand::CreateImm(opc1));
5164   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5165     return MCDisassembler::Fail;
5166   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5167     return MCDisassembler::Fail;
5168   Inst.addOperand(MCOperand::CreateImm(CRm));
5169 
5170   return S;
5171 }
5172 
5173