1//===-- BPFInstrInfo.td - Target Description for BPF Target ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the BPF instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14include "BPFInstrFormats.td" 15 16// Instruction Operands and Patterns 17 18// These are target-independent nodes, but have target-specific formats. 19def SDT_BPFCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>]>; 20def SDT_BPFCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 21def SDT_BPFCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 22def SDT_BPFSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>; 23def SDT_BPFSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>, 24 SDTCisSameAs<0, 4>, 25 SDTCisSameAs<4, 5>]>; 26def SDT_BPFBrCC : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>, 27 SDTCisVT<3, OtherVT>]>; 28def SDT_BPFWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 29 SDTCisPtrTy<0>]>; 30 31def BPFcall : SDNode<"BPFISD::CALL", SDT_BPFCall, 32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 33 SDNPVariadic]>; 34def BPFretflag : SDNode<"BPFISD::RET_FLAG", SDTNone, 35 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 36def BPFcallseq_start: SDNode<"ISD::CALLSEQ_START", SDT_BPFCallSeqStart, 37 [SDNPHasChain, SDNPOutGlue]>; 38def BPFcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_BPFCallSeqEnd, 39 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 40def BPFbrcc : SDNode<"BPFISD::BR_CC", SDT_BPFBrCC, 41 [SDNPHasChain, SDNPOutGlue, SDNPInGlue]>; 42 43def BPFselectcc : SDNode<"BPFISD::SELECT_CC", SDT_BPFSelectCC, [SDNPInGlue]>; 44def BPFWrapper : SDNode<"BPFISD::Wrapper", SDT_BPFWrapper>; 45 46def brtarget : Operand<OtherVT>; 47def calltarget : Operand<i64>; 48 49def u64imm : Operand<i64> { 50 let PrintMethod = "printImm64Operand"; 51} 52 53def i64immSExt32 : PatLeaf<(imm), 54 [{return isInt<32>(N->getSExtValue()); }]>; 55 56// Addressing modes. 57def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [frameindex], []>; 58 59// Address operands 60def MEMri : Operand<i64> { 61 let PrintMethod = "printMemOperand"; 62 let EncoderMethod = "getMemoryOpValue"; 63 let MIOperandInfo = (ops GPR, i16imm); 64} 65 66// Conditional code predicates - used for pattern matching for jump instructions 67def BPF_CC_EQ : PatLeaf<(imm), 68 [{return (N->getZExtValue() == ISD::SETEQ);}]>; 69def BPF_CC_NE : PatLeaf<(imm), 70 [{return (N->getZExtValue() == ISD::SETNE);}]>; 71def BPF_CC_GE : PatLeaf<(imm), 72 [{return (N->getZExtValue() == ISD::SETGE);}]>; 73def BPF_CC_GT : PatLeaf<(imm), 74 [{return (N->getZExtValue() == ISD::SETGT);}]>; 75def BPF_CC_GTU : PatLeaf<(imm), 76 [{return (N->getZExtValue() == ISD::SETUGT);}]>; 77def BPF_CC_GEU : PatLeaf<(imm), 78 [{return (N->getZExtValue() == ISD::SETUGE);}]>; 79 80// jump instructions 81class JMP_RR<bits<4> Opc, string OpcodeStr, PatLeaf Cond> 82 : InstBPF<(outs), (ins GPR:$dst, GPR:$src, brtarget:$BrDst), 83 !strconcat(OpcodeStr, "\t$dst, $src goto $BrDst"), 84 [(BPFbrcc i64:$dst, i64:$src, Cond, bb:$BrDst)]> { 85 bits<4> op; 86 bits<1> BPFSrc; 87 bits<4> dst; 88 bits<4> src; 89 bits<16> BrDst; 90 91 let Inst{63-60} = op; 92 let Inst{59} = BPFSrc; 93 let Inst{55-52} = src; 94 let Inst{51-48} = dst; 95 let Inst{47-32} = BrDst; 96 97 let op = Opc; 98 let BPFSrc = 1; 99 let BPFClass = 5; // BPF_JMP 100} 101 102class JMP_RI<bits<4> Opc, string OpcodeStr, PatLeaf Cond> 103 : InstBPF<(outs), (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst), 104 !strconcat(OpcodeStr, "i\t$dst, $imm goto $BrDst"), 105 [(BPFbrcc i64:$dst, i64immSExt32:$imm, Cond, bb:$BrDst)]> { 106 bits<4> op; 107 bits<1> BPFSrc; 108 bits<4> dst; 109 bits<16> BrDst; 110 bits<32> imm; 111 112 let Inst{63-60} = op; 113 let Inst{59} = BPFSrc; 114 let Inst{51-48} = dst; 115 let Inst{47-32} = BrDst; 116 let Inst{31-0} = imm; 117 118 let op = Opc; 119 let BPFSrc = 0; 120 let BPFClass = 5; // BPF_JMP 121} 122 123multiclass J<bits<4> Opc, string OpcodeStr, PatLeaf Cond> { 124 def _rr : JMP_RR<Opc, OpcodeStr, Cond>; 125 def _ri : JMP_RI<Opc, OpcodeStr, Cond>; 126} 127 128let isBranch = 1, isTerminator = 1, hasDelaySlot=0 in { 129// cmp+goto instructions 130defm JEQ : J<0x1, "jeq", BPF_CC_EQ>; 131defm JUGT : J<0x2, "jgt", BPF_CC_GTU>; 132defm JUGE : J<0x3, "jge", BPF_CC_GEU>; 133defm JNE : J<0x5, "jne", BPF_CC_NE>; 134defm JSGT : J<0x6, "jsgt", BPF_CC_GT>; 135defm JSGE : J<0x7, "jsge", BPF_CC_GE>; 136} 137 138// ALU instructions 139class ALU_RI<bits<4> Opc, string OpcodeStr, SDNode OpNode> 140 : InstBPF<(outs GPR:$dst), (ins GPR:$src2, i64imm:$imm), 141 !strconcat(OpcodeStr, "i\t$dst, $imm"), 142 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]> { 143 bits<4> op; 144 bits<1> BPFSrc; 145 bits<4> dst; 146 bits<32> imm; 147 148 let Inst{63-60} = op; 149 let Inst{59} = BPFSrc; 150 let Inst{51-48} = dst; 151 let Inst{31-0} = imm; 152 153 let op = Opc; 154 let BPFSrc = 0; 155 let BPFClass = 7; // BPF_ALU64 156} 157 158class ALU_RR<bits<4> Opc, string OpcodeStr, SDNode OpNode> 159 : InstBPF<(outs GPR:$dst), (ins GPR:$src2, GPR:$src), 160 !strconcat(OpcodeStr, "\t$dst, $src"), 161 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]> { 162 bits<4> op; 163 bits<1> BPFSrc; 164 bits<4> dst; 165 bits<4> src; 166 167 let Inst{63-60} = op; 168 let Inst{59} = BPFSrc; 169 let Inst{55-52} = src; 170 let Inst{51-48} = dst; 171 172 let op = Opc; 173 let BPFSrc = 1; 174 let BPFClass = 7; // BPF_ALU64 175} 176 177multiclass ALU<bits<4> Opc, string OpcodeStr, SDNode OpNode> { 178 def _rr : ALU_RR<Opc, OpcodeStr, OpNode>; 179 def _ri : ALU_RI<Opc, OpcodeStr, OpNode>; 180} 181 182let Constraints = "$dst = $src2" in { 183let isAsCheapAsAMove = 1 in { 184 defm ADD : ALU<0x0, "add", add>; 185 defm SUB : ALU<0x1, "sub", sub>; 186 defm OR : ALU<0x4, "or", or>; 187 defm AND : ALU<0x5, "and", and>; 188 defm SLL : ALU<0x6, "sll", shl>; 189 defm SRL : ALU<0x7, "srl", srl>; 190 defm XOR : ALU<0xa, "xor", xor>; 191 defm SRA : ALU<0xc, "sra", sra>; 192} 193 defm MUL : ALU<0x2, "mul", mul>; 194 defm DIV : ALU<0x3, "div", udiv>; 195} 196 197class MOV_RR<string OpcodeStr> 198 : InstBPF<(outs GPR:$dst), (ins GPR:$src), 199 !strconcat(OpcodeStr, "\t$dst, $src"), 200 []> { 201 bits<4> op; 202 bits<1> BPFSrc; 203 bits<4> dst; 204 bits<4> src; 205 206 let Inst{63-60} = op; 207 let Inst{59} = BPFSrc; 208 let Inst{55-52} = src; 209 let Inst{51-48} = dst; 210 211 let op = 0xb; // BPF_MOV 212 let BPFSrc = 1; // BPF_X 213 let BPFClass = 7; // BPF_ALU64 214} 215 216class MOV_RI<string OpcodeStr> 217 : InstBPF<(outs GPR:$dst), (ins i64imm:$imm), 218 !strconcat(OpcodeStr, "\t$dst, $imm"), 219 [(set GPR:$dst, (i64 i64immSExt32:$imm))]> { 220 bits<4> op; 221 bits<1> BPFSrc; 222 bits<4> dst; 223 bits<32> imm; 224 225 let Inst{63-60} = op; 226 let Inst{59} = BPFSrc; 227 let Inst{51-48} = dst; 228 let Inst{31-0} = imm; 229 230 let op = 0xb; // BPF_MOV 231 let BPFSrc = 0; // BPF_K 232 let BPFClass = 7; // BPF_ALU64 233} 234 235class LD_IMM64<bits<4> Pseudo, string OpcodeStr> 236 : InstBPF<(outs GPR:$dst), (ins u64imm:$imm), 237 !strconcat(OpcodeStr, "\t$dst, $imm"), 238 [(set GPR:$dst, (i64 imm:$imm))]> { 239 240 bits<3> mode; 241 bits<2> size; 242 bits<4> dst; 243 bits<64> imm; 244 245 let Inst{63-61} = mode; 246 let Inst{60-59} = size; 247 let Inst{51-48} = dst; 248 let Inst{55-52} = Pseudo; 249 let Inst{47-32} = 0; 250 let Inst{31-0} = imm{31-0}; 251 252 let mode = 0; // BPF_IMM 253 let size = 3; // BPF_DW 254 let BPFClass = 0; // BPF_LD 255} 256 257let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 258def LD_imm64 : LD_IMM64<0, "ld_64">; 259def MOV_rr : MOV_RR<"mov">; 260def MOV_ri : MOV_RI<"mov">; 261} 262 263def LD_pseudo 264 : InstBPF<(outs GPR:$dst), (ins i64imm:$pseudo, u64imm:$imm), 265 "ld_pseudo\t$dst, $pseudo, $imm", 266 [(set GPR:$dst, (int_bpf_pseudo imm:$pseudo, imm:$imm))]> { 267 268 bits<3> mode; 269 bits<2> size; 270 bits<4> dst; 271 bits<64> imm; 272 bits<4> pseudo; 273 274 let Inst{63-61} = mode; 275 let Inst{60-59} = size; 276 let Inst{51-48} = dst; 277 let Inst{55-52} = pseudo; 278 let Inst{47-32} = 0; 279 let Inst{31-0} = imm{31-0}; 280 281 let mode = 0; // BPF_IMM 282 let size = 3; // BPF_DW 283 let BPFClass = 0; // BPF_LD 284} 285 286// STORE instructions 287class STORE<bits<2> SizeOp, string OpcodeStr, list<dag> Pattern> 288 : InstBPF<(outs), (ins GPR:$src, MEMri:$addr), 289 !strconcat(OpcodeStr, "\t$addr, $src"), Pattern> { 290 bits<3> mode; 291 bits<2> size; 292 bits<4> src; 293 bits<20> addr; 294 295 let Inst{63-61} = mode; 296 let Inst{60-59} = size; 297 let Inst{51-48} = addr{19-16}; // base reg 298 let Inst{55-52} = src; 299 let Inst{47-32} = addr{15-0}; // offset 300 301 let mode = 3; // BPF_MEM 302 let size = SizeOp; 303 let BPFClass = 3; // BPF_STX 304} 305 306class STOREi64<bits<2> Opc, string OpcodeStr, PatFrag OpNode> 307 : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>; 308 309def STW : STOREi64<0x0, "stw", truncstorei32>; 310def STH : STOREi64<0x1, "sth", truncstorei16>; 311def STB : STOREi64<0x2, "stb", truncstorei8>; 312def STD : STOREi64<0x3, "std", store>; 313 314// LOAD instructions 315class LOAD<bits<2> SizeOp, string OpcodeStr, list<dag> Pattern> 316 : InstBPF<(outs GPR:$dst), (ins MEMri:$addr), 317 !strconcat(OpcodeStr, "\t$dst, $addr"), Pattern> { 318 bits<3> mode; 319 bits<2> size; 320 bits<4> dst; 321 bits<20> addr; 322 323 let Inst{63-61} = mode; 324 let Inst{60-59} = size; 325 let Inst{51-48} = dst; 326 let Inst{55-52} = addr{19-16}; 327 let Inst{47-32} = addr{15-0}; 328 329 let mode = 3; // BPF_MEM 330 let size = SizeOp; 331 let BPFClass = 1; // BPF_LDX 332} 333 334class LOADi64<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode> 335 : LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>; 336 337def LDW : LOADi64<0x0, "ldw", zextloadi32>; 338def LDH : LOADi64<0x1, "ldh", zextloadi16>; 339def LDB : LOADi64<0x2, "ldb", zextloadi8>; 340def LDD : LOADi64<0x3, "ldd", load>; 341 342class BRANCH<bits<4> Opc, string OpcodeStr, list<dag> Pattern> 343 : InstBPF<(outs), (ins brtarget:$BrDst), 344 !strconcat(OpcodeStr, "\t$BrDst"), Pattern> { 345 bits<4> op; 346 bits<16> BrDst; 347 bits<1> BPFSrc; 348 349 let Inst{63-60} = op; 350 let Inst{59} = BPFSrc; 351 let Inst{47-32} = BrDst; 352 353 let op = Opc; 354 let BPFSrc = 0; 355 let BPFClass = 5; // BPF_JMP 356} 357 358class CALL<string OpcodeStr> 359 : InstBPF<(outs), (ins calltarget:$BrDst), 360 !strconcat(OpcodeStr, "\t$BrDst"), []> { 361 bits<4> op; 362 bits<32> BrDst; 363 bits<1> BPFSrc; 364 365 let Inst{63-60} = op; 366 let Inst{59} = BPFSrc; 367 let Inst{31-0} = BrDst; 368 369 let op = 8; // BPF_CALL 370 let BPFSrc = 0; 371 let BPFClass = 5; // BPF_JMP 372} 373 374// Jump always 375let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in { 376 def JMP : BRANCH<0x0, "jmp", [(br bb:$BrDst)]>; 377} 378 379// Jump and link 380let isCall=1, hasDelaySlot=0, Uses = [R11], 381 // Potentially clobbered registers 382 Defs = [R0, R1, R2, R3, R4, R5] in { 383 def JAL : CALL<"call">; 384} 385 386class NOP_I<string OpcodeStr> 387 : InstBPF<(outs), (ins i32imm:$imm), 388 !strconcat(OpcodeStr, "\t$imm"), []> { 389 // mov r0, r0 == nop 390 bits<4> op; 391 bits<1> BPFSrc; 392 bits<4> dst; 393 bits<4> src; 394 395 let Inst{63-60} = op; 396 let Inst{59} = BPFSrc; 397 let Inst{55-52} = src; 398 let Inst{51-48} = dst; 399 400 let op = 0xb; // BPF_MOV 401 let BPFSrc = 1; // BPF_X 402 let BPFClass = 7; // BPF_ALU64 403 let src = 0; // R0 404 let dst = 0; // R0 405} 406 407let hasSideEffects = 0 in 408 def NOP : NOP_I<"nop">; 409 410class RET<string OpcodeStr> 411 : InstBPF<(outs), (ins), 412 !strconcat(OpcodeStr, ""), [(BPFretflag)]> { 413 bits<4> op; 414 415 let Inst{63-60} = op; 416 let Inst{59} = 0; 417 let Inst{31-0} = 0; 418 419 let op = 9; // BPF_EXIT 420 let BPFClass = 5; // BPF_JMP 421} 422 423let isReturn = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1, 424 isNotDuplicable = 1 in { 425 def RET : RET<"ret">; 426} 427 428// ADJCALLSTACKDOWN/UP pseudo insns 429let Defs = [R11], Uses = [R11] in { 430def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt), 431 "#ADJCALLSTACKDOWN $amt", 432 [(BPFcallseq_start timm:$amt)]>; 433def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 434 "#ADJCALLSTACKUP $amt1 $amt2", 435 [(BPFcallseq_end timm:$amt1, timm:$amt2)]>; 436} 437 438let usesCustomInserter = 1 in { 439 def Select : Pseudo<(outs GPR:$dst), 440 (ins GPR:$lhs, GPR:$rhs, i64imm:$imm, GPR:$src, GPR:$src2), 441 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", 442 [(set i64:$dst, 443 (BPFselectcc i64:$lhs, i64:$rhs, (i64 imm:$imm), i64:$src, i64:$src2))]>; 444} 445 446// load 64-bit global addr into register 447def : Pat<(BPFWrapper tglobaladdr:$in), (LD_imm64 tglobaladdr:$in)>; 448 449// 0xffffFFFF doesn't fit into simm32, optimize common case 450def : Pat<(i64 (and (i64 GPR:$src), 0xffffFFFF)), 451 (SRL_ri (SLL_ri (i64 GPR:$src), 32), 32)>; 452 453// Calls 454def : Pat<(BPFcall tglobaladdr:$dst), (JAL tglobaladdr:$dst)>; 455def : Pat<(BPFcall imm:$dst), (JAL imm:$dst)>; 456 457// Loads 458def : Pat<(extloadi8 ADDRri:$src), (i64 (LDB ADDRri:$src))>; 459def : Pat<(extloadi16 ADDRri:$src), (i64 (LDH ADDRri:$src))>; 460def : Pat<(extloadi32 ADDRri:$src), (i64 (LDW ADDRri:$src))>; 461 462// Atomics 463class XADD<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode> 464 : InstBPF<(outs GPR:$dst), (ins MEMri:$addr, GPR:$val), 465 !strconcat(OpcodeStr, "\t$dst, $addr, $val"), 466 [(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> { 467 bits<3> mode; 468 bits<2> size; 469 bits<4> src; 470 bits<20> addr; 471 472 let Inst{63-61} = mode; 473 let Inst{60-59} = size; 474 let Inst{51-48} = addr{19-16}; // base reg 475 let Inst{55-52} = src; 476 let Inst{47-32} = addr{15-0}; // offset 477 478 let mode = 6; // BPF_XADD 479 let size = SizeOp; 480 let BPFClass = 3; // BPF_STX 481} 482 483let Constraints = "$dst = $val" in { 484def XADD32 : XADD<0, "xadd32", atomic_load_add_32>; 485def XADD64 : XADD<3, "xadd64", atomic_load_add_64>; 486// undefined def XADD16 : XADD<1, "xadd16", atomic_load_add_16>; 487// undefined def XADD8 : XADD<2, "xadd8", atomic_load_add_8>; 488} 489 490// bswap16, bswap32, bswap64 491class BSWAP<bits<32> SizeOp, string OpcodeStr, list<dag> Pattern> 492 : InstBPF<(outs GPR:$dst), (ins GPR:$src), 493 !strconcat(OpcodeStr, "\t$dst"), 494 Pattern> { 495 bits<4> op; 496 bits<1> BPFSrc; 497 bits<4> dst; 498 bits<32> imm; 499 500 let Inst{63-60} = op; 501 let Inst{59} = BPFSrc; 502 let Inst{51-48} = dst; 503 let Inst{31-0} = imm; 504 505 let op = 0xd; // BPF_END 506 let BPFSrc = 1; // BPF_TO_BE (TODO: use BPF_TO_LE for big-endian target) 507 let BPFClass = 4; // BPF_ALU 508 let imm = SizeOp; 509} 510 511let Constraints = "$dst = $src" in { 512def BSWAP16 : BSWAP<16, "bswap16", [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>; 513def BSWAP32 : BSWAP<32, "bswap32", [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>; 514def BSWAP64 : BSWAP<64, "bswap64", [(set GPR:$dst, (bswap GPR:$src))]>; 515} 516 517let Defs = [R0, R1, R2, R3, R4, R5], Uses = [R6], hasSideEffects = 1, 518 hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in { 519class LOAD_ABS<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode> 520 : InstBPF<(outs), (ins GPR:$skb, i64imm:$imm), 521 !strconcat(OpcodeStr, "\tr0, $skb.data + $imm"), 522 [(set R0, (OpNode GPR:$skb, i64immSExt32:$imm))]> { 523 bits<3> mode; 524 bits<2> size; 525 bits<32> imm; 526 527 let Inst{63-61} = mode; 528 let Inst{60-59} = size; 529 let Inst{31-0} = imm; 530 531 let mode = 1; // BPF_ABS 532 let size = SizeOp; 533 let BPFClass = 0; // BPF_LD 534} 535 536class LOAD_IND<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode> 537 : InstBPF<(outs), (ins GPR:$skb, GPR:$val), 538 !strconcat(OpcodeStr, "\tr0, $skb.data + $val"), 539 [(set R0, (OpNode GPR:$skb, GPR:$val))]> { 540 bits<3> mode; 541 bits<2> size; 542 bits<4> val; 543 544 let Inst{63-61} = mode; 545 let Inst{60-59} = size; 546 let Inst{55-52} = val; 547 548 let mode = 2; // BPF_IND 549 let size = SizeOp; 550 let BPFClass = 0; // BPF_LD 551} 552} 553 554def LD_ABS_B : LOAD_ABS<2, "ldabs_b", int_bpf_load_byte>; 555def LD_ABS_H : LOAD_ABS<1, "ldabs_h", int_bpf_load_half>; 556def LD_ABS_W : LOAD_ABS<0, "ldabs_w", int_bpf_load_word>; 557 558def LD_IND_B : LOAD_IND<2, "ldind_b", int_bpf_load_byte>; 559def LD_IND_H : LOAD_IND<1, "ldind_h", int_bpf_load_half>; 560def LD_IND_W : LOAD_IND<0, "ldind_w", int_bpf_load_word>; 561