1//==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Hexagon V4 instruction classes in TableGen format.
11//
12//===----------------------------------------------------------------------===//
13
14//----------------------------------------------------------------------------//
15//                         Hexagon Instruction Flags
16//
17//                        *** Must match BaseInfo.h ***
18//----------------------------------------------------------------------------//
19
20def TypeMEMOP    : IType<9>;
21def TypeNV       : IType<10>;
22def TypeDUPLEX   : IType<11>;
23def TypeCOMPOUND : IType<12>;
24def TypeAG_VX    : IType<28>;
25def TypeAG_VM    : IType<29>;
26def TypePREFIX   : IType<30>;
27
28//                      Duplex Instruction Class Declaration
29//===----------------------------------------------------------------------===//
30
31class OpcodeDuplex {
32  field bits<32> Inst = ?; // Default to an invalid insn.
33  bits<4> IClass = 0; // ICLASS
34  bits<13> ISubHi = 0; // Low sub-insn
35  bits<13> ISubLo = 0; // High sub-insn
36
37  let Inst{31-29} = IClass{3-1};
38  let Inst{13}    = IClass{0};
39  let Inst{15-14} = 0;
40  let Inst{28-16} = ISubHi;
41  let Inst{12-0}  = ISubLo;
42}
43
44class InstDuplex<bits<4> iClass, list<dag> pattern = [],
45                 string cstr = "">
46  : Instruction, OpcodeDuplex {
47  let Namespace = "Hexagon";
48  IType Type = TypeDUPLEX;  // uses slot 0,1
49  let isCodeGenOnly = 1;
50  let hasSideEffects = 0;
51  dag OutOperandList = (outs);
52  dag InOperandList = (ins);
53  let IClass = iClass;
54  let Constraints = cstr;
55  let Itinerary = DUPLEX;
56  let Size = 4;
57
58  // SoftFail is a field the disassembler can use to provide a way for
59  // instructions to not match without killing the whole decode process. It is
60  // mainly used for ARM, but Tablegen expects this field to exist or it fails
61  // to build the decode table.
62  field bits<32> SoftFail = 0;
63
64  // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
65
66  let TSFlags{4-0} = Type.Value;
67
68  // Predicated instructions.
69  bits<1> isPredicated = 0;
70  let TSFlags{6} = isPredicated;
71  bits<1> isPredicatedFalse = 0;
72  let TSFlags{7} = isPredicatedFalse;
73  bits<1> isPredicatedNew = 0;
74  let TSFlags{8} = isPredicatedNew;
75
76  // New-value insn helper fields.
77  bits<1> isNewValue = 0;
78  let TSFlags{9} = isNewValue; // New-value consumer insn.
79  bits<1> hasNewValue = 0;
80  let TSFlags{10} = hasNewValue; // New-value producer insn.
81  bits<3> opNewValue = 0;
82  let TSFlags{13-11} = opNewValue; // New-value produced operand.
83  bits<1> isNVStorable = 0;
84  let TSFlags{14} = isNVStorable; // Store that can become new-value store.
85  bits<1> isNVStore = 0;
86  let TSFlags{15} = isNVStore; // New-value store insn.
87
88  // Immediate extender helper fields.
89  bits<1> isExtendable = 0;
90  let TSFlags{16} = isExtendable; // Insn may be extended.
91  bits<1> isExtended = 0;
92  let TSFlags{17} = isExtended; // Insn must be extended.
93  bits<3> opExtendable = 0;
94  let TSFlags{20-18} = opExtendable; // Which operand may be extended.
95  bits<1> isExtentSigned = 0;
96  let TSFlags{21} = isExtentSigned; // Signed or unsigned range.
97  bits<5> opExtentBits = 0;
98  let TSFlags{26-22} = opExtentBits; //Number of bits of range before extending.
99  bits<2> opExtentAlign = 0;
100  let TSFlags{28-27} = opExtentAlign; // Alignment exponent before extending.
101}
102
103//----------------------------------------------------------------------------//
104//                         Instruction Classes Definitions
105//----------------------------------------------------------------------------//
106
107//
108// NV type instructions.
109//
110class NVInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
111             string cstr = "", InstrItinClass itin = NCJ_tc_3or4stall_SLOT0>
112  : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeNV>, OpcodeHexagon;
113
114class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
115                string cstr = "", InstrItinClass itin = NCJ_tc_3or4stall_SLOT0>
116  : NVInst<outs, ins, asmstr, pattern, cstr, itin>;
117
118// Definition of Post increment new value store.
119class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
120               string cstr = "", InstrItinClass itin = ST_tc_st_SLOT0>
121  : NVInst<outs, ins, asmstr, pattern, cstr, itin>;
122
123// Post increment ST Instruction.
124let mayStore = 1 in
125class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
126               string cstr = "", InstrItinClass itin = ST_tc_st_SLOT0>
127  : NVInst<outs, ins, asmstr, pattern, cstr, itin>;
128
129// New-value conditional branch.
130class NCJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
131              string cstr = "">
132  : NVInst<outs, ins, asmstr, pattern, cstr>;
133
134let mayLoad = 1, mayStore = 1 in
135class MEMInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
136              string cstr = "", InstrItinClass itin = V4LDST_tc_st_SLOT0>
137  : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeMEMOP>,
138    OpcodeHexagon;
139
140class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
141                 string cstr = "", InstrItinClass itin = V4LDST_tc_st_SLOT0>
142  : MEMInst<outs, ins, asmstr, pattern, cstr, itin>;
143
144let isCodeGenOnly = 1 in
145class EXTENDERInst<dag outs, dag ins, string asmstr, list<dag> pattern = []>
146  : InstHexagon<outs, ins, asmstr, pattern, "", EXTENDER_tc_1_SLOT0123,
147                TypePREFIX>, OpcodeHexagon;
148
149class CJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
150              string cstr = "">
151  : InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND, TypeCOMPOUND>,
152    OpcodeHexagon;
153