1 //===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 // This peephole pass optimizes in the following cases.
9 // 1. Optimizes redundant sign extends for the following case
10 //    Transform the following pattern
11 //    %vreg170<def> = SXTW %vreg166
12 //    ...
13 //    %vreg176<def> = COPY %vreg170:subreg_loreg
14 //
15 //    Into
16 //    %vreg176<def> = COPY vreg166
17 //
18 //  2. Optimizes redundant negation of predicates.
19 //     %vreg15<def> = CMPGTrr %vreg6, %vreg2
20 //     ...
21 //     %vreg16<def> = NOT_p %vreg15<kill>
22 //     ...
23 //     JMP_c %vreg16<kill>, <BB#1>, %PC<imp-def,dead>
24 //
25 //     Into
26 //     %vreg15<def> = CMPGTrr %vreg6, %vreg2;
27 //     ...
28 //     JMP_cNot %vreg15<kill>, <BB#1>, %PC<imp-def,dead>;
29 //
30 // Note: The peephole pass makes the instrucstions like
31 // %vreg170<def> = SXTW %vreg166 or %vreg16<def> = NOT_p %vreg15<kill>
32 // redundant and relies on some form of dead removal instructions, like
33 // DCE or DIE to actually eliminate them.
34 
35 
36 //===----------------------------------------------------------------------===//
37 
38 #include "Hexagon.h"
39 #include "HexagonTargetMachine.h"
40 #include "llvm/ADT/DenseMap.h"
41 #include "llvm/ADT/Statistic.h"
42 #include "llvm/CodeGen/MachineFunction.h"
43 #include "llvm/CodeGen/MachineFunctionPass.h"
44 #include "llvm/CodeGen/MachineInstrBuilder.h"
45 #include "llvm/CodeGen/MachineRegisterInfo.h"
46 #include "llvm/CodeGen/Passes.h"
47 #include "llvm/IR/Constants.h"
48 #include "llvm/PassSupport.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/Target/TargetInstrInfo.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include "llvm/Target/TargetRegisterInfo.h"
55 #include <algorithm>
56 
57 using namespace llvm;
58 
59 #define DEBUG_TYPE "hexagon-peephole"
60 
61 static cl::opt<bool> DisableHexagonPeephole("disable-hexagon-peephole",
62     cl::Hidden, cl::ZeroOrMore, cl::init(false),
63     cl::desc("Disable Peephole Optimization"));
64 
65 static cl::opt<bool> DisablePNotP("disable-hexagon-pnotp",
66     cl::Hidden, cl::ZeroOrMore, cl::init(false),
67     cl::desc("Disable Optimization of PNotP"));
68 
69 static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext",
70     cl::Hidden, cl::ZeroOrMore, cl::init(false),
71     cl::desc("Disable Optimization of Sign/Zero Extends"));
72 
73 static cl::opt<bool> DisableOptExtTo64("disable-hexagon-opt-ext-to-64",
74     cl::Hidden, cl::ZeroOrMore, cl::init(false),
75     cl::desc("Disable Optimization of extensions to i64."));
76 
77 namespace llvm {
78   void initializeHexagonPeepholePass(PassRegistry&);
79 }
80 
81 namespace {
82   struct HexagonPeephole : public MachineFunctionPass {
83     const HexagonInstrInfo    *QII;
84     const HexagonRegisterInfo *QRI;
85     const MachineRegisterInfo *MRI;
86 
87   public:
88     static char ID;
HexagonPeephole__anonbebec75d0111::HexagonPeephole89     HexagonPeephole() : MachineFunctionPass(ID) {
90       initializeHexagonPeepholePass(*PassRegistry::getPassRegistry());
91     }
92 
93     bool runOnMachineFunction(MachineFunction &MF) override;
94 
getPassName__anonbebec75d0111::HexagonPeephole95     const char *getPassName() const override {
96       return "Hexagon optimize redundant zero and size extends";
97     }
98 
getAnalysisUsage__anonbebec75d0111::HexagonPeephole99     void getAnalysisUsage(AnalysisUsage &AU) const override {
100       MachineFunctionPass::getAnalysisUsage(AU);
101     }
102 
103   private:
104     void ChangeOpInto(MachineOperand &Dst, MachineOperand &Src);
105   };
106 }
107 
108 char HexagonPeephole::ID = 0;
109 
110 INITIALIZE_PASS(HexagonPeephole, "hexagon-peephole", "Hexagon Peephole",
111                 false, false)
112 
runOnMachineFunction(MachineFunction & MF)113 bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
114   QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
115   QRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
116   MRI = &MF.getRegInfo();
117 
118   DenseMap<unsigned, unsigned> PeepholeMap;
119   DenseMap<unsigned, std::pair<unsigned, unsigned> > PeepholeDoubleRegsMap;
120 
121   if (DisableHexagonPeephole) return false;
122 
123   // Loop over all of the basic blocks.
124   for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
125        MBBb != MBBe; ++MBBb) {
126     MachineBasicBlock* MBB = MBBb;
127     PeepholeMap.clear();
128     PeepholeDoubleRegsMap.clear();
129 
130     // Traverse the basic block.
131     for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
132                                      ++MII) {
133       MachineInstr *MI = MII;
134       // Look for sign extends:
135       // %vreg170<def> = SXTW %vreg166
136       if (!DisableOptSZExt && MI->getOpcode() == Hexagon::A2_sxtw) {
137         assert (MI->getNumOperands() == 2);
138         MachineOperand &Dst = MI->getOperand(0);
139         MachineOperand &Src  = MI->getOperand(1);
140         unsigned DstReg = Dst.getReg();
141         unsigned SrcReg = Src.getReg();
142         // Just handle virtual registers.
143         if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
144             TargetRegisterInfo::isVirtualRegister(SrcReg)) {
145           // Map the following:
146           // %vreg170<def> = SXTW %vreg166
147           // PeepholeMap[170] = vreg166
148           PeepholeMap[DstReg] = SrcReg;
149         }
150       }
151 
152       // Look for  %vreg170<def> = COMBINE_ir_V4 (0, %vreg169)
153       // %vreg170:DoublRegs, %vreg169:IntRegs
154       if (!DisableOptExtTo64 &&
155           MI->getOpcode () == Hexagon::A4_combineir) {
156         assert (MI->getNumOperands() == 3);
157         MachineOperand &Dst = MI->getOperand(0);
158         MachineOperand &Src1 = MI->getOperand(1);
159         MachineOperand &Src2 = MI->getOperand(2);
160         if (Src1.getImm() != 0)
161           continue;
162         unsigned DstReg = Dst.getReg();
163         unsigned SrcReg = Src2.getReg();
164         PeepholeMap[DstReg] = SrcReg;
165       }
166 
167       // Look for this sequence below
168       // %vregDoubleReg1 = LSRd_ri %vregDoubleReg0, 32
169       // %vregIntReg = COPY %vregDoubleReg1:subreg_loreg.
170       // and convert into
171       // %vregIntReg = COPY %vregDoubleReg0:subreg_hireg.
172       if (MI->getOpcode() == Hexagon::S2_lsr_i_p) {
173         assert(MI->getNumOperands() == 3);
174         MachineOperand &Dst = MI->getOperand(0);
175         MachineOperand &Src1 = MI->getOperand(1);
176         MachineOperand &Src2 = MI->getOperand(2);
177         if (Src2.getImm() != 32)
178           continue;
179         unsigned DstReg = Dst.getReg();
180         unsigned SrcReg = Src1.getReg();
181         PeepholeDoubleRegsMap[DstReg] =
182           std::make_pair(*&SrcReg, 1/*Hexagon::subreg_hireg*/);
183       }
184 
185       // Look for P=NOT(P).
186       if (!DisablePNotP &&
187           (MI->getOpcode() == Hexagon::C2_not)) {
188         assert (MI->getNumOperands() == 2);
189         MachineOperand &Dst = MI->getOperand(0);
190         MachineOperand &Src  = MI->getOperand(1);
191         unsigned DstReg = Dst.getReg();
192         unsigned SrcReg = Src.getReg();
193         // Just handle virtual registers.
194         if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
195             TargetRegisterInfo::isVirtualRegister(SrcReg)) {
196           // Map the following:
197           // %vreg170<def> = NOT_xx %vreg166
198           // PeepholeMap[170] = vreg166
199           PeepholeMap[DstReg] = SrcReg;
200         }
201       }
202 
203       // Look for copy:
204       // %vreg176<def> = COPY %vreg170:subreg_loreg
205       if (!DisableOptSZExt && MI->isCopy()) {
206         assert (MI->getNumOperands() == 2);
207         MachineOperand &Dst = MI->getOperand(0);
208         MachineOperand &Src  = MI->getOperand(1);
209 
210         // Make sure we are copying the lower 32 bits.
211         if (Src.getSubReg() != Hexagon::subreg_loreg)
212           continue;
213 
214         unsigned DstReg = Dst.getReg();
215         unsigned SrcReg = Src.getReg();
216         if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
217             TargetRegisterInfo::isVirtualRegister(SrcReg)) {
218           // Try to find in the map.
219           if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) {
220             // Change the 1st operand.
221             MI->RemoveOperand(1);
222             MI->addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
223           } else  {
224             DenseMap<unsigned, std::pair<unsigned, unsigned> >::iterator DI =
225               PeepholeDoubleRegsMap.find(SrcReg);
226             if (DI != PeepholeDoubleRegsMap.end()) {
227               std::pair<unsigned,unsigned> PeepholeSrc = DI->second;
228               MI->RemoveOperand(1);
229               MI->addOperand(MachineOperand::CreateReg(PeepholeSrc.first,
230                                                        false /*isDef*/,
231                                                        false /*isImp*/,
232                                                        false /*isKill*/,
233                                                        false /*isDead*/,
234                                                        false /*isUndef*/,
235                                                        false /*isEarlyClobber*/,
236                                                        PeepholeSrc.second));
237             }
238           }
239         }
240       }
241 
242       // Look for Predicated instructions.
243       if (!DisablePNotP) {
244         bool Done = false;
245         if (QII->isPredicated(MI)) {
246           MachineOperand &Op0 = MI->getOperand(0);
247           unsigned Reg0 = Op0.getReg();
248           const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
249           if (RC0->getID() == Hexagon::PredRegsRegClassID) {
250             // Handle instructions that have a prediate register in op0
251             // (most cases of predicable instructions).
252             if (TargetRegisterInfo::isVirtualRegister(Reg0)) {
253               // Try to find in the map.
254               if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
255                 // Change the 1st operand and, flip the opcode.
256                 MI->getOperand(0).setReg(PeepholeSrc);
257                 int NewOp = QII->getInvertedPredicatedOpcode(MI->getOpcode());
258                 MI->setDesc(QII->get(NewOp));
259                 Done = true;
260               }
261             }
262           }
263         }
264 
265         if (!Done) {
266           // Handle special instructions.
267           unsigned Op = MI->getOpcode();
268           unsigned NewOp = 0;
269           unsigned PR = 1, S1 = 2, S2 = 3;   // Operand indices.
270 
271           switch (Op) {
272             case Hexagon::C2_mux:
273             case Hexagon::C2_muxii:
274               NewOp = Op;
275               break;
276             case Hexagon::C2_muxri:
277               NewOp = Hexagon::C2_muxir;
278               break;
279             case Hexagon::C2_muxir:
280               NewOp = Hexagon::C2_muxri;
281               break;
282           }
283           if (NewOp) {
284             unsigned PSrc = MI->getOperand(PR).getReg();
285             if (unsigned POrig = PeepholeMap.lookup(PSrc)) {
286               MI->getOperand(PR).setReg(POrig);
287               MI->setDesc(QII->get(NewOp));
288               // Swap operands S1 and S2.
289               MachineOperand Op1 = MI->getOperand(S1);
290               MachineOperand Op2 = MI->getOperand(S2);
291               ChangeOpInto(MI->getOperand(S1), Op2);
292               ChangeOpInto(MI->getOperand(S2), Op1);
293             }
294           } // if (NewOp)
295         } // if (!Done)
296 
297       } // if (!DisablePNotP)
298 
299     } // Instruction
300   } // Basic Block
301   return true;
302 }
303 
ChangeOpInto(MachineOperand & Dst,MachineOperand & Src)304 void HexagonPeephole::ChangeOpInto(MachineOperand &Dst, MachineOperand &Src) {
305   assert (&Dst != &Src && "Cannot duplicate into itself");
306   switch (Dst.getType()) {
307     case MachineOperand::MO_Register:
308       if (Src.isReg()) {
309         Dst.setReg(Src.getReg());
310       } else if (Src.isImm()) {
311         Dst.ChangeToImmediate(Src.getImm());
312       } else {
313         llvm_unreachable("Unexpected src operand type");
314       }
315       break;
316 
317     case MachineOperand::MO_Immediate:
318       if (Src.isImm()) {
319         Dst.setImm(Src.getImm());
320       } else if (Src.isReg()) {
321         Dst.ChangeToRegister(Src.getReg(), Src.isDef(), Src.isImplicit(),
322                              Src.isKill(), Src.isDead(), Src.isUndef(),
323                              Src.isDebug());
324       } else {
325         llvm_unreachable("Unexpected src operand type");
326       }
327       break;
328 
329     default:
330       llvm_unreachable("Unexpected dst operand type");
331       break;
332   }
333 }
334 
createHexagonPeephole()335 FunctionPass *llvm::createHexagonPeephole() {
336   return new HexagonPeephole();
337 }
338