1 //===-- HexagonSubtarget.cpp - Hexagon Subtarget Information --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the Hexagon specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "HexagonSubtarget.h"
15 #include "Hexagon.h"
16 #include "HexagonRegisterInfo.h"
17 #include "llvm/Support/CommandLine.h"
18 #include "llvm/Support/ErrorHandling.h"
19 using namespace llvm;
20
21 #define DEBUG_TYPE "hexagon-subtarget"
22
23 #define GET_SUBTARGETINFO_CTOR
24 #define GET_SUBTARGETINFO_TARGET_DESC
25 #include "HexagonGenSubtargetInfo.inc"
26
27 static cl::opt<bool>
28 EnableV3("enable-hexagon-v3", cl::Hidden,
29 cl::desc("Enable Hexagon V3 instructions."));
30
31 static cl::opt<bool>
32 EnableMemOps(
33 "enable-hexagon-memops",
34 cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(true),
35 cl::desc(
36 "Generate V4 MEMOP in code generation for Hexagon target"));
37
38 static cl::opt<bool>
39 DisableMemOps(
40 "disable-hexagon-memops",
41 cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(false),
42 cl::desc(
43 "Do not generate V4 MEMOP in code generation for Hexagon target"));
44
45 static cl::opt<bool>
46 EnableIEEERndNear(
47 "enable-hexagon-ieee-rnd-near",
48 cl::Hidden, cl::ZeroOrMore, cl::init(false),
49 cl::desc("Generate non-chopped conversion from fp to int."));
50
51 static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
52 cl::Hidden, cl::ZeroOrMore, cl::init(false),
53 cl::desc("Disable Hexagon MI Scheduling"));
54
55 HexagonSubtarget &
initializeSubtargetDependencies(StringRef CPU,StringRef FS)56 HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
57 // If the programmer has not specified a Hexagon version, default to -mv4.
58 if (CPUString.empty())
59 CPUString = "hexagonv4";
60
61 if (CPUString == "hexagonv4") {
62 HexagonArchVersion = V4;
63 } else if (CPUString == "hexagonv5") {
64 HexagonArchVersion = V5;
65 } else {
66 llvm_unreachable("Unrecognized Hexagon processor version");
67 }
68
69 ParseSubtargetFeatures(CPUString, FS);
70 return *this;
71 }
72
HexagonSubtarget(StringRef TT,StringRef CPU,StringRef FS,const TargetMachine & TM)73 HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS,
74 const TargetMachine &TM)
75 : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU),
76 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
77 TSInfo(*TM.getDataLayout()), FrameLowering() {
78
79 // Initialize scheduling itinerary for the specified CPU.
80 InstrItins = getInstrItineraryForCPU(CPUString);
81
82 // UseMemOps on by default unless disabled explicitly
83 if (DisableMemOps)
84 UseMemOps = false;
85 else if (EnableMemOps)
86 UseMemOps = true;
87 else
88 UseMemOps = false;
89
90 if (EnableIEEERndNear)
91 ModeIEEERndNear = true;
92 else
93 ModeIEEERndNear = false;
94 }
95
96 // Pin the vtable to this file.
anchor()97 void HexagonSubtarget::anchor() {}
98
enableMachineScheduler() const99 bool HexagonSubtarget::enableMachineScheduler() const {
100 if (DisableHexagonMISched.getNumOccurrences())
101 return !DisableHexagonMISched;
102 return true;
103 }
104