1 //===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides Mips specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
15 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
16 
17 #include "llvm/Support/DataTypes.h"
18 
19 namespace llvm {
20 class MCAsmBackend;
21 class MCCodeEmitter;
22 class MCContext;
23 class MCInstrInfo;
24 class MCObjectWriter;
25 class MCRegisterInfo;
26 class MCSubtargetInfo;
27 class StringRef;
28 class Target;
29 class raw_ostream;
30 class raw_pwrite_stream;
31 
32 extern Target TheMipsTarget;
33 extern Target TheMipselTarget;
34 extern Target TheMips64Target;
35 extern Target TheMips64elTarget;
36 
37 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
38                                          const MCRegisterInfo &MRI,
39                                          MCContext &Ctx);
40 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
41                                          const MCRegisterInfo &MRI,
42                                          MCContext &Ctx);
43 
44 MCAsmBackend *createMipsAsmBackendEB32(const Target &T,
45                                        const MCRegisterInfo &MRI, StringRef TT,
46                                        StringRef CPU);
47 MCAsmBackend *createMipsAsmBackendEL32(const Target &T,
48                                        const MCRegisterInfo &MRI, StringRef TT,
49                                        StringRef CPU);
50 MCAsmBackend *createMipsAsmBackendEB64(const Target &T,
51                                        const MCRegisterInfo &MRI, StringRef TT,
52                                        StringRef CPU);
53 MCAsmBackend *createMipsAsmBackendEL64(const Target &T,
54                                        const MCRegisterInfo &MRI, StringRef TT,
55                                        StringRef CPU);
56 
57 MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
58                                           bool IsLittleEndian, bool Is64Bit);
59 
60 namespace MIPS_MC {
61 StringRef selectMipsCPU(StringRef TT, StringRef CPU);
62 }
63 
64 } // End llvm namespace
65 
66 // Defines symbolic names for Mips registers.  This defines a mapping from
67 // register name to register number.
68 #define GET_REGINFO_ENUM
69 #include "MipsGenRegisterInfo.inc"
70 
71 // Defines symbolic names for the Mips instructions.
72 #define GET_INSTRINFO_ENUM
73 #include "MipsGenInstrInfo.inc"
74 
75 #define GET_SUBTARGETINFO_ENUM
76 #include "MipsGenSubtargetInfo.inc"
77 
78 #endif
79