1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the MSP430TargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "MSP430ISelLowering.h"
15 #include "MSP430.h"
16 #include "MSP430MachineFunctionInfo.h"
17 #include "MSP430Subtarget.h"
18 #include "MSP430TargetMachine.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
26 #include "llvm/CodeGen/ValueTypes.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/GlobalAlias.h"
31 #include "llvm/IR/GlobalVariable.h"
32 #include "llvm/IR/Intrinsics.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
37 using namespace llvm;
38
39 #define DEBUG_TYPE "msp430-lower"
40
41 typedef enum {
42 NoHWMult,
43 HWMultIntr,
44 HWMultNoIntr
45 } HWMultUseMode;
46
47 static cl::opt<HWMultUseMode>
48 HWMultMode("msp430-hwmult-mode", cl::Hidden,
49 cl::desc("Hardware multiplier use mode"),
50 cl::init(HWMultNoIntr),
51 cl::values(
52 clEnumValN(NoHWMult, "no",
53 "Do not use hardware multiplier"),
54 clEnumValN(HWMultIntr, "interrupts",
55 "Assume hardware multiplier can be used inside interrupts"),
56 clEnumValN(HWMultNoIntr, "use",
57 "Assume hardware multiplier cannot be used inside interrupts"),
58 clEnumValEnd));
59
MSP430TargetLowering(const TargetMachine & TM,const MSP430Subtarget & STI)60 MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
61 const MSP430Subtarget &STI)
62 : TargetLowering(TM) {
63
64 // Set up the register classes.
65 addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
66 addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
67
68 // Compute derived properties from the register classes
69 computeRegisterProperties(STI.getRegisterInfo());
70
71 // Provide all sorts of operation actions
72
73 // Division is expensive
74 setIntDivIsCheap(false);
75
76 setStackPointerRegisterToSaveRestore(MSP430::SP);
77 setBooleanContents(ZeroOrOneBooleanContent);
78 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
79
80 // We have post-incremented loads / stores.
81 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
82 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
83
84 for (MVT VT : MVT::integer_valuetypes()) {
85 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
86 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
87 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
88 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
89 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand);
90 }
91
92 // We don't have any truncstores
93 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
94
95 setOperationAction(ISD::SRA, MVT::i8, Custom);
96 setOperationAction(ISD::SHL, MVT::i8, Custom);
97 setOperationAction(ISD::SRL, MVT::i8, Custom);
98 setOperationAction(ISD::SRA, MVT::i16, Custom);
99 setOperationAction(ISD::SHL, MVT::i16, Custom);
100 setOperationAction(ISD::SRL, MVT::i16, Custom);
101 setOperationAction(ISD::ROTL, MVT::i8, Expand);
102 setOperationAction(ISD::ROTR, MVT::i8, Expand);
103 setOperationAction(ISD::ROTL, MVT::i16, Expand);
104 setOperationAction(ISD::ROTR, MVT::i16, Expand);
105 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
106 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
107 setOperationAction(ISD::BlockAddress, MVT::i16, Custom);
108 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
109 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
110 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
111 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
112 setOperationAction(ISD::SETCC, MVT::i8, Custom);
113 setOperationAction(ISD::SETCC, MVT::i16, Custom);
114 setOperationAction(ISD::SELECT, MVT::i8, Expand);
115 setOperationAction(ISD::SELECT, MVT::i16, Expand);
116 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
117 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
118 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
119 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
120 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
121
122 setOperationAction(ISD::CTTZ, MVT::i8, Expand);
123 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
124 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i8, Expand);
125 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand);
126 setOperationAction(ISD::CTLZ, MVT::i8, Expand);
127 setOperationAction(ISD::CTLZ, MVT::i16, Expand);
128 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8, Expand);
129 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Expand);
130 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
131 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
132
133 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
134 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
135 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
136 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
137 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
138 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
139
140 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
141
142 // FIXME: Implement efficiently multiplication by a constant
143 setOperationAction(ISD::MUL, MVT::i8, Expand);
144 setOperationAction(ISD::MULHS, MVT::i8, Expand);
145 setOperationAction(ISD::MULHU, MVT::i8, Expand);
146 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
147 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
148 setOperationAction(ISD::MUL, MVT::i16, Expand);
149 setOperationAction(ISD::MULHS, MVT::i16, Expand);
150 setOperationAction(ISD::MULHU, MVT::i16, Expand);
151 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
152 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
153
154 setOperationAction(ISD::UDIV, MVT::i8, Expand);
155 setOperationAction(ISD::UDIVREM, MVT::i8, Expand);
156 setOperationAction(ISD::UREM, MVT::i8, Expand);
157 setOperationAction(ISD::SDIV, MVT::i8, Expand);
158 setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
159 setOperationAction(ISD::SREM, MVT::i8, Expand);
160 setOperationAction(ISD::UDIV, MVT::i16, Expand);
161 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
162 setOperationAction(ISD::UREM, MVT::i16, Expand);
163 setOperationAction(ISD::SDIV, MVT::i16, Expand);
164 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
165 setOperationAction(ISD::SREM, MVT::i16, Expand);
166
167 // varargs support
168 setOperationAction(ISD::VASTART, MVT::Other, Custom);
169 setOperationAction(ISD::VAARG, MVT::Other, Expand);
170 setOperationAction(ISD::VAEND, MVT::Other, Expand);
171 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
172 setOperationAction(ISD::JumpTable, MVT::i16, Custom);
173
174 // Libcalls names.
175 if (HWMultMode == HWMultIntr) {
176 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw");
177 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
178 } else if (HWMultMode == HWMultNoIntr) {
179 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw_noint");
180 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
181 }
182
183 setMinFunctionAlignment(1);
184 setPrefFunctionAlignment(2);
185 }
186
LowerOperation(SDValue Op,SelectionDAG & DAG) const187 SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
188 SelectionDAG &DAG) const {
189 switch (Op.getOpcode()) {
190 case ISD::SHL: // FALLTHROUGH
191 case ISD::SRL:
192 case ISD::SRA: return LowerShifts(Op, DAG);
193 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
194 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
195 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
196 case ISD::SETCC: return LowerSETCC(Op, DAG);
197 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
198 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
199 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
200 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
201 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
202 case ISD::VASTART: return LowerVASTART(Op, DAG);
203 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
204 default:
205 llvm_unreachable("unimplemented operand");
206 }
207 }
208
209 //===----------------------------------------------------------------------===//
210 // MSP430 Inline Assembly Support
211 //===----------------------------------------------------------------------===//
212
213 /// getConstraintType - Given a constraint letter, return the type of
214 /// constraint it is for this target.
215 TargetLowering::ConstraintType
getConstraintType(const std::string & Constraint) const216 MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
217 if (Constraint.size() == 1) {
218 switch (Constraint[0]) {
219 case 'r':
220 return C_RegisterClass;
221 default:
222 break;
223 }
224 }
225 return TargetLowering::getConstraintType(Constraint);
226 }
227
228 std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo * TRI,const std::string & Constraint,MVT VT) const229 MSP430TargetLowering::getRegForInlineAsmConstraint(
230 const TargetRegisterInfo *TRI, const std::string &Constraint,
231 MVT VT) const {
232 if (Constraint.size() == 1) {
233 // GCC Constraint Letters
234 switch (Constraint[0]) {
235 default: break;
236 case 'r': // GENERAL_REGS
237 if (VT == MVT::i8)
238 return std::make_pair(0U, &MSP430::GR8RegClass);
239
240 return std::make_pair(0U, &MSP430::GR16RegClass);
241 }
242 }
243
244 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
245 }
246
247 //===----------------------------------------------------------------------===//
248 // Calling Convention Implementation
249 //===----------------------------------------------------------------------===//
250
251 #include "MSP430GenCallingConv.inc"
252
253 /// For each argument in a function store the number of pieces it is composed
254 /// of.
255 template<typename ArgT>
ParseFunctionArgs(const SmallVectorImpl<ArgT> & Args,SmallVectorImpl<unsigned> & Out)256 static void ParseFunctionArgs(const SmallVectorImpl<ArgT> &Args,
257 SmallVectorImpl<unsigned> &Out) {
258 unsigned CurrentArgIndex = ~0U;
259 for (unsigned i = 0, e = Args.size(); i != e; i++) {
260 if (CurrentArgIndex == Args[i].OrigArgIndex) {
261 Out.back()++;
262 } else {
263 Out.push_back(1);
264 CurrentArgIndex++;
265 }
266 }
267 }
268
AnalyzeVarArgs(CCState & State,const SmallVectorImpl<ISD::OutputArg> & Outs)269 static void AnalyzeVarArgs(CCState &State,
270 const SmallVectorImpl<ISD::OutputArg> &Outs) {
271 State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
272 }
273
AnalyzeVarArgs(CCState & State,const SmallVectorImpl<ISD::InputArg> & Ins)274 static void AnalyzeVarArgs(CCState &State,
275 const SmallVectorImpl<ISD::InputArg> &Ins) {
276 State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
277 }
278
279 /// Analyze incoming and outgoing function arguments. We need custom C++ code
280 /// to handle special constraints in the ABI like reversing the order of the
281 /// pieces of splitted arguments. In addition, all pieces of a certain argument
282 /// have to be passed either using registers or the stack but never mixing both.
283 template<typename ArgT>
AnalyzeArguments(CCState & State,SmallVectorImpl<CCValAssign> & ArgLocs,const SmallVectorImpl<ArgT> & Args)284 static void AnalyzeArguments(CCState &State,
285 SmallVectorImpl<CCValAssign> &ArgLocs,
286 const SmallVectorImpl<ArgT> &Args) {
287 static const MCPhysReg RegList[] = {
288 MSP430::R15, MSP430::R14, MSP430::R13, MSP430::R12
289 };
290 static const unsigned NbRegs = array_lengthof(RegList);
291
292 if (State.isVarArg()) {
293 AnalyzeVarArgs(State, Args);
294 return;
295 }
296
297 SmallVector<unsigned, 4> ArgsParts;
298 ParseFunctionArgs(Args, ArgsParts);
299
300 unsigned RegsLeft = NbRegs;
301 bool UseStack = false;
302 unsigned ValNo = 0;
303
304 for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) {
305 MVT ArgVT = Args[ValNo].VT;
306 ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
307 MVT LocVT = ArgVT;
308 CCValAssign::LocInfo LocInfo = CCValAssign::Full;
309
310 // Promote i8 to i16
311 if (LocVT == MVT::i8) {
312 LocVT = MVT::i16;
313 if (ArgFlags.isSExt())
314 LocInfo = CCValAssign::SExt;
315 else if (ArgFlags.isZExt())
316 LocInfo = CCValAssign::ZExt;
317 else
318 LocInfo = CCValAssign::AExt;
319 }
320
321 // Handle byval arguments
322 if (ArgFlags.isByVal()) {
323 State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags);
324 continue;
325 }
326
327 unsigned Parts = ArgsParts[i];
328
329 if (!UseStack && Parts <= RegsLeft) {
330 unsigned FirstVal = ValNo;
331 for (unsigned j = 0; j < Parts; j++) {
332 unsigned Reg = State.AllocateReg(RegList);
333 State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
334 RegsLeft--;
335 }
336
337 // Reverse the order of the pieces to agree with the "big endian" format
338 // required in the calling convention ABI.
339 SmallVectorImpl<CCValAssign>::iterator B = ArgLocs.begin() + FirstVal;
340 std::reverse(B, B + Parts);
341 } else {
342 UseStack = true;
343 for (unsigned j = 0; j < Parts; j++)
344 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
345 }
346 }
347 }
348
AnalyzeRetResult(CCState & State,const SmallVectorImpl<ISD::InputArg> & Ins)349 static void AnalyzeRetResult(CCState &State,
350 const SmallVectorImpl<ISD::InputArg> &Ins) {
351 State.AnalyzeCallResult(Ins, RetCC_MSP430);
352 }
353
AnalyzeRetResult(CCState & State,const SmallVectorImpl<ISD::OutputArg> & Outs)354 static void AnalyzeRetResult(CCState &State,
355 const SmallVectorImpl<ISD::OutputArg> &Outs) {
356 State.AnalyzeReturn(Outs, RetCC_MSP430);
357 }
358
359 template<typename ArgT>
AnalyzeReturnValues(CCState & State,SmallVectorImpl<CCValAssign> & RVLocs,const SmallVectorImpl<ArgT> & Args)360 static void AnalyzeReturnValues(CCState &State,
361 SmallVectorImpl<CCValAssign> &RVLocs,
362 const SmallVectorImpl<ArgT> &Args) {
363 AnalyzeRetResult(State, Args);
364
365 // Reverse splitted return values to get the "big endian" format required
366 // to agree with the calling convention ABI.
367 std::reverse(RVLocs.begin(), RVLocs.end());
368 }
369
370 SDValue
LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,SDLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const371 MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
372 CallingConv::ID CallConv,
373 bool isVarArg,
374 const SmallVectorImpl<ISD::InputArg>
375 &Ins,
376 SDLoc dl,
377 SelectionDAG &DAG,
378 SmallVectorImpl<SDValue> &InVals)
379 const {
380
381 switch (CallConv) {
382 default:
383 llvm_unreachable("Unsupported calling convention");
384 case CallingConv::C:
385 case CallingConv::Fast:
386 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
387 case CallingConv::MSP430_INTR:
388 if (Ins.empty())
389 return Chain;
390 report_fatal_error("ISRs cannot have arguments");
391 }
392 }
393
394 SDValue
LowerCall(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const395 MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
396 SmallVectorImpl<SDValue> &InVals) const {
397 SelectionDAG &DAG = CLI.DAG;
398 SDLoc &dl = CLI.DL;
399 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
400 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
401 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
402 SDValue Chain = CLI.Chain;
403 SDValue Callee = CLI.Callee;
404 bool &isTailCall = CLI.IsTailCall;
405 CallingConv::ID CallConv = CLI.CallConv;
406 bool isVarArg = CLI.IsVarArg;
407
408 // MSP430 target does not yet support tail call optimization.
409 isTailCall = false;
410
411 switch (CallConv) {
412 default:
413 llvm_unreachable("Unsupported calling convention");
414 case CallingConv::Fast:
415 case CallingConv::C:
416 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
417 Outs, OutVals, Ins, dl, DAG, InVals);
418 case CallingConv::MSP430_INTR:
419 report_fatal_error("ISRs cannot be called directly");
420 }
421 }
422
423 /// LowerCCCArguments - transform physical registers into virtual registers and
424 /// generate load operations for arguments places on the stack.
425 // FIXME: struct return stuff
426 SDValue
LowerCCCArguments(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,SDLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const427 MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
428 CallingConv::ID CallConv,
429 bool isVarArg,
430 const SmallVectorImpl<ISD::InputArg>
431 &Ins,
432 SDLoc dl,
433 SelectionDAG &DAG,
434 SmallVectorImpl<SDValue> &InVals)
435 const {
436 MachineFunction &MF = DAG.getMachineFunction();
437 MachineFrameInfo *MFI = MF.getFrameInfo();
438 MachineRegisterInfo &RegInfo = MF.getRegInfo();
439 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
440
441 // Assign locations to all of the incoming arguments.
442 SmallVector<CCValAssign, 16> ArgLocs;
443 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
444 *DAG.getContext());
445 AnalyzeArguments(CCInfo, ArgLocs, Ins);
446
447 // Create frame index for the start of the first vararg value
448 if (isVarArg) {
449 unsigned Offset = CCInfo.getNextStackOffset();
450 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, Offset, true));
451 }
452
453 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
454 CCValAssign &VA = ArgLocs[i];
455 if (VA.isRegLoc()) {
456 // Arguments passed in registers
457 EVT RegVT = VA.getLocVT();
458 switch (RegVT.getSimpleVT().SimpleTy) {
459 default:
460 {
461 #ifndef NDEBUG
462 errs() << "LowerFormalArguments Unhandled argument type: "
463 << RegVT.getSimpleVT().SimpleTy << "\n";
464 #endif
465 llvm_unreachable(nullptr);
466 }
467 case MVT::i16:
468 unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
469 RegInfo.addLiveIn(VA.getLocReg(), VReg);
470 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
471
472 // If this is an 8-bit value, it is really passed promoted to 16
473 // bits. Insert an assert[sz]ext to capture this, then truncate to the
474 // right size.
475 if (VA.getLocInfo() == CCValAssign::SExt)
476 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
477 DAG.getValueType(VA.getValVT()));
478 else if (VA.getLocInfo() == CCValAssign::ZExt)
479 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
480 DAG.getValueType(VA.getValVT()));
481
482 if (VA.getLocInfo() != CCValAssign::Full)
483 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
484
485 InVals.push_back(ArgValue);
486 }
487 } else {
488 // Sanity check
489 assert(VA.isMemLoc());
490
491 SDValue InVal;
492 ISD::ArgFlagsTy Flags = Ins[i].Flags;
493
494 if (Flags.isByVal()) {
495 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
496 VA.getLocMemOffset(), true);
497 InVal = DAG.getFrameIndex(FI, getPointerTy());
498 } else {
499 // Load the argument to a virtual register
500 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
501 if (ObjSize > 2) {
502 errs() << "LowerFormalArguments Unhandled argument type: "
503 << EVT(VA.getLocVT()).getEVTString()
504 << "\n";
505 }
506 // Create the frame index object for this incoming parameter...
507 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
508
509 // Create the SelectionDAG nodes corresponding to a load
510 //from this parameter
511 SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
512 InVal = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
513 MachinePointerInfo::getFixedStack(FI),
514 false, false, false, 0);
515 }
516
517 InVals.push_back(InVal);
518 }
519 }
520
521 return Chain;
522 }
523
524 SDValue
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,SDLoc dl,SelectionDAG & DAG) const525 MSP430TargetLowering::LowerReturn(SDValue Chain,
526 CallingConv::ID CallConv, bool isVarArg,
527 const SmallVectorImpl<ISD::OutputArg> &Outs,
528 const SmallVectorImpl<SDValue> &OutVals,
529 SDLoc dl, SelectionDAG &DAG) const {
530
531 // CCValAssign - represent the assignment of the return value to a location
532 SmallVector<CCValAssign, 16> RVLocs;
533
534 // ISRs cannot return any value.
535 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
536 report_fatal_error("ISRs cannot return any value");
537
538 // CCState - Info about the registers and stack slot.
539 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
540 *DAG.getContext());
541
542 // Analize return values.
543 AnalyzeReturnValues(CCInfo, RVLocs, Outs);
544
545 SDValue Flag;
546 SmallVector<SDValue, 4> RetOps(1, Chain);
547
548 // Copy the result values into the output registers.
549 for (unsigned i = 0; i != RVLocs.size(); ++i) {
550 CCValAssign &VA = RVLocs[i];
551 assert(VA.isRegLoc() && "Can only return in registers!");
552
553 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
554 OutVals[i], Flag);
555
556 // Guarantee that all emitted copies are stuck together,
557 // avoiding something bad.
558 Flag = Chain.getValue(1);
559 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
560 }
561
562 unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
563 MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
564
565 RetOps[0] = Chain; // Update chain.
566
567 // Add the flag if we have it.
568 if (Flag.getNode())
569 RetOps.push_back(Flag);
570
571 return DAG.getNode(Opc, dl, MVT::Other, RetOps);
572 }
573
574 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
575 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
576 // TODO: sret.
577 SDValue
LowerCCCCallTo(SDValue Chain,SDValue Callee,CallingConv::ID CallConv,bool isVarArg,bool isTailCall,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SmallVectorImpl<ISD::InputArg> & Ins,SDLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const578 MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
579 CallingConv::ID CallConv, bool isVarArg,
580 bool isTailCall,
581 const SmallVectorImpl<ISD::OutputArg>
582 &Outs,
583 const SmallVectorImpl<SDValue> &OutVals,
584 const SmallVectorImpl<ISD::InputArg> &Ins,
585 SDLoc dl, SelectionDAG &DAG,
586 SmallVectorImpl<SDValue> &InVals) const {
587 // Analyze operands of the call, assigning locations to each operand.
588 SmallVector<CCValAssign, 16> ArgLocs;
589 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
590 *DAG.getContext());
591 AnalyzeArguments(CCInfo, ArgLocs, Outs);
592
593 // Get a count of how many bytes are to be pushed on the stack.
594 unsigned NumBytes = CCInfo.getNextStackOffset();
595
596 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
597 getPointerTy(), true),
598 dl);
599
600 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
601 SmallVector<SDValue, 12> MemOpChains;
602 SDValue StackPtr;
603
604 // Walk the register/memloc assignments, inserting copies/loads.
605 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
606 CCValAssign &VA = ArgLocs[i];
607
608 SDValue Arg = OutVals[i];
609
610 // Promote the value if needed.
611 switch (VA.getLocInfo()) {
612 default: llvm_unreachable("Unknown loc info!");
613 case CCValAssign::Full: break;
614 case CCValAssign::SExt:
615 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
616 break;
617 case CCValAssign::ZExt:
618 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
619 break;
620 case CCValAssign::AExt:
621 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
622 break;
623 }
624
625 // Arguments that can be passed on register must be kept at RegsToPass
626 // vector
627 if (VA.isRegLoc()) {
628 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
629 } else {
630 assert(VA.isMemLoc());
631
632 if (!StackPtr.getNode())
633 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, getPointerTy());
634
635 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
636 StackPtr,
637 DAG.getIntPtrConstant(VA.getLocMemOffset()));
638
639 SDValue MemOp;
640 ISD::ArgFlagsTy Flags = Outs[i].Flags;
641
642 if (Flags.isByVal()) {
643 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i16);
644 MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
645 Flags.getByValAlign(),
646 /*isVolatile*/false,
647 /*AlwaysInline=*/true,
648 /*isTailCall=*/false,
649 MachinePointerInfo(),
650 MachinePointerInfo());
651 } else {
652 MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(),
653 false, false, 0);
654 }
655
656 MemOpChains.push_back(MemOp);
657 }
658 }
659
660 // Transform all store nodes into one single node because all store nodes are
661 // independent of each other.
662 if (!MemOpChains.empty())
663 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
664
665 // Build a sequence of copy-to-reg nodes chained together with token chain and
666 // flag operands which copy the outgoing args into registers. The InFlag in
667 // necessary since all emitted instructions must be stuck together.
668 SDValue InFlag;
669 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
670 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
671 RegsToPass[i].second, InFlag);
672 InFlag = Chain.getValue(1);
673 }
674
675 // If the callee is a GlobalAddress node (quite common, every direct call is)
676 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
677 // Likewise ExternalSymbol -> TargetExternalSymbol.
678 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
679 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
680 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
681 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
682
683 // Returns a chain & a flag for retval copy to use.
684 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
685 SmallVector<SDValue, 8> Ops;
686 Ops.push_back(Chain);
687 Ops.push_back(Callee);
688
689 // Add argument registers to the end of the list so that they are
690 // known live into the call.
691 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
692 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
693 RegsToPass[i].second.getValueType()));
694
695 if (InFlag.getNode())
696 Ops.push_back(InFlag);
697
698 Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops);
699 InFlag = Chain.getValue(1);
700
701 // Create the CALLSEQ_END node.
702 Chain = DAG.getCALLSEQ_END(Chain,
703 DAG.getConstant(NumBytes, getPointerTy(), true),
704 DAG.getConstant(0, getPointerTy(), true),
705 InFlag, dl);
706 InFlag = Chain.getValue(1);
707
708 // Handle result values, copying them out of physregs into vregs that we
709 // return.
710 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
711 DAG, InVals);
712 }
713
714 /// LowerCallResult - Lower the result values of a call into the
715 /// appropriate copies out of appropriate physical registers.
716 ///
717 SDValue
LowerCallResult(SDValue Chain,SDValue InFlag,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,SDLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const718 MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
719 CallingConv::ID CallConv, bool isVarArg,
720 const SmallVectorImpl<ISD::InputArg> &Ins,
721 SDLoc dl, SelectionDAG &DAG,
722 SmallVectorImpl<SDValue> &InVals) const {
723
724 // Assign locations to each value returned by this call.
725 SmallVector<CCValAssign, 16> RVLocs;
726 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
727 *DAG.getContext());
728
729 AnalyzeReturnValues(CCInfo, RVLocs, Ins);
730
731 // Copy all of the result registers out of their specified physreg.
732 for (unsigned i = 0; i != RVLocs.size(); ++i) {
733 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
734 RVLocs[i].getValVT(), InFlag).getValue(1);
735 InFlag = Chain.getValue(2);
736 InVals.push_back(Chain.getValue(0));
737 }
738
739 return Chain;
740 }
741
LowerShifts(SDValue Op,SelectionDAG & DAG) const742 SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
743 SelectionDAG &DAG) const {
744 unsigned Opc = Op.getOpcode();
745 SDNode* N = Op.getNode();
746 EVT VT = Op.getValueType();
747 SDLoc dl(N);
748
749 // Expand non-constant shifts to loops:
750 if (!isa<ConstantSDNode>(N->getOperand(1)))
751 switch (Opc) {
752 default: llvm_unreachable("Invalid shift opcode!");
753 case ISD::SHL:
754 return DAG.getNode(MSP430ISD::SHL, dl,
755 VT, N->getOperand(0), N->getOperand(1));
756 case ISD::SRA:
757 return DAG.getNode(MSP430ISD::SRA, dl,
758 VT, N->getOperand(0), N->getOperand(1));
759 case ISD::SRL:
760 return DAG.getNode(MSP430ISD::SRL, dl,
761 VT, N->getOperand(0), N->getOperand(1));
762 }
763
764 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
765
766 // Expand the stuff into sequence of shifts.
767 // FIXME: for some shift amounts this might be done better!
768 // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
769 SDValue Victim = N->getOperand(0);
770
771 if (Opc == ISD::SRL && ShiftAmount) {
772 // Emit a special goodness here:
773 // srl A, 1 => clrc; rrc A
774 Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
775 ShiftAmount -= 1;
776 }
777
778 while (ShiftAmount--)
779 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
780 dl, VT, Victim);
781
782 return Victim;
783 }
784
LowerGlobalAddress(SDValue Op,SelectionDAG & DAG) const785 SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
786 SelectionDAG &DAG) const {
787 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
788 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
789
790 // Create the TargetGlobalAddress node, folding in the constant offset.
791 SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
792 getPointerTy(), Offset);
793 return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op),
794 getPointerTy(), Result);
795 }
796
LowerExternalSymbol(SDValue Op,SelectionDAG & DAG) const797 SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
798 SelectionDAG &DAG) const {
799 SDLoc dl(Op);
800 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
801 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
802
803 return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);
804 }
805
LowerBlockAddress(SDValue Op,SelectionDAG & DAG) const806 SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
807 SelectionDAG &DAG) const {
808 SDLoc dl(Op);
809 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
810 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy());
811
812 return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);
813 }
814
EmitCMP(SDValue & LHS,SDValue & RHS,SDValue & TargetCC,ISD::CondCode CC,SDLoc dl,SelectionDAG & DAG)815 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
816 ISD::CondCode CC,
817 SDLoc dl, SelectionDAG &DAG) {
818 // FIXME: Handle bittests someday
819 assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
820
821 // FIXME: Handle jump negative someday
822 MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
823 switch (CC) {
824 default: llvm_unreachable("Invalid integer condition!");
825 case ISD::SETEQ:
826 TCC = MSP430CC::COND_E; // aka COND_Z
827 // Minor optimization: if LHS is a constant, swap operands, then the
828 // constant can be folded into comparison.
829 if (LHS.getOpcode() == ISD::Constant)
830 std::swap(LHS, RHS);
831 break;
832 case ISD::SETNE:
833 TCC = MSP430CC::COND_NE; // aka COND_NZ
834 // Minor optimization: if LHS is a constant, swap operands, then the
835 // constant can be folded into comparison.
836 if (LHS.getOpcode() == ISD::Constant)
837 std::swap(LHS, RHS);
838 break;
839 case ISD::SETULE:
840 std::swap(LHS, RHS); // FALLTHROUGH
841 case ISD::SETUGE:
842 // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
843 // fold constant into instruction.
844 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
845 LHS = RHS;
846 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
847 TCC = MSP430CC::COND_LO;
848 break;
849 }
850 TCC = MSP430CC::COND_HS; // aka COND_C
851 break;
852 case ISD::SETUGT:
853 std::swap(LHS, RHS); // FALLTHROUGH
854 case ISD::SETULT:
855 // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
856 // fold constant into instruction.
857 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
858 LHS = RHS;
859 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
860 TCC = MSP430CC::COND_HS;
861 break;
862 }
863 TCC = MSP430CC::COND_LO; // aka COND_NC
864 break;
865 case ISD::SETLE:
866 std::swap(LHS, RHS); // FALLTHROUGH
867 case ISD::SETGE:
868 // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
869 // fold constant into instruction.
870 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
871 LHS = RHS;
872 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
873 TCC = MSP430CC::COND_L;
874 break;
875 }
876 TCC = MSP430CC::COND_GE;
877 break;
878 case ISD::SETGT:
879 std::swap(LHS, RHS); // FALLTHROUGH
880 case ISD::SETLT:
881 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
882 // fold constant into instruction.
883 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
884 LHS = RHS;
885 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
886 TCC = MSP430CC::COND_GE;
887 break;
888 }
889 TCC = MSP430CC::COND_L;
890 break;
891 }
892
893 TargetCC = DAG.getConstant(TCC, MVT::i8);
894 return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
895 }
896
897
LowerBR_CC(SDValue Op,SelectionDAG & DAG) const898 SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
899 SDValue Chain = Op.getOperand(0);
900 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
901 SDValue LHS = Op.getOperand(2);
902 SDValue RHS = Op.getOperand(3);
903 SDValue Dest = Op.getOperand(4);
904 SDLoc dl (Op);
905
906 SDValue TargetCC;
907 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
908
909 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
910 Chain, Dest, TargetCC, Flag);
911 }
912
LowerSETCC(SDValue Op,SelectionDAG & DAG) const913 SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
914 SDValue LHS = Op.getOperand(0);
915 SDValue RHS = Op.getOperand(1);
916 SDLoc dl (Op);
917
918 // If we are doing an AND and testing against zero, then the CMP
919 // will not be generated. The AND (or BIT) will generate the condition codes,
920 // but they are different from CMP.
921 // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
922 // lowering & isel wouldn't diverge.
923 bool andCC = false;
924 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
925 if (RHSC->isNullValue() && LHS.hasOneUse() &&
926 (LHS.getOpcode() == ISD::AND ||
927 (LHS.getOpcode() == ISD::TRUNCATE &&
928 LHS.getOperand(0).getOpcode() == ISD::AND))) {
929 andCC = true;
930 }
931 }
932 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
933 SDValue TargetCC;
934 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
935
936 // Get the condition codes directly from the status register, if its easy.
937 // Otherwise a branch will be generated. Note that the AND and BIT
938 // instructions generate different flags than CMP, the carry bit can be used
939 // for NE/EQ.
940 bool Invert = false;
941 bool Shift = false;
942 bool Convert = true;
943 switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
944 default:
945 Convert = false;
946 break;
947 case MSP430CC::COND_HS:
948 // Res = SR & 1, no processing is required
949 break;
950 case MSP430CC::COND_LO:
951 // Res = ~(SR & 1)
952 Invert = true;
953 break;
954 case MSP430CC::COND_NE:
955 if (andCC) {
956 // C = ~Z, thus Res = SR & 1, no processing is required
957 } else {
958 // Res = ~((SR >> 1) & 1)
959 Shift = true;
960 Invert = true;
961 }
962 break;
963 case MSP430CC::COND_E:
964 Shift = true;
965 // C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however,
966 // Res = (SR >> 1) & 1 is 1 word shorter.
967 break;
968 }
969 EVT VT = Op.getValueType();
970 SDValue One = DAG.getConstant(1, VT);
971 if (Convert) {
972 SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR,
973 MVT::i16, Flag);
974 if (Shift)
975 // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
976 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
977 SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
978 if (Invert)
979 SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
980 return SR;
981 } else {
982 SDValue Zero = DAG.getConstant(0, VT);
983 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
984 SDValue Ops[] = {One, Zero, TargetCC, Flag};
985 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
986 }
987 }
988
LowerSELECT_CC(SDValue Op,SelectionDAG & DAG) const989 SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
990 SelectionDAG &DAG) const {
991 SDValue LHS = Op.getOperand(0);
992 SDValue RHS = Op.getOperand(1);
993 SDValue TrueV = Op.getOperand(2);
994 SDValue FalseV = Op.getOperand(3);
995 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
996 SDLoc dl (Op);
997
998 SDValue TargetCC;
999 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1000
1001 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1002 SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag};
1003
1004 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
1005 }
1006
LowerSIGN_EXTEND(SDValue Op,SelectionDAG & DAG) const1007 SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
1008 SelectionDAG &DAG) const {
1009 SDValue Val = Op.getOperand(0);
1010 EVT VT = Op.getValueType();
1011 SDLoc dl(Op);
1012
1013 assert(VT == MVT::i16 && "Only support i16 for now!");
1014
1015 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
1016 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
1017 DAG.getValueType(Val.getValueType()));
1018 }
1019
1020 SDValue
getReturnAddressFrameIndex(SelectionDAG & DAG) const1021 MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
1022 MachineFunction &MF = DAG.getMachineFunction();
1023 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
1024 int ReturnAddrIndex = FuncInfo->getRAIndex();
1025
1026 if (ReturnAddrIndex == 0) {
1027 // Set up a frame object for the return address.
1028 uint64_t SlotSize = getDataLayout()->getPointerSize();
1029 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
1030 true);
1031 FuncInfo->setRAIndex(ReturnAddrIndex);
1032 }
1033
1034 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1035 }
1036
LowerRETURNADDR(SDValue Op,SelectionDAG & DAG) const1037 SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
1038 SelectionDAG &DAG) const {
1039 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1040 MFI->setReturnAddressIsTaken(true);
1041
1042 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1043 return SDValue();
1044
1045 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1046 SDLoc dl(Op);
1047
1048 if (Depth > 0) {
1049 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1050 SDValue Offset =
1051 DAG.getConstant(getDataLayout()->getPointerSize(), MVT::i16);
1052 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
1053 DAG.getNode(ISD::ADD, dl, getPointerTy(),
1054 FrameAddr, Offset),
1055 MachinePointerInfo(), false, false, false, 0);
1056 }
1057
1058 // Just load the return address.
1059 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
1060 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
1061 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
1062 }
1063
LowerFRAMEADDR(SDValue Op,SelectionDAG & DAG) const1064 SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
1065 SelectionDAG &DAG) const {
1066 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1067 MFI->setFrameAddressIsTaken(true);
1068
1069 EVT VT = Op.getValueType();
1070 SDLoc dl(Op); // FIXME probably not meaningful
1071 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1072 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1073 MSP430::FP, VT);
1074 while (Depth--)
1075 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1076 MachinePointerInfo(),
1077 false, false, false, 0);
1078 return FrameAddr;
1079 }
1080
LowerVASTART(SDValue Op,SelectionDAG & DAG) const1081 SDValue MSP430TargetLowering::LowerVASTART(SDValue Op,
1082 SelectionDAG &DAG) const {
1083 MachineFunction &MF = DAG.getMachineFunction();
1084 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
1085
1086 // Frame index of first vararg argument
1087 SDValue FrameIndex = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1088 getPointerTy());
1089 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1090
1091 // Create a store of the frame index to the location operand
1092 return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex,
1093 Op.getOperand(1), MachinePointerInfo(SV),
1094 false, false, 0);
1095 }
1096
LowerJumpTable(SDValue Op,SelectionDAG & DAG) const1097 SDValue MSP430TargetLowering::LowerJumpTable(SDValue Op,
1098 SelectionDAG &DAG) const {
1099 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1100 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
1101 return DAG.getNode(MSP430ISD::Wrapper, SDLoc(JT),
1102 getPointerTy(), Result);
1103 }
1104
1105 /// getPostIndexedAddressParts - returns true by value, base pointer and
1106 /// offset pointer and addressing mode by reference if this node can be
1107 /// combined with a load / store to form a post-indexed load / store.
getPostIndexedAddressParts(SDNode * N,SDNode * Op,SDValue & Base,SDValue & Offset,ISD::MemIndexedMode & AM,SelectionDAG & DAG) const1108 bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1109 SDValue &Base,
1110 SDValue &Offset,
1111 ISD::MemIndexedMode &AM,
1112 SelectionDAG &DAG) const {
1113
1114 LoadSDNode *LD = cast<LoadSDNode>(N);
1115 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1116 return false;
1117
1118 EVT VT = LD->getMemoryVT();
1119 if (VT != MVT::i8 && VT != MVT::i16)
1120 return false;
1121
1122 if (Op->getOpcode() != ISD::ADD)
1123 return false;
1124
1125 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1126 uint64_t RHSC = RHS->getZExtValue();
1127 if ((VT == MVT::i16 && RHSC != 2) ||
1128 (VT == MVT::i8 && RHSC != 1))
1129 return false;
1130
1131 Base = Op->getOperand(0);
1132 Offset = DAG.getConstant(RHSC, VT);
1133 AM = ISD::POST_INC;
1134 return true;
1135 }
1136
1137 return false;
1138 }
1139
1140
getTargetNodeName(unsigned Opcode) const1141 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
1142 switch (Opcode) {
1143 default: return nullptr;
1144 case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
1145 case MSP430ISD::RETI_FLAG: return "MSP430ISD::RETI_FLAG";
1146 case MSP430ISD::RRA: return "MSP430ISD::RRA";
1147 case MSP430ISD::RLA: return "MSP430ISD::RLA";
1148 case MSP430ISD::RRC: return "MSP430ISD::RRC";
1149 case MSP430ISD::CALL: return "MSP430ISD::CALL";
1150 case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
1151 case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
1152 case MSP430ISD::CMP: return "MSP430ISD::CMP";
1153 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC";
1154 case MSP430ISD::SHL: return "MSP430ISD::SHL";
1155 case MSP430ISD::SRA: return "MSP430ISD::SRA";
1156 }
1157 }
1158
isTruncateFree(Type * Ty1,Type * Ty2) const1159 bool MSP430TargetLowering::isTruncateFree(Type *Ty1,
1160 Type *Ty2) const {
1161 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
1162 return false;
1163
1164 return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
1165 }
1166
isTruncateFree(EVT VT1,EVT VT2) const1167 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1168 if (!VT1.isInteger() || !VT2.isInteger())
1169 return false;
1170
1171 return (VT1.getSizeInBits() > VT2.getSizeInBits());
1172 }
1173
isZExtFree(Type * Ty1,Type * Ty2) const1174 bool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
1175 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1176 return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1177 }
1178
isZExtFree(EVT VT1,EVT VT2) const1179 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
1180 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1181 return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1182 }
1183
isZExtFree(SDValue Val,EVT VT2) const1184 bool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
1185 return isZExtFree(Val.getValueType(), VT2);
1186 }
1187
1188 //===----------------------------------------------------------------------===//
1189 // Other Lowering Code
1190 //===----------------------------------------------------------------------===//
1191
1192 MachineBasicBlock*
EmitShiftInstr(MachineInstr * MI,MachineBasicBlock * BB) const1193 MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
1194 MachineBasicBlock *BB) const {
1195 MachineFunction *F = BB->getParent();
1196 MachineRegisterInfo &RI = F->getRegInfo();
1197 DebugLoc dl = MI->getDebugLoc();
1198 const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo();
1199
1200 unsigned Opc;
1201 const TargetRegisterClass * RC;
1202 switch (MI->getOpcode()) {
1203 default: llvm_unreachable("Invalid shift opcode!");
1204 case MSP430::Shl8:
1205 Opc = MSP430::SHL8r1;
1206 RC = &MSP430::GR8RegClass;
1207 break;
1208 case MSP430::Shl16:
1209 Opc = MSP430::SHL16r1;
1210 RC = &MSP430::GR16RegClass;
1211 break;
1212 case MSP430::Sra8:
1213 Opc = MSP430::SAR8r1;
1214 RC = &MSP430::GR8RegClass;
1215 break;
1216 case MSP430::Sra16:
1217 Opc = MSP430::SAR16r1;
1218 RC = &MSP430::GR16RegClass;
1219 break;
1220 case MSP430::Srl8:
1221 Opc = MSP430::SAR8r1c;
1222 RC = &MSP430::GR8RegClass;
1223 break;
1224 case MSP430::Srl16:
1225 Opc = MSP430::SAR16r1c;
1226 RC = &MSP430::GR16RegClass;
1227 break;
1228 }
1229
1230 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1231 MachineFunction::iterator I = BB;
1232 ++I;
1233
1234 // Create loop block
1235 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1236 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1237
1238 F->insert(I, LoopBB);
1239 F->insert(I, RemBB);
1240
1241 // Update machine-CFG edges by transferring all successors of the current
1242 // block to the block containing instructions after shift.
1243 RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1244 BB->end());
1245 RemBB->transferSuccessorsAndUpdatePHIs(BB);
1246
1247 // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1248 BB->addSuccessor(LoopBB);
1249 BB->addSuccessor(RemBB);
1250 LoopBB->addSuccessor(RemBB);
1251 LoopBB->addSuccessor(LoopBB);
1252
1253 unsigned ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1254 unsigned ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1255 unsigned ShiftReg = RI.createVirtualRegister(RC);
1256 unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1257 unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
1258 unsigned SrcReg = MI->getOperand(1).getReg();
1259 unsigned DstReg = MI->getOperand(0).getReg();
1260
1261 // BB:
1262 // cmp 0, N
1263 // je RemBB
1264 BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1265 .addReg(ShiftAmtSrcReg).addImm(0);
1266 BuildMI(BB, dl, TII.get(MSP430::JCC))
1267 .addMBB(RemBB)
1268 .addImm(MSP430CC::COND_E);
1269
1270 // LoopBB:
1271 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1272 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1273 // ShiftReg2 = shift ShiftReg
1274 // ShiftAmt2 = ShiftAmt - 1;
1275 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1276 .addReg(SrcReg).addMBB(BB)
1277 .addReg(ShiftReg2).addMBB(LoopBB);
1278 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1279 .addReg(ShiftAmtSrcReg).addMBB(BB)
1280 .addReg(ShiftAmtReg2).addMBB(LoopBB);
1281 BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1282 .addReg(ShiftReg);
1283 BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1284 .addReg(ShiftAmtReg).addImm(1);
1285 BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1286 .addMBB(LoopBB)
1287 .addImm(MSP430CC::COND_NE);
1288
1289 // RemBB:
1290 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1291 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1292 .addReg(SrcReg).addMBB(BB)
1293 .addReg(ShiftReg2).addMBB(LoopBB);
1294
1295 MI->eraseFromParent(); // The pseudo instruction is gone now.
1296 return RemBB;
1297 }
1298
1299 MachineBasicBlock*
EmitInstrWithCustomInserter(MachineInstr * MI,MachineBasicBlock * BB) const1300 MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1301 MachineBasicBlock *BB) const {
1302 unsigned Opc = MI->getOpcode();
1303
1304 if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1305 Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1306 Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1307 return EmitShiftInstr(MI, BB);
1308
1309 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
1310 DebugLoc dl = MI->getDebugLoc();
1311
1312 assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1313 "Unexpected instr type to insert");
1314
1315 // To "insert" a SELECT instruction, we actually have to insert the diamond
1316 // control-flow pattern. The incoming instruction knows the destination vreg
1317 // to set, the condition code register to branch on, the true/false values to
1318 // select between, and a branch opcode to use.
1319 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1320 MachineFunction::iterator I = BB;
1321 ++I;
1322
1323 // thisMBB:
1324 // ...
1325 // TrueVal = ...
1326 // cmpTY ccX, r1, r2
1327 // jCC copy1MBB
1328 // fallthrough --> copy0MBB
1329 MachineBasicBlock *thisMBB = BB;
1330 MachineFunction *F = BB->getParent();
1331 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1332 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1333 F->insert(I, copy0MBB);
1334 F->insert(I, copy1MBB);
1335 // Update machine-CFG edges by transferring all successors of the current
1336 // block to the new block which will contain the Phi node for the select.
1337 copy1MBB->splice(copy1MBB->begin(), BB,
1338 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1339 copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1340 // Next, add the true and fallthrough blocks as its successors.
1341 BB->addSuccessor(copy0MBB);
1342 BB->addSuccessor(copy1MBB);
1343
1344 BuildMI(BB, dl, TII.get(MSP430::JCC))
1345 .addMBB(copy1MBB)
1346 .addImm(MI->getOperand(3).getImm());
1347
1348 // copy0MBB:
1349 // %FalseValue = ...
1350 // # fallthrough to copy1MBB
1351 BB = copy0MBB;
1352
1353 // Update machine-CFG edges
1354 BB->addSuccessor(copy1MBB);
1355
1356 // copy1MBB:
1357 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1358 // ...
1359 BB = copy1MBB;
1360 BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI),
1361 MI->getOperand(0).getReg())
1362 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1363 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1364
1365 MI->eraseFromParent(); // The pseudo instruction is gone now.
1366 return BB;
1367 }
1368