1//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips64 instructions. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Mips Operand, Complex Patterns and Transformations Definitions. 16//===----------------------------------------------------------------------===// 17 18// Unsigned Operand 19def uimm5_64 : Operand<i64> { 20 let PrintMethod = "printUnsignedImm"; 21} 22 23def uimm16_64 : Operand<i64> { 24 let PrintMethod = "printUnsignedImm"; 25} 26 27// Signed Operand 28def simm10_64 : Operand<i64>; 29 30def imm64: Operand<i64>; 31 32// Transformation Function - get Imm - 32. 33def Subtract32 : SDNodeXForm<imm, [{ 34 return getImm(N, (unsigned)N->getZExtValue() - 32); 35}]>; 36 37// shamt must fit in 6 bits. 38def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 39 40// Node immediate fits as 10-bit sign extended on target immediate. 41// e.g. seqi, snei 42def immSExt10_64 : PatLeaf<(i64 imm), 43 [{ return isInt<10>(N->getSExtValue()); }]>; 44 45def immZExt16_64 : PatLeaf<(i64 imm), 46 [{ return isInt<16>(N->getZExtValue()); }]>; 47 48def immZExt5_64 : ImmLeaf<i64, [{ return Imm == (Imm & 0x1f); }]>; 49 50// Transformation function: get log2 of low 32 bits of immediate 51def Log2LO : SDNodeXForm<imm, [{ 52 return getImm(N, Log2_64((unsigned) N->getZExtValue())); 53}]>; 54 55// Transformation function: get log2 of high 32 bits of immediate 56def Log2HI : SDNodeXForm<imm, [{ 57 return getImm(N, Log2_64((unsigned) (N->getZExtValue() >> 32))); 58}]>; 59 60// Predicate: True if immediate is a power of 2 and fits 32 bits 61def PowerOf2LO : PatLeaf<(imm), [{ 62 if (N->getValueType(0) == MVT::i64) { 63 uint64_t Imm = N->getZExtValue(); 64 return isPowerOf2_64(Imm) && (Imm & 0xffffffff) == Imm; 65 } 66 else 67 return false; 68}]>; 69 70// Predicate: True if immediate is a power of 2 and exceeds 32 bits 71def PowerOf2HI : PatLeaf<(imm), [{ 72 if (N->getValueType(0) == MVT::i64) { 73 uint64_t Imm = N->getZExtValue(); 74 return isPowerOf2_64(Imm) && (Imm & 0xffffffff00000000) == Imm; 75 } 76 else 77 return false; 78}]>; 79 80//===----------------------------------------------------------------------===// 81// Instructions specific format 82//===----------------------------------------------------------------------===// 83let usesCustomInserter = 1 in { 84 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>; 85 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>; 86 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>; 87 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>; 88 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>; 89 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>; 90 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>; 91 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>; 92} 93 94/// Pseudo instructions for loading and storing accumulator registers. 95let isPseudo = 1, isCodeGenOnly = 1 in { 96 def LOAD_ACC128 : Load<"", ACC128>; 97 def STORE_ACC128 : Store<"", ACC128>; 98} 99 100//===----------------------------------------------------------------------===// 101// Instruction definition 102//===----------------------------------------------------------------------===// 103let DecoderNamespace = "Mips64" in { 104/// Arithmetic Instructions (ALU Immediate) 105def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>, 106 ISA_MIPS3_NOT_32R6_64R6; 107def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU, 108 immSExt16, add>, 109 ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3; 110 111let isCodeGenOnly = 1 in { 112def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>, 113 SLTI_FM<0xa>; 114def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>, 115 SLTI_FM<0xb>; 116def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>, 117 ADDI_FM<0xc>; 118def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>, 119 ADDI_FM<0xd>; 120def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>, 121 ADDI_FM<0xe>; 122def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM; 123} 124 125/// Arithmetic Instructions (3-Operand, R-Type) 126def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>, 127 ISA_MIPS3; 128def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, ADD_FM<0, 0x2d>, 129 ISA_MIPS3; 130def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>, 131 ISA_MIPS3; 132def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>, 133 ISA_MIPS3; 134 135let isCodeGenOnly = 1 in { 136def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>; 137def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>; 138def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>; 139def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>; 140def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>; 141def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>; 142} 143 144/// Shift Instructions 145def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>, 146 SRA_FM<0x38, 0>, ISA_MIPS3; 147def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>, 148 SRA_FM<0x3a, 0>, ISA_MIPS3; 149def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>, 150 SRA_FM<0x3b, 0>, ISA_MIPS3; 151def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>, 152 SRLV_FM<0x14, 0>, ISA_MIPS3; 153def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>, 154 SRLV_FM<0x16, 0>, ISA_MIPS3; 155def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>, 156 SRLV_FM<0x17, 0>, ISA_MIPS3; 157def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>, 158 SRA_FM<0x3c, 0>, ISA_MIPS3; 159def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>, 160 SRA_FM<0x3e, 0>, ISA_MIPS3; 161def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>, 162 SRA_FM<0x3f, 0>, ISA_MIPS3; 163 164// Rotate Instructions 165def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr, 166 immZExt6>, 167 SRA_FM<0x3a, 1>, ISA_MIPS64R2; 168def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>, 169 SRLV_FM<0x16, 1>, ISA_MIPS64R2; 170def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>, 171 SRA_FM<0x3e, 1>, ISA_MIPS64R2; 172 173/// Load and Store Instructions 174/// aligned 175let isCodeGenOnly = 1 in { 176def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>; 177def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>; 178def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>; 179def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>; 180def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>; 181def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>; 182def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>; 183def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>; 184} 185 186def LWu : Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>, ISA_MIPS3; 187def LD : Load<"ld", GPR64Opnd, load, II_LD>, LW_FM<0x37>, ISA_MIPS3; 188def SD : Store<"sd", GPR64Opnd, store, II_SD>, LW_FM<0x3f>, ISA_MIPS3; 189 190/// load/store left/right 191let isCodeGenOnly = 1 in { 192def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>; 193def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>; 194def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>; 195def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>; 196} 197 198def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>, 199 ISA_MIPS3_NOT_32R6_64R6; 200def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>, 201 ISA_MIPS3_NOT_32R6_64R6; 202def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>, 203 ISA_MIPS3_NOT_32R6_64R6; 204def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>, 205 ISA_MIPS3_NOT_32R6_64R6; 206 207/// Load-linked, Store-conditional 208def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>, ISA_MIPS3_NOT_32R6_64R6; 209def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6; 210 211/// Jump and Branch Instructions 212let isCodeGenOnly = 1 in { 213 def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>; 214 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>; 215 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>; 216 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>; 217 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>; 218 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>; 219 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>; 220 def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM; 221 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>; 222 def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>; 223} 224 225def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>; 226def PseudoIndirectBranch64 : PseudoIndirectBranchBase<GPR64Opnd>; 227 228/// Multiply and Divide Instructions. 229def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>, 230 MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6; 231def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>, 232 MULT_FM<0, 0x1d>, ISA_MIPS3_NOT_32R6_64R6; 233def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult, 234 II_DMULT>, ISA_MIPS3_NOT_32R6_64R6; 235def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu, 236 II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6; 237def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>, 238 MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6; 239def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>, 240 MULT_FM<0, 0x1f>, ISA_MIPS3_NOT_32R6_64R6; 241def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem, 242 II_DDIV, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6; 243def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU, 244 II_DDIVU, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6; 245 246let isCodeGenOnly = 1 in { 247def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>, 248 ISA_MIPS3_NOT_32R6_64R6; 249def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>, 250 ISA_MIPS3_NOT_32R6_64R6; 251def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>, 252 ISA_MIPS3_NOT_32R6_64R6; 253def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>, 254 ISA_MIPS3_NOT_32R6_64R6; 255def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>, 256 ISA_MIPS3_NOT_32R6_64R6; 257def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>, 258 ISA_MIPS3_NOT_32R6_64R6; 259def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>, ISA_MIPS3_NOT_32R6_64R6; 260 261/// Sign Ext In Register Instructions. 262def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>, 263 ISA_MIPS32R2; 264def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>, 265 ISA_MIPS32R2; 266} 267 268/// Count Leading 269def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64_NOT_64R6; 270def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64_NOT_64R6; 271 272/// Double Word Swap Bytes/HalfWords 273def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2; 274def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2; 275 276def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>; 277 278let isCodeGenOnly = 1 in 279def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM; 280 281def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>; 282def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>; 283def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>; 284 285def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>; 286def DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>; 287def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>; 288 289let isCodeGenOnly = 1, rs = 0, shamt = 0 in { 290 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt), 291 "dsll\t$rd, $rt, 32", [], II_DSLL>; 292 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt), 293 "sll\t$rd, $rt, 0", [], II_SLL>; 294 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt), 295 "sll\t$rd, $rt, 0", [], II_SLL>; 296} 297 298// We need the following pseudo instruction to avoid offset calculation for 299// long branches. See the comment in file MipsLongBranch.cpp for detailed 300// explanation. 301 302// Expands to: daddiu $dst, $src, %PART($tgt - $baltgt) 303// where %PART may be %hi or %lo, depending on the relocation kind 304// that $tgt is annotated with. 305def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst), 306 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>; 307 308// Cavium Octeon cmMIPS instructions 309let EncodingPredicates = []<Predicate>, // FIXME: The lack of HasStdEnc is probably a bug 310 AdditionalPredicates = [HasCnMips] in { 311 312class Count1s<string opstr, RegisterOperand RO>: 313 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 314 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> { 315 let TwoOperandAliasConstraint = "$rd = $rs"; 316} 317 318class ExtsCins<string opstr, SDPatternOperator Op = null_frag>: 319 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1), 320 !strconcat(opstr, " $rt, $rs, $pos, $lenm1"), 321 [(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))], 322 NoItinerary, FrmR, opstr> { 323 let TwoOperandAliasConstraint = "$rt = $rs"; 324} 325 326class SetCC64_R<string opstr, PatFrag cond_op> : 327 InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt), 328 !strconcat(opstr, "\t$rd, $rs, $rt"), 329 [(set GPR64Opnd:$rd, (zext (cond_op GPR64Opnd:$rs, 330 GPR64Opnd:$rt)))], 331 II_SEQ_SNE, FrmR, opstr> { 332 let TwoOperandAliasConstraint = "$rd = $rs"; 333} 334 335class SetCC64_I<string opstr, PatFrag cond_op>: 336 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10), 337 !strconcat(opstr, "\t$rt, $rs, $imm10"), 338 [(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs, 339 immSExt10_64:$imm10)))], 340 II_SEQI_SNEI, FrmI, opstr> { 341 let TwoOperandAliasConstraint = "$rt = $rs"; 342} 343 344class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op, 345 RegisterOperand RO, bits<64> shift = 1> : 346 InstSE<(outs), (ins RO:$rs, uimm5_64:$p, opnd:$offset), 347 !strconcat(opstr, "\t$rs, $p, $offset"), 348 [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)), 349 bb:$offset)], IIBranch, FrmI, opstr> { 350 let isBranch = 1; 351 let isTerminator = 1; 352 let hasDelaySlot = 1; 353 let Defs = [AT]; 354} 355 356// Unsigned Byte Add 357let Pattern = [(set GPR64Opnd:$rd, 358 (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in 359def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>, 360 ADD_FM<0x1c, 0x28>; 361 362// Branch on Bit Clear /+32 363def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd>, BBIT_FM<0x32>; 364def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, 0x100000000>, 365 BBIT_FM<0x36>; 366 367// Branch on Bit Set /+32 368def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd>, BBIT_FM<0x3a>; 369def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, 0x100000000>, 370 BBIT_FM<0x3e>; 371 372// Multiply Doubleword to GPR 373let Defs = [HI0, LO0, P0, P1, P2] in 374def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>, 375 ADD_FM<0x1c, 0x03>; 376 377// Extract a signed bit field /+32 378def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>; 379def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>; 380 381// Clear and insert a bit field /+32 382def CINS : ExtsCins<"cins">, EXTS_FM<0x32>; 383def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>; 384 385// Move to multiplier/product register 386def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>; 387def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>; 388def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>; 389def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>; 390def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>; 391def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>; 392 393// Count Ones in a Word/Doubleword 394def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>; 395def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>; 396 397// Set on equal/not equal 398def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>; 399def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>; 400def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>; 401def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>; 402 403// 192-bit x 64-bit Unsigned Multiply and Add 404let Defs = [P0, P1, P2] in 405def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>, 406 ADD_FM<0x1c, 0x11>; 407 408// 64-bit Unsigned Multiply and Add Move 409let Defs = [MPL0, P0, P1, P2] in 410def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>, 411 ADD_FM<0x1c, 0x10>; 412 413// 64-bit Unsigned Multiply and Add 414let Defs = [MPL1, MPL2, P0, P1, P2] in 415def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>, 416 ADD_FM<0x1c, 0x0f>; 417 418} 419 420} 421 422/// Move between CPU and coprocessor registers 423let DecoderNamespace = "Mips64", Predicates = [HasMips64] in { 424def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>; 425def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3; 426def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3; 427def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3; 428} 429 430//===----------------------------------------------------------------------===// 431// Arbitrary patterns that map to one or more instructions 432//===----------------------------------------------------------------------===// 433 434// extended loads 435def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; 436def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; 437def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; 438def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; 439 440// hi/lo relocs 441def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; 442def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>; 443def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>; 444def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>; 445def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>; 446def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>; 447 448def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>; 449def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>; 450def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>; 451def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>; 452def : MipsPat<(MipsLo tglobaltlsaddr:$in), 453 (DADDiu ZERO_64, tglobaltlsaddr:$in)>; 454def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>; 455 456def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)), 457 (DADDiu GPR64:$hi, tglobaladdr:$lo)>; 458def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)), 459 (DADDiu GPR64:$hi, tblockaddress:$lo)>; 460def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)), 461 (DADDiu GPR64:$hi, tjumptable:$lo)>; 462def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)), 463 (DADDiu GPR64:$hi, tconstpool:$lo)>; 464def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)), 465 (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>; 466 467def : WrapperPat<tglobaladdr, DADDiu, GPR64>; 468def : WrapperPat<tconstpool, DADDiu, GPR64>; 469def : WrapperPat<texternalsym, DADDiu, GPR64>; 470def : WrapperPat<tblockaddress, DADDiu, GPR64>; 471def : WrapperPat<tjumptable, DADDiu, GPR64>; 472def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>; 473 474defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 475 ZERO_64>; 476 477def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst), 478 (BLEZ64 i64:$lhs, bb:$dst)>; 479def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst), 480 (BGEZ64 i64:$lhs, bb:$dst)>; 481 482// setcc patterns 483defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>; 484defm : SetlePats<GPR64, SLT64, SLTu64>; 485defm : SetgtPats<GPR64, SLT64, SLTu64>; 486defm : SetgePats<GPR64, SLT64, SLTu64>; 487defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>; 488 489// truncate 490def : MipsPat<(trunc (assertsext GPR64:$src)), 491 (EXTRACT_SUBREG GPR64:$src, sub_32)>; 492def : MipsPat<(trunc (assertzext GPR64:$src)), 493 (EXTRACT_SUBREG GPR64:$src, sub_32)>; 494def : MipsPat<(i32 (trunc GPR64:$src)), 495 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>; 496 497// Bypass trunc nodes for bitwise ops. 498def : MipsPat<(i32 (trunc (and GPR64:$lhs, GPR64:$rhs))), 499 (EXTRACT_SUBREG (AND64 GPR64:$lhs, GPR64:$rhs), sub_32)>; 500def : MipsPat<(i32 (trunc (or GPR64:$lhs, GPR64:$rhs))), 501 (EXTRACT_SUBREG (OR64 GPR64:$lhs, GPR64:$rhs), sub_32)>; 502def : MipsPat<(i32 (trunc (xor GPR64:$lhs, GPR64:$rhs))), 503 (EXTRACT_SUBREG (XOR64 GPR64:$lhs, GPR64:$rhs), sub_32)>; 504 505// 32-to-64-bit extension 506def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>; 507def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>; 508def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>; 509 510// Sign extend in register 511def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)), 512 (SLL64_64 GPR64:$src)>; 513 514// bswap MipsPattern 515def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>; 516 517// Carry pattern 518def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs), 519 (DSUBu GPR64:$lhs, GPR64:$rhs)>; 520let AdditionalPredicates = [NotDSP] in { 521 def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs), 522 (DADDu GPR64:$lhs, GPR64:$rhs)>; 523 def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm), 524 (DADDiu GPR64:$lhs, imm:$imm)>; 525} 526 527// Octeon bbit0/bbit1 MipsPattern 528let Predicates = [HasMips64, HasCnMips] in { 529def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), 530 (BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>; 531def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), 532 (BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>; 533def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), 534 (BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>; 535def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), 536 (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>; 537} 538 539//===----------------------------------------------------------------------===// 540// Instruction aliases 541//===----------------------------------------------------------------------===// 542def : MipsInstAlias<"move $dst, $src", 543 (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>, 544 GPR_64; 545def : MipsInstAlias<"daddu $rs, $rt, $imm", 546 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 547 0>, ISA_MIPS3; 548def : MipsInstAlias<"dadd $rs, $rt, $imm", 549 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 550 0>, ISA_MIPS3_NOT_32R6_64R6; 551def : MipsInstAlias<"daddu $rs, $imm", 552 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), 553 0>, ISA_MIPS3; 554def : MipsInstAlias<"dadd $rs, $imm", 555 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), 556 0>, ISA_MIPS3_NOT_32R6_64R6; 557def : MipsInstAlias<"dsll $rd, $rt, $rs", 558 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, 559 ISA_MIPS3; 560def : MipsInstAlias<"dsubu $rt, $rs, $imm", 561 (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs, 562 InvertedImOperand64:$imm), 0>, ISA_MIPS3; 563def : MipsInstAlias<"dsubi $rs, $rt, $imm", 564 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, 565 InvertedImOperand64:$imm), 566 0>, ISA_MIPS3_NOT_32R6_64R6; 567def : MipsInstAlias<"dsubi $rs, $imm", 568 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, 569 InvertedImOperand64:$imm), 570 0>, ISA_MIPS3_NOT_32R6_64R6; 571def : MipsInstAlias<"dsub $rs, $rt, $imm", 572 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, 573 InvertedImOperand64:$imm), 574 0>, ISA_MIPS3_NOT_32R6_64R6; 575def : MipsInstAlias<"dsub $rs, $imm", 576 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, 577 InvertedImOperand64:$imm), 578 0>, ISA_MIPS3_NOT_32R6_64R6; 579def : MipsInstAlias<"dsubu $rs, $imm", 580 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, 581 InvertedImOperand64:$imm), 582 0>, ISA_MIPS3; 583def : MipsInstAlias<"dsra $rd, $rt, $rs", 584 (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, 585 ISA_MIPS3; 586def : MipsInstAlias<"dsrl $rd, $rt, $rs", 587 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, 588 ISA_MIPS3; 589 590// Two operand (implicit 0 selector) versions: 591def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>; 592def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>; 593def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>; 594def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>; 595 596let Predicates = [HasMips64, HasCnMips] in { 597def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>; 598def : MipsInstAlias<"syncs", (SYNC 0x6), 0>; 599def : MipsInstAlias<"syncw", (SYNC 0x4), 0>; 600def : MipsInstAlias<"syncws", (SYNC 0x5), 0>; 601} 602 603//===----------------------------------------------------------------------===// 604// Assembler Pseudo Instructions 605//===----------------------------------------------------------------------===// 606 607class LoadImmediate64<string instr_asm, Operand Od, RegisterOperand RO> : 608 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64), 609 !strconcat(instr_asm, "\t$rt, $imm64")> ; 610def LoadImm64 : LoadImmediate64<"dli", imm64, GPR64Opnd>; 611