1 //===-- MipsOptionRecord.cpp - Abstraction for storing information --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 #include "MipsOptionRecord.h"
11 #include "MipsELFStreamer.h"
12 #include "MipsTargetStreamer.h"
13 #include "llvm/MC/MCSectionELF.h"
14
15 using namespace llvm;
16
EmitMipsOptionRecord()17 void MipsRegInfoRecord::EmitMipsOptionRecord() {
18 MCAssembler &MCA = Streamer->getAssembler();
19 MipsTargetStreamer *MTS =
20 static_cast<MipsTargetStreamer *>(Streamer->getTargetStreamer());
21
22 Streamer->PushSection();
23
24 // We need to distinguish between N64 and the rest because at the moment
25 // we don't emit .Mips.options for other ELFs other than N64.
26 // Since .reginfo has the same information as .Mips.options (ODK_REGINFO),
27 // we can use the same abstraction (MipsRegInfoRecord class) to handle both.
28 if (MTS->getABI().IsN64()) {
29 // The EntrySize value of 1 seems strange since the records are neither
30 // 1-byte long nor fixed length but it matches the value GAS emits.
31 const MCSectionELF *Sec =
32 Context.getELFSection(".MIPS.options", ELF::SHT_MIPS_OPTIONS,
33 ELF::SHF_ALLOC | ELF::SHF_MIPS_NOSTRIP, 1, "");
34 MCA.getOrCreateSectionData(*Sec).setAlignment(8);
35 Streamer->SwitchSection(Sec);
36
37 Streamer->EmitIntValue(ELF::ODK_REGINFO, 1); // kind
38 Streamer->EmitIntValue(40, 1); // size
39 Streamer->EmitIntValue(0, 2); // section
40 Streamer->EmitIntValue(0, 4); // info
41 Streamer->EmitIntValue(ri_gprmask, 4);
42 Streamer->EmitIntValue(0, 4); // pad
43 Streamer->EmitIntValue(ri_cprmask[0], 4);
44 Streamer->EmitIntValue(ri_cprmask[1], 4);
45 Streamer->EmitIntValue(ri_cprmask[2], 4);
46 Streamer->EmitIntValue(ri_cprmask[3], 4);
47 Streamer->EmitIntValue(ri_gp_value, 8);
48 } else {
49 const MCSectionELF *Sec = Context.getELFSection(
50 ".reginfo", ELF::SHT_MIPS_REGINFO, ELF::SHF_ALLOC, 24, "");
51 MCA.getOrCreateSectionData(*Sec)
52 .setAlignment(MTS->getABI().IsN32() ? 8 : 4);
53 Streamer->SwitchSection(Sec);
54
55 Streamer->EmitIntValue(ri_gprmask, 4);
56 Streamer->EmitIntValue(ri_cprmask[0], 4);
57 Streamer->EmitIntValue(ri_cprmask[1], 4);
58 Streamer->EmitIntValue(ri_cprmask[2], 4);
59 Streamer->EmitIntValue(ri_cprmask[3], 4);
60 assert((ri_gp_value & 0xffffffff) == ri_gp_value);
61 Streamer->EmitIntValue(ri_gp_value, 4);
62 }
63
64 Streamer->PopSection();
65 }
66
SetPhysRegUsed(unsigned Reg,const MCRegisterInfo * MCRegInfo)67 void MipsRegInfoRecord::SetPhysRegUsed(unsigned Reg,
68 const MCRegisterInfo *MCRegInfo) {
69 unsigned Value = 0;
70
71 for (MCSubRegIterator SubRegIt(Reg, MCRegInfo, true); SubRegIt.isValid();
72 ++SubRegIt) {
73 unsigned CurrentSubReg = *SubRegIt;
74
75 unsigned EncVal = MCRegInfo->getEncodingValue(CurrentSubReg);
76 Value |= 1 << EncVal;
77
78 if (GPR32RegClass->contains(CurrentSubReg) ||
79 GPR64RegClass->contains(CurrentSubReg))
80 ri_gprmask |= Value;
81 else if (FGR32RegClass->contains(CurrentSubReg) ||
82 FGR64RegClass->contains(CurrentSubReg) ||
83 AFGR64RegClass->contains(CurrentSubReg) ||
84 MSA128BRegClass->contains(CurrentSubReg))
85 ri_cprmask[1] |= Value;
86 else if (COP2RegClass->contains(CurrentSubReg))
87 ri_cprmask[2] |= Value;
88 else if (COP3RegClass->contains(CurrentSubReg))
89 ri_cprmask[3] |= Value;
90 }
91 }
92