1//===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This describes the calling conventions for the PowerPC 32- and 64-bit
11// architectures.
12//
13//===----------------------------------------------------------------------===//
14
15/// CCIfSubtarget - Match if the current subtarget has a feature F.
16class CCIfSubtarget<string F, CCAction A>
17    : CCIf<!strconcat("static_cast<const PPCSubtarget&>"
18                       "(State.getMachineFunction().getSubtarget()).",
19                     F),
20          A>;
21class CCIfNotSubtarget<string F, CCAction A>
22    : CCIf<!strconcat("!static_cast<const PPCSubtarget&>"
23                       "(State.getMachineFunction().getSubtarget()).",
24                     F),
25          A>;
26
27//===----------------------------------------------------------------------===//
28// Return Value Calling Convention
29//===----------------------------------------------------------------------===//
30
31// PPC64 AnyReg return-value convention. No explicit register is specified for
32// the return-value. The register allocator is allowed and expected to choose
33// any free register.
34//
35// This calling convention is currently only supported by the stackmap and
36// patchpoint intrinsics. All other uses will result in an assert on Debug
37// builds. On Release builds we fallback to the PPC C calling convention.
38def RetCC_PPC64_AnyReg : CallingConv<[
39  CCCustom<"CC_PPC_AnyReg_Error">
40]>;
41
42// Return-value convention for PowerPC
43def RetCC_PPC : CallingConv<[
44  CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>,
45
46  // On PPC64, integer return values are always promoted to i64
47  CCIfType<[i32, i1], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>,
48  CCIfType<[i1], CCIfNotSubtarget<"isPPC64()", CCPromoteToType<i32>>>,
49
50  CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
51  CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
52  CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
53
54  // Floating point types returned as "direct" go into F1 .. F8; note that
55  // only the ELFv2 ABI fully utilizes all these registers.
56  CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
57  CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
58
59  // QPX vectors are returned in QF1 and QF2.
60  CCIfType<[v4f64, v4f32, v4i1],
61           CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1, QF2]>>>,
62
63  // Vector types returned as "direct" go into V2 .. V9; note that only the
64  // ELFv2 ABI fully utilizes all these registers.
65  CCIfType<[v16i8, v8i16, v4i32, v4f32], CCIfSubtarget<"hasAltivec()",
66           CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>,
67  CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()",
68           CCAssignToReg<[VSH2, VSH3, VSH4, VSH5, VSH6, VSH7, VSH8, VSH9]>>>
69]>;
70
71// No explicit register is specified for the AnyReg calling convention. The
72// register allocator may assign the arguments to any free register.
73//
74// This calling convention is currently only supported by the stackmap and
75// patchpoint intrinsics. All other uses will result in an assert on Debug
76// builds. On Release builds we fallback to the PPC C calling convention.
77def CC_PPC64_AnyReg : CallingConv<[
78  CCCustom<"CC_PPC_AnyReg_Error">
79]>;
80
81// Note that we don't currently have calling conventions for 64-bit
82// PowerPC, but handle all the complexities of the ABI in the lowering
83// logic.  FIXME: See if the logic can be simplified with use of CCs.
84// This may require some extensions to current table generation.
85
86// Simple calling convention for 64-bit ELF PowerPC fast isel.
87// Only handle ints and floats.  All ints are promoted to i64.
88// Vector types and quadword ints are not handled.
89def CC_PPC64_ELF_FIS : CallingConv<[
90  CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_PPC64_AnyReg>>,
91
92  CCIfType<[i1],  CCPromoteToType<i64>>,
93  CCIfType<[i8],  CCPromoteToType<i64>>,
94  CCIfType<[i16], CCPromoteToType<i64>>,
95  CCIfType<[i32], CCPromoteToType<i64>>,
96  CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
97  CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>
98]>;
99
100// Simple return-value convention for 64-bit ELF PowerPC fast isel.
101// All small ints are promoted to i64.  Vector types, quadword ints,
102// and multiple register returns are "supported" to avoid compile
103// errors, but none are handled by the fast selector.
104def RetCC_PPC64_ELF_FIS : CallingConv<[
105  CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>,
106
107  CCIfType<[i1],   CCPromoteToType<i64>>,
108  CCIfType<[i8],   CCPromoteToType<i64>>,
109  CCIfType<[i16],  CCPromoteToType<i64>>,
110  CCIfType<[i32],  CCPromoteToType<i64>>,
111  CCIfType<[i64],  CCAssignToReg<[X3, X4]>>,
112  CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
113  CCIfType<[f32],  CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
114  CCIfType<[f64],  CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
115  CCIfType<[v4f64, v4f32, v4i1],
116           CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1, QF2]>>>,
117  CCIfType<[v16i8, v8i16, v4i32, v4f32], CCIfSubtarget<"hasAltivec()",
118           CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>,
119  CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()",
120           CCAssignToReg<[VSH2, VSH3, VSH4, VSH5, VSH6, VSH7, VSH8, VSH9]>>>
121]>;
122
123//===----------------------------------------------------------------------===//
124// PowerPC System V Release 4 32-bit ABI
125//===----------------------------------------------------------------------===//
126
127def CC_PPC32_SVR4_Common : CallingConv<[
128  CCIfType<[i1], CCPromoteToType<i32>>,
129
130  // The ABI requires i64 to be passed in two adjacent registers with the first
131  // register having an odd register number.
132  CCIfType<[i32], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>,
133
134  // The first 8 integer arguments are passed in integer registers.
135  CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
136
137  // Make sure the i64 words from a long double are either both passed in
138  // registers or both passed on the stack.
139  CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignFPArgRegs">>>,
140
141  // FP values are passed in F1 - F8.
142  CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
143
144  // Split arguments have an alignment of 8 bytes on the stack.
145  CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>,
146
147  CCIfType<[i32], CCAssignToStack<4, 4>>,
148
149  // Floats are stored in double precision format, thus they have the same
150  // alignment and size as doubles.
151  CCIfType<[f32,f64], CCAssignToStack<8, 8>>,
152
153  // QPX vectors that are stored in double precision need 32-byte alignment.
154  CCIfType<[v4f64, v4i1], CCAssignToStack<32, 32>>,
155
156  // Vectors get 16-byte stack slots that are 16-byte aligned.
157  CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>
158]>;
159
160// This calling convention puts vector arguments always on the stack. It is used
161// to assign vector arguments which belong to the variable portion of the
162// parameter list of a variable argument function.
163def CC_PPC32_SVR4_VarArg : CallingConv<[
164  CCDelegateTo<CC_PPC32_SVR4_Common>
165]>;
166
167// In contrast to CC_PPC32_SVR4_VarArg, this calling convention first tries to
168// put vector arguments in vector registers before putting them on the stack.
169def CC_PPC32_SVR4 : CallingConv<[
170  // QPX vectors mirror the scalar FP convention.
171  CCIfType<[v4f64, v4f32, v4i1], CCIfSubtarget<"hasQPX()",
172    CCAssignToReg<[QF1, QF2, QF3, QF4, QF5, QF6, QF7, QF8]>>>,
173
174  // The first 12 Vector arguments are passed in AltiVec registers.
175  CCIfType<[v16i8, v8i16, v4i32, v4f32], CCIfSubtarget<"hasAltivec()",
176           CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9,
177                          V10, V11, V12, V13]>>>,
178  CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()",
179           CCAssignToReg<[VSH2, VSH3, VSH4, VSH5, VSH6, VSH7, VSH8, VSH9,
180                          VSH10, VSH11, VSH12, VSH13]>>>,
181
182  CCDelegateTo<CC_PPC32_SVR4_Common>
183]>;
184
185// Helper "calling convention" to handle aggregate by value arguments.
186// Aggregate by value arguments are always placed in the local variable space
187// of the caller. This calling convention is only used to assign those stack
188// offsets in the callers stack frame.
189//
190// Still, the address of the aggregate copy in the callers stack frame is passed
191// in a GPR (or in the parameter list area if all GPRs are allocated) from the
192// caller to the callee. The location for the address argument is assigned by
193// the CC_PPC32_SVR4 calling convention.
194//
195// The only purpose of CC_PPC32_SVR4_Custom_Dummy is to skip arguments which are
196// not passed by value.
197
198def CC_PPC32_SVR4_ByVal : CallingConv<[
199  CCIfByVal<CCPassByVal<4, 4>>,
200
201  CCCustom<"CC_PPC32_SVR4_Custom_Dummy">
202]>;
203
204def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27,
205                                       V28, V29, V30, V31)>;
206
207def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
208                                        R21, R22, R23, R24, R25, R26, R27, R28,
209                                        R29, R30, R31, F14, F15, F16, F17, F18,
210                                        F19, F20, F21, F22, F23, F24, F25, F26,
211                                        F27, F28, F29, F30, F31, CR2, CR3, CR4
212                                   )>;
213
214def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>;
215
216def CSR_SVR432   : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
217                                        R21, R22, R23, R24, R25, R26, R27, R28,
218                                        R29, R30, R31, F14, F15, F16, F17, F18,
219                                        F19, F20, F21, F22, F23, F24, F25, F26,
220                                        F27, F28, F29, F30, F31, CR2, CR3, CR4
221                                   )>;
222
223def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
224
225def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20,
226                                        X21, X22, X23, X24, X25, X26, X27, X28,
227                                        X29, X30, X31, F14, F15, F16, F17, F18,
228                                        F19, F20, F21, F22, F23, F24, F25, F26,
229                                        F27, F28, F29, F30, F31, CR2, CR3, CR4
230                                   )>;
231
232def CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>;
233
234def CSR_SVR464   : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
235                                        X21, X22, X23, X24, X25, X26, X27, X28,
236                                        X29, X30, X31, F14, F15, F16, F17, F18,
237                                        F19, F20, F21, F22, F23, F24, F25, F26,
238                                        F27, F28, F29, F30, F31, CR2, CR3, CR4
239                                   )>;
240
241def CSR_SVR464_Altivec : CalleeSavedRegs<(add CSR_SVR464, CSR_Altivec)>;
242
243def CSR_SVR464_R2 : CalleeSavedRegs<(add CSR_SVR464, X2)>;
244
245def CSR_SVR464_R2_Altivec : CalleeSavedRegs<(add CSR_SVR464_Altivec, X2)>;
246
247def CSR_NoRegs : CalleeSavedRegs<(add)>;
248
249def CSR_64_AllRegs: CalleeSavedRegs<(add X0, (sequence "X%u", 3, 10),
250                                             (sequence "X%u", 14, 31),
251                                             (sequence "F%u", 0, 31),
252                                             (sequence "CR%u", 0, 7))>;
253
254def CSR_64_AllRegs_Altivec : CalleeSavedRegs<(add CSR_64_AllRegs,
255                                             (sequence "V%u", 0, 31))>;
256
257def CSR_64_AllRegs_VSX : CalleeSavedRegs<(add CSR_64_AllRegs_Altivec,
258                                         (sequence "VSL%u", 0, 31),
259                                         (sequence "VSH%u", 0, 31))>;
260
261