1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 15 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 16 17 #include "PPC.h" 18 #include "PPCRegisterInfo.h" 19 #include "llvm/Target/TargetInstrInfo.h" 20 21 #define GET_INSTRINFO_HEADER 22 #include "PPCGenInstrInfo.inc" 23 24 namespace llvm { 25 26 /// PPCII - This namespace holds all of the PowerPC target-specific 27 /// per-instruction flags. These must match the corresponding definitions in 28 /// PPC.td and PPCInstrFormats.td. 29 namespace PPCII { 30 enum { 31 // PPC970 Instruction Flags. These flags describe the characteristics of the 32 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 33 // raw machine instructions. 34 35 /// PPC970_First - This instruction starts a new dispatch group, so it will 36 /// always be the first one in the group. 37 PPC970_First = 0x1, 38 39 /// PPC970_Single - This instruction starts a new dispatch group and 40 /// terminates it, so it will be the sole instruction in the group. 41 PPC970_Single = 0x2, 42 43 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 44 /// two dispatch pipes to be available to issue. 45 PPC970_Cracked = 0x4, 46 47 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 48 /// an instruction is issued to. 49 PPC970_Shift = 3, 50 PPC970_Mask = 0x07 << PPC970_Shift 51 }; 52 enum PPC970_Unit { 53 /// These are the various PPC970 execution unit pipelines. Each instruction 54 /// is one of these. 55 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 56 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 57 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 58 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 59 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 60 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 61 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 62 PPC970_BRU = 7 << PPC970_Shift // Branch Unit 63 }; 64 } // end namespace PPCII 65 66 class PPCSubtarget; 67 class PPCInstrInfo : public PPCGenInstrInfo { 68 PPCSubtarget &Subtarget; 69 const PPCRegisterInfo RI; 70 71 bool StoreRegToStackSlot(MachineFunction &MF, 72 unsigned SrcReg, bool isKill, int FrameIdx, 73 const TargetRegisterClass *RC, 74 SmallVectorImpl<MachineInstr*> &NewMIs, 75 bool &NonRI, bool &SpillsVRS) const; 76 bool LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, 77 unsigned DestReg, int FrameIdx, 78 const TargetRegisterClass *RC, 79 SmallVectorImpl<MachineInstr*> &NewMIs, 80 bool &NonRI, bool &SpillsVRS) const; 81 virtual void anchor(); 82 public: 83 explicit PPCInstrInfo(PPCSubtarget &STI); 84 85 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 86 /// such, whenever a client has an instance of instruction info, it should 87 /// always be able to get register info as well (through this method). 88 /// getRegisterInfo()89 const PPCRegisterInfo &getRegisterInfo() const { return RI; } 90 91 ScheduleHazardRecognizer * 92 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 93 const ScheduleDAG *DAG) const override; 94 ScheduleHazardRecognizer * 95 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 96 const ScheduleDAG *DAG) const override; 97 98 int getOperandLatency(const InstrItineraryData *ItinData, 99 const MachineInstr *DefMI, unsigned DefIdx, 100 const MachineInstr *UseMI, 101 unsigned UseIdx) const override; getOperandLatency(const InstrItineraryData * ItinData,SDNode * DefNode,unsigned DefIdx,SDNode * UseNode,unsigned UseIdx)102 int getOperandLatency(const InstrItineraryData *ItinData, 103 SDNode *DefNode, unsigned DefIdx, 104 SDNode *UseNode, unsigned UseIdx) const override { 105 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, 106 UseNode, UseIdx); 107 } 108 hasLowDefLatency(const InstrItineraryData * ItinData,const MachineInstr * DefMI,unsigned DefIdx)109 bool hasLowDefLatency(const InstrItineraryData *ItinData, 110 const MachineInstr *DefMI, 111 unsigned DefIdx) const override { 112 // Machine LICM should hoist all instructions in low-register-pressure 113 // situations; none are sufficiently free to justify leaving in a loop 114 // body. 115 return false; 116 } 117 118 bool isCoalescableExtInstr(const MachineInstr &MI, 119 unsigned &SrcReg, unsigned &DstReg, 120 unsigned &SubIdx) const override; 121 unsigned isLoadFromStackSlot(const MachineInstr *MI, 122 int &FrameIndex) const override; 123 unsigned isStoreToStackSlot(const MachineInstr *MI, 124 int &FrameIndex) const override; 125 126 // commuteInstruction - We can commute rlwimi instructions, but only if the 127 // rotate amt is zero. We also have to munge the immediates a bit. 128 MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const override; 129 130 bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 131 unsigned &SrcOpIdx2) const override; 132 133 void insertNoop(MachineBasicBlock &MBB, 134 MachineBasicBlock::iterator MI) const override; 135 136 137 // Branch analysis. 138 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 139 MachineBasicBlock *&FBB, 140 SmallVectorImpl<MachineOperand> &Cond, 141 bool AllowModify) const override; 142 unsigned RemoveBranch(MachineBasicBlock &MBB) const override; 143 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 144 MachineBasicBlock *FBB, 145 const SmallVectorImpl<MachineOperand> &Cond, 146 DebugLoc DL) const override; 147 148 // Select analysis. 149 bool canInsertSelect(const MachineBasicBlock&, 150 const SmallVectorImpl<MachineOperand> &Cond, 151 unsigned, unsigned, int&, int&, int&) const override; 152 void insertSelect(MachineBasicBlock &MBB, 153 MachineBasicBlock::iterator MI, DebugLoc DL, 154 unsigned DstReg, 155 const SmallVectorImpl<MachineOperand> &Cond, 156 unsigned TrueReg, unsigned FalseReg) const override; 157 158 void copyPhysReg(MachineBasicBlock &MBB, 159 MachineBasicBlock::iterator I, DebugLoc DL, 160 unsigned DestReg, unsigned SrcReg, 161 bool KillSrc) const override; 162 163 void storeRegToStackSlot(MachineBasicBlock &MBB, 164 MachineBasicBlock::iterator MBBI, 165 unsigned SrcReg, bool isKill, int FrameIndex, 166 const TargetRegisterClass *RC, 167 const TargetRegisterInfo *TRI) const override; 168 169 void loadRegFromStackSlot(MachineBasicBlock &MBB, 170 MachineBasicBlock::iterator MBBI, 171 unsigned DestReg, int FrameIndex, 172 const TargetRegisterClass *RC, 173 const TargetRegisterInfo *TRI) const override; 174 175 bool 176 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 177 178 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 179 unsigned Reg, MachineRegisterInfo *MRI) const override; 180 181 // If conversion by predication (only supported by some branch instructions). 182 // All of the profitability checks always return true; it is always 183 // profitable to use the predicated branches. isProfitableToIfCvt(MachineBasicBlock & MBB,unsigned NumCycles,unsigned ExtraPredCycles,const BranchProbability & Probability)184 bool isProfitableToIfCvt(MachineBasicBlock &MBB, 185 unsigned NumCycles, unsigned ExtraPredCycles, 186 const BranchProbability &Probability) const override { 187 return true; 188 } 189 190 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 191 unsigned NumT, unsigned ExtraT, 192 MachineBasicBlock &FMBB, 193 unsigned NumF, unsigned ExtraF, 194 const BranchProbability &Probability) const override; 195 isProfitableToDupForIfCvt(MachineBasicBlock & MBB,unsigned NumCycles,const BranchProbability & Probability)196 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, 197 unsigned NumCycles, 198 const BranchProbability 199 &Probability) const override { 200 return true; 201 } 202 isProfitableToUnpredicate(MachineBasicBlock & TMBB,MachineBasicBlock & FMBB)203 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 204 MachineBasicBlock &FMBB) const override { 205 return false; 206 } 207 208 // Predication support. 209 bool isPredicated(const MachineInstr *MI) const override; 210 211 bool isUnpredicatedTerminator(const MachineInstr *MI) const override; 212 213 bool PredicateInstruction(MachineInstr *MI, 214 const SmallVectorImpl<MachineOperand> &Pred) const override; 215 216 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 217 const SmallVectorImpl<MachineOperand> &Pred2) const override; 218 219 bool DefinesPredicate(MachineInstr *MI, 220 std::vector<MachineOperand> &Pred) const override; 221 222 bool isPredicable(MachineInstr *MI) const override; 223 224 // Comparison optimization. 225 226 227 bool analyzeCompare(const MachineInstr *MI, 228 unsigned &SrcReg, unsigned &SrcReg2, 229 int &Mask, int &Value) const override; 230 231 bool optimizeCompareInstr(MachineInstr *CmpInstr, 232 unsigned SrcReg, unsigned SrcReg2, 233 int Mask, int Value, 234 const MachineRegisterInfo *MRI) const override; 235 236 /// GetInstSize - Return the number of bytes of code the specified 237 /// instruction may be. This returns the maximum number of bytes. 238 /// 239 unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 240 241 void getNoopForMachoTarget(MCInst &NopInst) const override; 242 }; 243 244 } 245 246 #endif 247