1//===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This describes the calling conventions for the X86-32 and X86-64 11// architectures. 12// 13//===----------------------------------------------------------------------===// 14 15/// CCIfSubtarget - Match if the current subtarget has a feature F. 16class CCIfSubtarget<string F, CCAction A> 17 : CCIf<!strconcat("static_cast<const X86Subtarget&>" 18 "(State.getMachineFunction().getSubtarget()).", F), 19 A>; 20 21//===----------------------------------------------------------------------===// 22// Return Value Calling Conventions 23//===----------------------------------------------------------------------===// 24 25// Return-value conventions common to all X86 CC's. 26def RetCC_X86Common : CallingConv<[ 27 // Scalar values are returned in AX first, then DX. For i8, the ABI 28 // requires the values to be in AL and AH, however this code uses AL and DL 29 // instead. This is because using AH for the second register conflicts with 30 // the way LLVM does multiple return values -- a return of {i16,i8} would end 31 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI 32 // for functions that return two i8 values are currently expected to pack the 33 // values into an i16 (which uses AX, and thus AL:AH). 34 // 35 // For code that doesn't care about the ABI, we allow returning more than two 36 // integer values in registers. 37 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>, 38 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, 39 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, 40 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>, 41 42 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3 43 // can only be used by ABI non-compliant code. If the target doesn't have XMM 44 // registers, it won't have vector types. 45 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 46 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 47 48 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3 49 // can only be used by ABI non-compliant code. This vector type is only 50 // supported while using the AVX target feature. 51 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 52 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, 53 54 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3 55 // can only be used by ABI non-compliant code. This vector type is only 56 // supported while using the AVX-512 target feature. 57 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 58 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, 59 60 // MMX vector types are always returned in MM0. If the target doesn't have 61 // MM0, it doesn't support these vector types. 62 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>, 63 64 // Long double types are always returned in FP0 (even with SSE). 65 CCIfType<[f80], CCAssignToReg<[FP0, FP1]>> 66]>; 67 68// X86-32 C return-value convention. 69def RetCC_X86_32_C : CallingConv<[ 70 // The X86-32 calling convention returns FP values in FP0, unless marked 71 // with "inreg" (used here to distinguish one kind of reg from another, 72 // weirdly; this is really the sse-regparm calling convention) in which 73 // case they use XMM0, otherwise it is the same as the common X86 calling 74 // conv. 75 CCIfInReg<CCIfSubtarget<"hasSSE2()", 76 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 77 CCIfType<[f32,f64], CCAssignToReg<[FP0, FP1]>>, 78 CCDelegateTo<RetCC_X86Common> 79]>; 80 81// X86-32 FastCC return-value convention. 82def RetCC_X86_32_Fast : CallingConv<[ 83 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has 84 // SSE2. 85 // This can happen when a float, 2 x float, or 3 x float vector is split by 86 // target lowering, and is returned in 1-3 sse regs. 87 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, 88 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, 89 90 // For integers, ECX can be used as an extra return register 91 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>, 92 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, 93 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, 94 95 // Otherwise, it is the same as the common X86 calling convention. 96 CCDelegateTo<RetCC_X86Common> 97]>; 98 99// Intel_OCL_BI return-value convention. 100def RetCC_Intel_OCL_BI : CallingConv<[ 101 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3. 102 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], 103 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 104 105 // 256-bit FP vectors 106 // No more than 4 registers 107 CCIfType<[v8f32, v4f64, v8i32, v4i64], 108 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, 109 110 // 512-bit FP vectors 111 CCIfType<[v16f32, v8f64, v16i32, v8i64], 112 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, 113 114 // i32, i64 in the standard way 115 CCDelegateTo<RetCC_X86Common> 116]>; 117 118// X86-32 HiPE return-value convention. 119def RetCC_X86_32_HiPE : CallingConv<[ 120 // Promote all types to i32 121 CCIfType<[i8, i16], CCPromoteToType<i32>>, 122 123 // Return: HP, P, VAL1, VAL2 124 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>> 125]>; 126 127// X86-32 HiPE return-value convention. 128def RetCC_X86_32_VectorCall : CallingConv<[ 129 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3. 130 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 131 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 132 133 // 256-bit FP vectors 134 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 135 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, 136 137 // 512-bit FP vectors 138 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 139 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, 140 141 // Return integers in the standard way. 142 CCDelegateTo<RetCC_X86Common> 143]>; 144 145// X86-64 C return-value convention. 146def RetCC_X86_64_C : CallingConv<[ 147 // The X86-64 calling convention always returns FP values in XMM0. 148 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>, 149 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>, 150 151 // MMX vector types are always returned in XMM0. 152 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>, 153 CCDelegateTo<RetCC_X86Common> 154]>; 155 156// X86-Win64 C return-value convention. 157def RetCC_X86_Win64_C : CallingConv<[ 158 // The X86-Win64 calling convention always returns __m64 values in RAX. 159 CCIfType<[x86mmx], CCBitConvertToType<i64>>, 160 161 // Otherwise, everything is the same as 'normal' X86-64 C CC. 162 CCDelegateTo<RetCC_X86_64_C> 163]>; 164 165// X86-64 HiPE return-value convention. 166def RetCC_X86_64_HiPE : CallingConv<[ 167 // Promote all types to i64 168 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 169 170 // Return: HP, P, VAL1, VAL2 171 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>> 172]>; 173 174// X86-64 WebKit_JS return-value convention. 175def RetCC_X86_64_WebKit_JS : CallingConv<[ 176 // Promote all types to i64 177 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 178 179 // Return: RAX 180 CCIfType<[i64], CCAssignToReg<[RAX]>> 181]>; 182 183// X86-64 AnyReg return-value convention. No explicit register is specified for 184// the return-value. The register allocator is allowed and expected to choose 185// any free register. 186// 187// This calling convention is currently only supported by the stackmap and 188// patchpoint intrinsics. All other uses will result in an assert on Debug 189// builds. On Release builds we fallback to the X86 C calling convention. 190def RetCC_X86_64_AnyReg : CallingConv<[ 191 CCCustom<"CC_X86_AnyReg_Error"> 192]>; 193 194// This is the root return-value convention for the X86-32 backend. 195def RetCC_X86_32 : CallingConv<[ 196 // If FastCC, use RetCC_X86_32_Fast. 197 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>, 198 // If HiPE, use RetCC_X86_32_HiPE. 199 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>, 200 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_32_VectorCall>>, 201 202 // Otherwise, use RetCC_X86_32_C. 203 CCDelegateTo<RetCC_X86_32_C> 204]>; 205 206// This is the root return-value convention for the X86-64 backend. 207def RetCC_X86_64 : CallingConv<[ 208 // HiPE uses RetCC_X86_64_HiPE 209 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>, 210 211 // Handle JavaScript calls. 212 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<RetCC_X86_64_WebKit_JS>>, 213 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_X86_64_AnyReg>>, 214 215 // Handle explicit CC selection 216 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<RetCC_X86_Win64_C>>, 217 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>, 218 219 // Mingw64 and native Win64 use Win64 CC 220 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>, 221 222 // Otherwise, drop to normal X86-64 CC 223 CCDelegateTo<RetCC_X86_64_C> 224]>; 225 226// This is the return-value convention used for the entire X86 backend. 227def RetCC_X86 : CallingConv<[ 228 229 // Check if this is the Intel OpenCL built-ins calling convention 230 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>, 231 232 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>, 233 CCDelegateTo<RetCC_X86_32> 234]>; 235 236//===----------------------------------------------------------------------===// 237// X86-64 Argument Calling Conventions 238//===----------------------------------------------------------------------===// 239 240def CC_X86_64_C : CallingConv<[ 241 // Handles byval parameters. 242 CCIfByVal<CCPassByVal<8, 8>>, 243 244 // Promote i8/i16 arguments to i32. 245 CCIfType<[i8, i16], CCPromoteToType<i32>>, 246 247 // The 'nest' parameter, if any, is passed in R10. 248 CCIfNest<CCIfSubtarget<"isTarget64BitILP32()", CCAssignToReg<[R10D]>>>, 249 CCIfNest<CCAssignToReg<[R10]>>, 250 251 // The first 6 integer arguments are passed in integer registers. 252 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>, 253 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>, 254 255 // The first 8 MMX vector arguments are passed in XMM registers on Darwin. 256 CCIfType<[x86mmx], 257 CCIfSubtarget<"isTargetDarwin()", 258 CCIfSubtarget<"hasSSE2()", 259 CCPromoteToType<v2i64>>>>, 260 261 // The first 8 FP/Vector arguments are passed in XMM registers. 262 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 263 CCIfSubtarget<"hasSSE1()", 264 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>, 265 266 // The first 8 256-bit vector arguments are passed in YMM registers, unless 267 // this is a vararg function. 268 // FIXME: This isn't precisely correct; the x86-64 ABI document says that 269 // fixed arguments to vararg functions are supposed to be passed in 270 // registers. Actually modeling that would be a lot of work, though. 271 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 272 CCIfSubtarget<"hasFp256()", 273 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3, 274 YMM4, YMM5, YMM6, YMM7]>>>>, 275 276 // The first 8 512-bit vector arguments are passed in ZMM registers. 277 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 278 CCIfSubtarget<"hasAVX512()", 279 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>, 280 281 // Integer/FP values get stored in stack slots that are 8 bytes in size and 282 // 8-byte aligned if there are no more registers to hold them. 283 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>, 284 285 // Long doubles get stack slots whose size and alignment depends on the 286 // subtarget. 287 CCIfType<[f80], CCAssignToStack<0, 0>>, 288 289 // Vectors get 16-byte stack slots that are 16-byte aligned. 290 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>, 291 292 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned. 293 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 294 CCAssignToStack<32, 32>>, 295 296 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 297 CCIfType<[v16i32, v8i64, v16f32, v8f64], 298 CCAssignToStack<64, 64>> 299]>; 300 301// Calling convention used on Win64 302def CC_X86_Win64_C : CallingConv<[ 303 // FIXME: Handle byval stuff. 304 // FIXME: Handle varargs. 305 306 // Promote i8/i16 arguments to i32. 307 CCIfType<[i8, i16], CCPromoteToType<i32>>, 308 309 // The 'nest' parameter, if any, is passed in R10. 310 CCIfNest<CCAssignToReg<[R10]>>, 311 312 // 128 bit vectors are passed by pointer 313 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>, 314 315 316 // 256 bit vectors are passed by pointer 317 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>, 318 319 // 512 bit vectors are passed by pointer 320 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>, 321 322 // The first 4 MMX vector arguments are passed in GPRs. 323 CCIfType<[x86mmx], CCBitConvertToType<i64>>, 324 325 // The first 4 integer arguments are passed in integer registers. 326 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ], 327 [XMM0, XMM1, XMM2, XMM3]>>, 328 329 // Do not pass the sret argument in RCX, the Win64 thiscall calling 330 // convention requires "this" to be passed in RCX. 331 CCIfCC<"CallingConv::X86_ThisCall", 332 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ], 333 [XMM1, XMM2, XMM3]>>>>, 334 335 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ], 336 [XMM0, XMM1, XMM2, XMM3]>>, 337 338 // The first 4 FP/Vector arguments are passed in XMM registers. 339 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 340 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3], 341 [RCX , RDX , R8 , R9 ]>>, 342 343 // Integer/FP values get stored in stack slots that are 8 bytes in size and 344 // 8-byte aligned if there are no more registers to hold them. 345 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>, 346 347 // Long doubles get stack slots whose size and alignment depends on the 348 // subtarget. 349 CCIfType<[f80], CCAssignToStack<0, 0>> 350]>; 351 352def CC_X86_Win64_VectorCall : CallingConv<[ 353 // The first 6 floating point and vector types of 128 bits or less use 354 // XMM0-XMM5. 355 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 356 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5]>>, 357 358 // 256-bit vectors use YMM registers. 359 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 360 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3, YMM4, YMM5]>>, 361 362 // 512-bit vectors use ZMM registers. 363 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 364 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5]>>, 365 366 // Delegate to fastcall to handle integer types. 367 CCDelegateTo<CC_X86_Win64_C> 368]>; 369 370 371def CC_X86_64_GHC : CallingConv<[ 372 // Promote i8/i16/i32 arguments to i64. 373 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 374 375 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim 376 CCIfType<[i64], 377 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>, 378 379 // Pass in STG registers: F1, F2, F3, F4, D1, D2 380 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 381 CCIfSubtarget<"hasSSE1()", 382 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>> 383]>; 384 385def CC_X86_64_HiPE : CallingConv<[ 386 // Promote i8/i16/i32 arguments to i64. 387 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 388 389 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3 390 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>, 391 392 // Integer/FP values get stored in stack slots that are 8 bytes in size and 393 // 8-byte aligned if there are no more registers to hold them. 394 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>> 395]>; 396 397def CC_X86_64_WebKit_JS : CallingConv<[ 398 // Promote i8/i16 arguments to i32. 399 CCIfType<[i8, i16], CCPromoteToType<i32>>, 400 401 // Only the first integer argument is passed in register. 402 CCIfType<[i32], CCAssignToReg<[EAX]>>, 403 CCIfType<[i64], CCAssignToReg<[RAX]>>, 404 405 // The remaining integer arguments are passed on the stack. 32bit integer and 406 // floating-point arguments are aligned to 4 byte and stored in 4 byte slots. 407 // 64bit integer and floating-point arguments are aligned to 8 byte and stored 408 // in 8 byte stack slots. 409 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 410 CCIfType<[i64, f64], CCAssignToStack<8, 8>> 411]>; 412 413// No explicit register is specified for the AnyReg calling convention. The 414// register allocator may assign the arguments to any free register. 415// 416// This calling convention is currently only supported by the stackmap and 417// patchpoint intrinsics. All other uses will result in an assert on Debug 418// builds. On Release builds we fallback to the X86 C calling convention. 419def CC_X86_64_AnyReg : CallingConv<[ 420 CCCustom<"CC_X86_AnyReg_Error"> 421]>; 422 423//===----------------------------------------------------------------------===// 424// X86 C Calling Convention 425//===----------------------------------------------------------------------===// 426 427/// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP 428/// values are spilled on the stack, and the first 4 vector values go in XMM 429/// regs. 430def CC_X86_32_Common : CallingConv<[ 431 // Handles byval parameters. 432 CCIfByVal<CCPassByVal<4, 4>>, 433 434 // The first 3 float or double arguments, if marked 'inreg' and if the call 435 // is not a vararg call and if SSE2 is available, are passed in SSE registers. 436 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64], 437 CCIfSubtarget<"hasSSE2()", 438 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>, 439 440 // The first 3 __m64 vector arguments are passed in mmx registers if the 441 // call is not a vararg call. 442 CCIfNotVarArg<CCIfType<[x86mmx], 443 CCAssignToReg<[MM0, MM1, MM2]>>>, 444 445 // Integer/Float values get stored in stack slots that are 4 bytes in 446 // size and 4-byte aligned. 447 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 448 449 // Doubles get 8-byte slots that are 4-byte aligned. 450 CCIfType<[f64], CCAssignToStack<8, 4>>, 451 452 // Long doubles get slots whose size depends on the subtarget. 453 CCIfType<[f80], CCAssignToStack<0, 4>>, 454 455 // The first 4 SSE vector arguments are passed in XMM registers. 456 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 457 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>, 458 459 // The first 4 AVX 256-bit vector arguments are passed in YMM registers. 460 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 461 CCIfSubtarget<"hasFp256()", 462 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>, 463 464 // The first 4 AVX 512-bit vector arguments are passed in ZMM registers. 465 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 466 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>>, 467 468 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned. 469 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>, 470 471 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned. 472 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 473 CCAssignToStack<32, 32>>, 474 475 // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 476 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 477 CCAssignToStack<64, 64>>, 478 479 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are 480 // passed in the parameter area. 481 CCIfType<[x86mmx], CCAssignToStack<8, 4>>]>; 482 483def CC_X86_32_C : CallingConv<[ 484 // Promote i8/i16 arguments to i32. 485 CCIfType<[i8, i16], CCPromoteToType<i32>>, 486 487 // The 'nest' parameter, if any, is passed in ECX. 488 CCIfNest<CCAssignToReg<[ECX]>>, 489 490 // The first 3 integer arguments, if marked 'inreg' and if the call is not 491 // a vararg call, are passed in integer registers. 492 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>, 493 494 // Otherwise, same as everything else. 495 CCDelegateTo<CC_X86_32_Common> 496]>; 497 498def CC_X86_32_FastCall : CallingConv<[ 499 // Promote i8/i16 arguments to i32. 500 CCIfType<[i8, i16], CCPromoteToType<i32>>, 501 502 // The 'nest' parameter, if any, is passed in EAX. 503 CCIfNest<CCAssignToReg<[EAX]>>, 504 505 // The first 2 integer arguments are passed in ECX/EDX 506 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>, 507 508 // Otherwise, same as everything else. 509 CCDelegateTo<CC_X86_32_Common> 510]>; 511 512def CC_X86_32_VectorCall : CallingConv<[ 513 // The first 6 floating point and vector types of 128 bits or less use 514 // XMM0-XMM5. 515 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 516 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5]>>, 517 518 // 256-bit vectors use YMM registers. 519 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 520 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3, YMM4, YMM5]>>, 521 522 // 512-bit vectors use ZMM registers. 523 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 524 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5]>>, 525 526 // Otherwise, pass it indirectly. 527 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, 528 v32i8, v16i16, v8i32, v4i64, v8f32, v4f64, 529 v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 530 CCCustom<"CC_X86_32_VectorCallIndirect">>, 531 532 // Delegate to fastcall to handle integer types. 533 CCDelegateTo<CC_X86_32_FastCall> 534]>; 535 536def CC_X86_32_ThisCall_Common : CallingConv<[ 537 // The first integer argument is passed in ECX 538 CCIfType<[i32], CCAssignToReg<[ECX]>>, 539 540 // Otherwise, same as everything else. 541 CCDelegateTo<CC_X86_32_Common> 542]>; 543 544def CC_X86_32_ThisCall_Mingw : CallingConv<[ 545 // Promote i8/i16 arguments to i32. 546 CCIfType<[i8, i16], CCPromoteToType<i32>>, 547 548 CCDelegateTo<CC_X86_32_ThisCall_Common> 549]>; 550 551def CC_X86_32_ThisCall_Win : CallingConv<[ 552 // Promote i8/i16 arguments to i32. 553 CCIfType<[i8, i16], CCPromoteToType<i32>>, 554 555 // Pass sret arguments indirectly through stack. 556 CCIfSRet<CCAssignToStack<4, 4>>, 557 558 CCDelegateTo<CC_X86_32_ThisCall_Common> 559]>; 560 561def CC_X86_32_ThisCall : CallingConv<[ 562 CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>, 563 CCDelegateTo<CC_X86_32_ThisCall_Win> 564]>; 565 566def CC_X86_32_FastCC : CallingConv<[ 567 // Handles byval parameters. Note that we can't rely on the delegation 568 // to CC_X86_32_Common for this because that happens after code that 569 // puts arguments in registers. 570 CCIfByVal<CCPassByVal<4, 4>>, 571 572 // Promote i8/i16 arguments to i32. 573 CCIfType<[i8, i16], CCPromoteToType<i32>>, 574 575 // The 'nest' parameter, if any, is passed in EAX. 576 CCIfNest<CCAssignToReg<[EAX]>>, 577 578 // The first 2 integer arguments are passed in ECX/EDX 579 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>, 580 581 // The first 3 float or double arguments, if the call is not a vararg 582 // call and if SSE2 is available, are passed in SSE registers. 583 CCIfNotVarArg<CCIfType<[f32,f64], 584 CCIfSubtarget<"hasSSE2()", 585 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 586 587 // Doubles get 8-byte slots that are 8-byte aligned. 588 CCIfType<[f64], CCAssignToStack<8, 8>>, 589 590 // Otherwise, same as everything else. 591 CCDelegateTo<CC_X86_32_Common> 592]>; 593 594def CC_X86_32_GHC : CallingConv<[ 595 // Promote i8/i16 arguments to i32. 596 CCIfType<[i8, i16], CCPromoteToType<i32>>, 597 598 // Pass in STG registers: Base, Sp, Hp, R1 599 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>> 600]>; 601 602def CC_X86_32_HiPE : CallingConv<[ 603 // Promote i8/i16 arguments to i32. 604 CCIfType<[i8, i16], CCPromoteToType<i32>>, 605 606 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2 607 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>, 608 609 // Integer/Float values get stored in stack slots that are 4 bytes in 610 // size and 4-byte aligned. 611 CCIfType<[i32, f32], CCAssignToStack<4, 4>> 612]>; 613 614// X86-64 Intel OpenCL built-ins calling convention. 615def CC_Intel_OCL_BI : CallingConv<[ 616 617 CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>, 618 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>, 619 620 CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>, 621 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>, 622 623 CCIfType<[i32], CCAssignToStack<4, 4>>, 624 625 // The SSE vector arguments are passed in XMM registers. 626 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], 627 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 628 629 // The 256-bit vector arguments are passed in YMM registers. 630 CCIfType<[v8f32, v4f64, v8i32, v4i64], 631 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>, 632 633 // The 512-bit vector arguments are passed in ZMM registers. 634 CCIfType<[v16f32, v8f64, v16i32, v8i64], 635 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>, 636 637 // Pass masks in mask registers 638 CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>, 639 640 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>, 641 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>, 642 CCDelegateTo<CC_X86_32_C> 643]>; 644 645//===----------------------------------------------------------------------===// 646// X86 Root Argument Calling Conventions 647//===----------------------------------------------------------------------===// 648 649// This is the root argument convention for the X86-32 backend. 650def CC_X86_32 : CallingConv<[ 651 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>, 652 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_32_VectorCall>>, 653 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>, 654 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>, 655 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>, 656 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>, 657 658 // Otherwise, drop to normal X86-32 CC 659 CCDelegateTo<CC_X86_32_C> 660]>; 661 662// This is the root argument convention for the X86-64 backend. 663def CC_X86_64 : CallingConv<[ 664 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>, 665 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>, 666 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<CC_X86_64_WebKit_JS>>, 667 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_X86_64_AnyReg>>, 668 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<CC_X86_Win64_C>>, 669 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>, 670 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win64_VectorCall>>, 671 672 // Mingw64 and native Win64 use Win64 CC 673 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>, 674 675 // Otherwise, drop to normal X86-64 CC 676 CCDelegateTo<CC_X86_64_C> 677]>; 678 679// This is the argument convention used for the entire X86 backend. 680def CC_X86 : CallingConv<[ 681 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>, 682 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>, 683 CCDelegateTo<CC_X86_32> 684]>; 685 686//===----------------------------------------------------------------------===// 687// Callee-saved Registers. 688//===----------------------------------------------------------------------===// 689 690def CSR_NoRegs : CalleeSavedRegs<(add)>; 691 692def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>; 693def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>; 694 695def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>; 696def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>; 697 698def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15, 699 (sequence "XMM%u", 6, 15))>; 700 701// All GPRs - except r11 702def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI, 703 R8, R9, R10, RSP)>; 704 705// All registers - except r11 706def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs, 707 (sequence "XMM%u", 0, 15))>; 708def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs, 709 (sequence "YMM%u", 0, 15))>; 710 711def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10, 712 R11, R12, R13, R14, R15, RBP, 713 (sequence "XMM%u", 0, 15))>; 714 715def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX, RSP, 716 (sequence "XMM%u", 16, 31))>; 717def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, RSP, 718 (sequence "YMM%u", 0, 31)), 719 (sequence "XMM%u", 0, 15))>; 720 721// Standard C + YMM6-15 722def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, 723 R13, R14, R15, 724 (sequence "YMM%u", 6, 15))>; 725 726def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, 727 R12, R13, R14, R15, 728 (sequence "ZMM%u", 6, 21), 729 K4, K5, K6, K7)>; 730//Standard C + XMM 8-15 731def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64, 732 (sequence "XMM%u", 8, 15))>; 733 734//Standard C + YMM 8-15 735def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64, 736 (sequence "YMM%u", 8, 15))>; 737 738def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RDI, RSI, R14, R15, 739 (sequence "ZMM%u", 16, 31), 740 K4, K5, K6, K7)>; 741