1//===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 instruction set, defining the instructions, and 11// properties of the instructions which are needed for code generation, machine 12// code emission, and analysis. 13// 14//===----------------------------------------------------------------------===// 15 16//===----------------------------------------------------------------------===// 17// X86 specific DAG Nodes. 18// 19 20def SDTIntShiftDOp: SDTypeProfile<1, 3, 21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 22 SDTCisInt<0>, SDTCisInt<3>]>; 23 24def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; 25 26def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 27//def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 28 29def SDTX86Cmov : SDTypeProfile<1, 4, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; 32 33// Unary and binary operator instructions that set EFLAGS as a side-effect. 34def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, 35 [SDTCisSameAs<0, 2>, 36 SDTCisInt<0>, SDTCisVT<1, i32>]>; 37 38def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 39 [SDTCisSameAs<0, 2>, 40 SDTCisSameAs<0, 3>, 41 SDTCisInt<0>, SDTCisVT<1, i32>]>; 42 43// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS 44def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 45 [SDTCisSameAs<0, 2>, 46 SDTCisSameAs<0, 3>, 47 SDTCisInt<0>, 48 SDTCisVT<1, i32>, 49 SDTCisVT<4, i32>]>; 50// RES1, RES2, FLAGS = op LHS, RHS 51def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2, 52 [SDTCisSameAs<0, 1>, 53 SDTCisSameAs<0, 2>, 54 SDTCisSameAs<0, 3>, 55 SDTCisInt<0>, SDTCisVT<1, i32>]>; 56def SDTX86BrCond : SDTypeProfile<0, 3, 57 [SDTCisVT<0, OtherVT>, 58 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 59 60def SDTX86SetCC : SDTypeProfile<1, 2, 61 [SDTCisVT<0, i8>, 62 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 63def SDTX86SetCC_C : SDTypeProfile<1, 2, 64 [SDTCisInt<0>, 65 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 66 67def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>; 68 69def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>; 70 71def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, 72 SDTCisVT<2, i8>]>; 73def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 74 75def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>, 76 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>; 77def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>; 78 79def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 80def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, 81 SDTCisVT<1, i32>]>; 82 83def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 84 85def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, 86 SDTCisVT<1, iPTR>, 87 SDTCisVT<2, iPTR>]>; 88 89def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>, 90 SDTCisPtrTy<1>, 91 SDTCisVT<2, i32>, 92 SDTCisVT<3, i8>, 93 SDTCisVT<4, i32>]>; 94 95def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; 96 97def SDTX86Void : SDTypeProfile<0, 0, []>; 98 99def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 100 101def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 102 103def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 104 105def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 106 107def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 108 109def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>; 110 111def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 112 113def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 114 115def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>; 116 117def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER, 118 [SDNPHasChain,SDNPSideEffect]>; 119def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER, 120 [SDNPHasChain]>; 121def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER, 122 [SDNPHasChain]>; 123def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER, 124 [SDNPHasChain]>; 125 126 127def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; 128def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; 129def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; 130def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; 131 132def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; 133def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; 134 135def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; 136def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, 137 [SDNPHasChain]>; 138def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; 139def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; 140 141def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>; 142 143def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, 144 [SDNPHasChain, SDNPSideEffect]>; 145 146def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand, 147 [SDNPHasChain, SDNPSideEffect]>; 148 149def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, 150 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 151 SDNPMayLoad, SDNPMemOperand]>; 152def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair, 153 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 154 SDNPMayLoad, SDNPMemOperand]>; 155def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair, 156 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 157 SDNPMayLoad, SDNPMemOperand]>; 158 159def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, 160 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 161 162def X86vastart_save_xmm_regs : 163 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", 164 SDT_X86VASTART_SAVE_XMM_REGS, 165 [SDNPHasChain, SDNPVariadic]>; 166def X86vaarg64 : 167 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64, 168 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 169 SDNPMemOperand]>; 170def X86callseq_start : 171 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, 172 [SDNPHasChain, SDNPOutGlue]>; 173def X86callseq_end : 174 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, 175 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 176 177def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, 178 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 179 SDNPVariadic]>; 180 181def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, 182 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>; 183def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, 184 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 185 SDNPMayLoad]>; 186 187def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void, 188 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 189def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void, 190 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 191def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void, 192 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 193 194def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; 195def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; 196 197def X86RecoverFrameAlloc : SDNode<"ISD::FRAME_ALLOC_RECOVER", 198 SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 199 SDTCisInt<1>]>>; 200 201def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, 202 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 203 204def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR, 205 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 206 207def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, 208 [SDNPHasChain]>; 209 210def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP", 211 SDTypeProfile<1, 1, [SDTCisInt<0>, 212 SDTCisPtrTy<1>]>, 213 [SDNPHasChain, SDNPSideEffect]>; 214def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP", 215 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 216 [SDNPHasChain, SDNPSideEffect]>; 217 218def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, 219 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 220 221def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, 222 [SDNPCommutative]>; 223def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; 224def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, 225 [SDNPCommutative]>; 226def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags, 227 [SDNPCommutative]>; 228def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>; 229def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>; 230 231def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; 232def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; 233def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, 234 [SDNPCommutative]>; 235def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, 236 [SDNPCommutative]>; 237def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, 238 [SDNPCommutative]>; 239 240def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>; 241 242def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; 243 244def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void, 245 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 246 247def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, 248 [SDNPHasChain]>; 249 250def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, 251 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 252 253def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL, 254 [SDNPHasChain, SDNPOutGlue]>; 255 256//===----------------------------------------------------------------------===// 257// X86 Operand Definitions. 258// 259 260// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for 261// the index operand of an address, to conform to x86 encoding restrictions. 262def ptr_rc_nosp : PointerLikeRegClass<1>; 263 264// *mem - Operand definitions for the funky X86 addressing mode operands. 265// 266def X86MemAsmOperand : AsmOperandClass { 267 let Name = "Mem"; 268} 269let RenderMethod = "addMemOperands" in { 270 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; } 271 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; } 272 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; } 273 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; } 274 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; } 275 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; } 276 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; } 277 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; } 278 // Gather mem operands 279 def X86MemVX32Operand : AsmOperandClass { let Name = "MemVX32"; } 280 def X86MemVY32Operand : AsmOperandClass { let Name = "MemVY32"; } 281 def X86MemVZ32Operand : AsmOperandClass { let Name = "MemVZ32"; } 282 def X86MemVX64Operand : AsmOperandClass { let Name = "MemVX64"; } 283 def X86MemVY64Operand : AsmOperandClass { let Name = "MemVY64"; } 284 def X86MemVZ64Operand : AsmOperandClass { let Name = "MemVZ64"; } 285} 286 287def X86AbsMemAsmOperand : AsmOperandClass { 288 let Name = "AbsMem"; 289 let SuperClasses = [X86MemAsmOperand]; 290} 291 292class X86MemOperand<string printMethod, 293 AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> { 294 let PrintMethod = printMethod; 295 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); 296 let ParserMatchClass = parserMatchClass; 297 let OperandType = "OPERAND_MEMORY"; 298} 299 300// Gather mem operands 301class X86VMemOperand<RegisterClass RC, string printMethod, 302 AsmOperandClass parserMatchClass> 303 : X86MemOperand<printMethod, parserMatchClass> { 304 let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, i8imm); 305} 306 307def anymem : X86MemOperand<"printanymem">; 308 309def opaque32mem : X86MemOperand<"printopaquemem">; 310def opaque48mem : X86MemOperand<"printopaquemem">; 311def opaque80mem : X86MemOperand<"printopaquemem">; 312def opaque512mem : X86MemOperand<"printopaquemem">; 313 314def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>; 315def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>; 316def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>; 317def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>; 318def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>; 319def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>; 320def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>; 321def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>; 322def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>; 323def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>; 324def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>; 325def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>; 326def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>; 327 328def v512mem : X86VMemOperand<VR512, "printf512mem", X86Mem512AsmOperand>; 329 330// Gather mem operands 331def vx32mem : X86VMemOperand<VR128, "printi32mem", X86MemVX32Operand>; 332def vy32mem : X86VMemOperand<VR256, "printi32mem", X86MemVY32Operand>; 333def vx64mem : X86VMemOperand<VR128, "printi64mem", X86MemVX64Operand>; 334def vy64mem : X86VMemOperand<VR256, "printi64mem", X86MemVY64Operand>; 335def vy64xmem : X86VMemOperand<VR256X, "printi64mem", X86MemVY64Operand>; 336def vz32mem : X86VMemOperand<VR512, "printi32mem", X86MemVZ32Operand>; 337def vz64mem : X86VMemOperand<VR512, "printi64mem", X86MemVZ64Operand>; 338 339// A version of i8mem for use on x86-64 that uses GR64_NOREX instead of 340// plain GR64, so that it doesn't potentially require a REX prefix. 341def i8mem_NOREX : Operand<i64> { 342 let PrintMethod = "printi8mem"; 343 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm); 344 let ParserMatchClass = X86Mem8AsmOperand; 345 let OperandType = "OPERAND_MEMORY"; 346} 347 348// GPRs available for tailcall. 349// It represents GR32_TC, GR64_TC or GR64_TCW64. 350def ptr_rc_tailcall : PointerLikeRegClass<2>; 351 352// Special i32mem for addresses of load folding tail calls. These are not 353// allowed to use callee-saved registers since they must be scheduled 354// after callee-saved register are popped. 355def i32mem_TC : Operand<i32> { 356 let PrintMethod = "printi32mem"; 357 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall, 358 i32imm, i8imm); 359 let ParserMatchClass = X86Mem32AsmOperand; 360 let OperandType = "OPERAND_MEMORY"; 361} 362 363// Special i64mem for addresses of load folding tail calls. These are not 364// allowed to use callee-saved registers since they must be scheduled 365// after callee-saved register are popped. 366def i64mem_TC : Operand<i64> { 367 let PrintMethod = "printi64mem"; 368 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, 369 ptr_rc_tailcall, i32imm, i8imm); 370 let ParserMatchClass = X86Mem64AsmOperand; 371 let OperandType = "OPERAND_MEMORY"; 372} 373 374let OperandType = "OPERAND_PCREL", 375 ParserMatchClass = X86AbsMemAsmOperand, 376 PrintMethod = "printPCRelImm" in { 377def i32imm_pcrel : Operand<i32>; 378def i16imm_pcrel : Operand<i16>; 379 380// Branch targets have OtherVT type and print as pc-relative values. 381def brtarget : Operand<OtherVT>; 382def brtarget8 : Operand<OtherVT>; 383 384} 385 386// Special parser to detect 16-bit mode to select 16-bit displacement. 387def X86AbsMem16AsmOperand : AsmOperandClass { 388 let Name = "AbsMem16"; 389 let RenderMethod = "addAbsMemOperands"; 390 let SuperClasses = [X86AbsMemAsmOperand]; 391} 392 393// Branch targets have OtherVT type and print as pc-relative values. 394let OperandType = "OPERAND_PCREL", 395 PrintMethod = "printPCRelImm" in { 396let ParserMatchClass = X86AbsMem16AsmOperand in 397 def brtarget16 : Operand<OtherVT>; 398let ParserMatchClass = X86AbsMemAsmOperand in 399 def brtarget32 : Operand<OtherVT>; 400} 401 402let RenderMethod = "addSrcIdxOperands" in { 403 def X86SrcIdx8Operand : AsmOperandClass { 404 let Name = "SrcIdx8"; 405 let SuperClasses = [X86Mem8AsmOperand]; 406 } 407 def X86SrcIdx16Operand : AsmOperandClass { 408 let Name = "SrcIdx16"; 409 let SuperClasses = [X86Mem16AsmOperand]; 410 } 411 def X86SrcIdx32Operand : AsmOperandClass { 412 let Name = "SrcIdx32"; 413 let SuperClasses = [X86Mem32AsmOperand]; 414 } 415 def X86SrcIdx64Operand : AsmOperandClass { 416 let Name = "SrcIdx64"; 417 let SuperClasses = [X86Mem64AsmOperand]; 418 } 419} // RenderMethod = "addSrcIdxOperands" 420 421let RenderMethod = "addDstIdxOperands" in { 422 def X86DstIdx8Operand : AsmOperandClass { 423 let Name = "DstIdx8"; 424 let SuperClasses = [X86Mem8AsmOperand]; 425 } 426 def X86DstIdx16Operand : AsmOperandClass { 427 let Name = "DstIdx16"; 428 let SuperClasses = [X86Mem16AsmOperand]; 429 } 430 def X86DstIdx32Operand : AsmOperandClass { 431 let Name = "DstIdx32"; 432 let SuperClasses = [X86Mem32AsmOperand]; 433 } 434 def X86DstIdx64Operand : AsmOperandClass { 435 let Name = "DstIdx64"; 436 let SuperClasses = [X86Mem64AsmOperand]; 437 } 438} // RenderMethod = "addDstIdxOperands" 439 440let RenderMethod = "addMemOffsOperands" in { 441 def X86MemOffs16_8AsmOperand : AsmOperandClass { 442 let Name = "MemOffs16_8"; 443 let SuperClasses = [X86Mem8AsmOperand]; 444 } 445 def X86MemOffs16_16AsmOperand : AsmOperandClass { 446 let Name = "MemOffs16_16"; 447 let SuperClasses = [X86Mem16AsmOperand]; 448 } 449 def X86MemOffs16_32AsmOperand : AsmOperandClass { 450 let Name = "MemOffs16_32"; 451 let SuperClasses = [X86Mem32AsmOperand]; 452 } 453 def X86MemOffs32_8AsmOperand : AsmOperandClass { 454 let Name = "MemOffs32_8"; 455 let SuperClasses = [X86Mem8AsmOperand]; 456 } 457 def X86MemOffs32_16AsmOperand : AsmOperandClass { 458 let Name = "MemOffs32_16"; 459 let SuperClasses = [X86Mem16AsmOperand]; 460 } 461 def X86MemOffs32_32AsmOperand : AsmOperandClass { 462 let Name = "MemOffs32_32"; 463 let SuperClasses = [X86Mem32AsmOperand]; 464 } 465 def X86MemOffs32_64AsmOperand : AsmOperandClass { 466 let Name = "MemOffs32_64"; 467 let SuperClasses = [X86Mem64AsmOperand]; 468 } 469 def X86MemOffs64_8AsmOperand : AsmOperandClass { 470 let Name = "MemOffs64_8"; 471 let SuperClasses = [X86Mem8AsmOperand]; 472 } 473 def X86MemOffs64_16AsmOperand : AsmOperandClass { 474 let Name = "MemOffs64_16"; 475 let SuperClasses = [X86Mem16AsmOperand]; 476 } 477 def X86MemOffs64_32AsmOperand : AsmOperandClass { 478 let Name = "MemOffs64_32"; 479 let SuperClasses = [X86Mem32AsmOperand]; 480 } 481 def X86MemOffs64_64AsmOperand : AsmOperandClass { 482 let Name = "MemOffs64_64"; 483 let SuperClasses = [X86Mem64AsmOperand]; 484 } 485} // RenderMethod = "addMemOffsOperands" 486 487class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass> 488 : X86MemOperand<printMethod, parserMatchClass> { 489 let MIOperandInfo = (ops ptr_rc, i8imm); 490} 491 492class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass> 493 : X86MemOperand<printMethod, parserMatchClass> { 494 let MIOperandInfo = (ops ptr_rc); 495} 496 497def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>; 498def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>; 499def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>; 500def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>; 501def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>; 502def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>; 503def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>; 504def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>; 505 506class X86MemOffsOperand<Operand immOperand, string printMethod, 507 AsmOperandClass parserMatchClass> 508 : X86MemOperand<printMethod, parserMatchClass> { 509 let MIOperandInfo = (ops immOperand, i8imm); 510} 511 512def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8", 513 X86MemOffs16_8AsmOperand>; 514def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16", 515 X86MemOffs16_16AsmOperand>; 516def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32", 517 X86MemOffs16_32AsmOperand>; 518def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8", 519 X86MemOffs32_8AsmOperand>; 520def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16", 521 X86MemOffs32_16AsmOperand>; 522def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32", 523 X86MemOffs32_32AsmOperand>; 524def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64", 525 X86MemOffs32_64AsmOperand>; 526def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8", 527 X86MemOffs64_8AsmOperand>; 528def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16", 529 X86MemOffs64_16AsmOperand>; 530def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32", 531 X86MemOffs64_32AsmOperand>; 532def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64", 533 X86MemOffs64_64AsmOperand>; 534 535def SSECC : Operand<i8> { 536 let PrintMethod = "printSSEAVXCC"; 537 let OperandType = "OPERAND_IMMEDIATE"; 538} 539 540def i8immZExt3 : ImmLeaf<i8, [{ 541 return Imm >= 0 && Imm < 8; 542}]>; 543 544def AVXCC : Operand<i8> { 545 let PrintMethod = "printSSEAVXCC"; 546 let OperandType = "OPERAND_IMMEDIATE"; 547} 548 549def i8immZExt5 : ImmLeaf<i8, [{ 550 return Imm >= 0 && Imm < 32; 551}]>; 552 553def AVX512ICC : Operand<i8> { 554 let PrintMethod = "printSSEAVXCC"; 555 let OperandType = "OPERAND_IMMEDIATE"; 556} 557 558def XOPCC : Operand<i8> { 559 let PrintMethod = "printXOPCC"; 560 let OperandType = "OPERAND_IMMEDIATE"; 561} 562 563class ImmSExtAsmOperandClass : AsmOperandClass { 564 let SuperClasses = [ImmAsmOperand]; 565 let RenderMethod = "addImmOperands"; 566} 567 568def X86GR32orGR64AsmOperand : AsmOperandClass { 569 let Name = "GR32orGR64"; 570} 571 572def GR32orGR64 : RegisterOperand<GR32> { 573 let ParserMatchClass = X86GR32orGR64AsmOperand; 574} 575def AVX512RCOperand : AsmOperandClass { 576 let Name = "AVX512RC"; 577} 578def AVX512RC : Operand<i32> { 579 let PrintMethod = "printRoundingControl"; 580 let OperandType = "OPERAND_IMMEDIATE"; 581 let ParserMatchClass = AVX512RCOperand; 582} 583 584// Sign-extended immediate classes. We don't need to define the full lattice 585// here because there is no instruction with an ambiguity between ImmSExti64i32 586// and ImmSExti32i8. 587// 588// The strange ranges come from the fact that the assembler always works with 589// 64-bit immediates, but for a 16-bit target value we want to accept both "-1" 590// (which will be a -1ULL), and "0xFF" (-1 in 16-bits). 591 592// [0, 0x7FFFFFFF] | 593// [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] 594def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { 595 let Name = "ImmSExti64i32"; 596} 597 598// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | 599// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 600def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { 601 let Name = "ImmSExti16i8"; 602 let SuperClasses = [ImmSExti64i32AsmOperand]; 603} 604 605// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | 606// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 607def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { 608 let Name = "ImmSExti32i8"; 609} 610 611// [0, 0x0000007F] | 612// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 613def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { 614 let Name = "ImmSExti64i8"; 615 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, 616 ImmSExti64i32AsmOperand]; 617} 618 619// Unsigned immediate used by SSE/AVX instructions 620// [0, 0xFF] 621// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 622def ImmUnsignedi8AsmOperand : AsmOperandClass { 623 let Name = "ImmUnsignedi8"; 624 let RenderMethod = "addImmOperands"; 625} 626 627// A couple of more descriptive operand definitions. 628// 16-bits but only 8 bits are significant. 629def i16i8imm : Operand<i16> { 630 let ParserMatchClass = ImmSExti16i8AsmOperand; 631 let OperandType = "OPERAND_IMMEDIATE"; 632} 633// 32-bits but only 8 bits are significant. 634def i32i8imm : Operand<i32> { 635 let ParserMatchClass = ImmSExti32i8AsmOperand; 636 let OperandType = "OPERAND_IMMEDIATE"; 637} 638 639// 64-bits but only 32 bits are significant. 640def i64i32imm : Operand<i64> { 641 let ParserMatchClass = ImmSExti64i32AsmOperand; 642 let OperandType = "OPERAND_IMMEDIATE"; 643} 644 645// 64-bits but only 8 bits are significant. 646def i64i8imm : Operand<i64> { 647 let ParserMatchClass = ImmSExti64i8AsmOperand; 648 let OperandType = "OPERAND_IMMEDIATE"; 649} 650 651// Unsigned 8-bit immediate used by SSE/AVX instructions. 652def u8imm : Operand<i8> { 653 let PrintMethod = "printU8Imm"; 654 let ParserMatchClass = ImmUnsignedi8AsmOperand; 655 let OperandType = "OPERAND_IMMEDIATE"; 656} 657 658// 32-bit immediate but only 8-bits are significant and they are unsigned. 659// Used by some SSE/AVX instructions that use intrinsics. 660def i32u8imm : Operand<i32> { 661 let PrintMethod = "printU8Imm"; 662 let ParserMatchClass = ImmUnsignedi8AsmOperand; 663 let OperandType = "OPERAND_IMMEDIATE"; 664} 665 666// 64-bits but only 32 bits are significant, and those bits are treated as being 667// pc relative. 668def i64i32imm_pcrel : Operand<i64> { 669 let PrintMethod = "printPCRelImm"; 670 let ParserMatchClass = X86AbsMemAsmOperand; 671 let OperandType = "OPERAND_PCREL"; 672} 673 674def lea64_32mem : Operand<i32> { 675 let PrintMethod = "printanymem"; 676 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm); 677 let ParserMatchClass = X86MemAsmOperand; 678} 679 680// Memory operands that use 64-bit pointers in both ILP32 and LP64. 681def lea64mem : Operand<i64> { 682 let PrintMethod = "printanymem"; 683 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm); 684 let ParserMatchClass = X86MemAsmOperand; 685} 686 687 688//===----------------------------------------------------------------------===// 689// X86 Complex Pattern Definitions. 690// 691 692// Define X86 specific addressing mode. 693def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>; 694def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr", 695 [add, sub, mul, X86mul_imm, shl, or, frameindex], 696 []>; 697// In 64-bit mode 32-bit LEAs can use RIP-relative addressing. 698def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr", 699 [add, sub, mul, X86mul_imm, shl, or, 700 frameindex, X86WrapperRIP], 701 []>; 702 703def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr", 704 [tglobaltlsaddr], []>; 705 706def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr", 707 [tglobaltlsaddr], []>; 708 709def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr", 710 [add, sub, mul, X86mul_imm, shl, or, frameindex, 711 X86WrapperRIP], []>; 712 713def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", 714 [tglobaltlsaddr], []>; 715 716def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", 717 [tglobaltlsaddr], []>; 718 719//===----------------------------------------------------------------------===// 720// X86 Instruction Predicate Definitions. 721def HasCMov : Predicate<"Subtarget->hasCMov()">; 722def NoCMov : Predicate<"!Subtarget->hasCMov()">; 723 724def HasMMX : Predicate<"Subtarget->hasMMX()">; 725def Has3DNow : Predicate<"Subtarget->has3DNow()">; 726def Has3DNowA : Predicate<"Subtarget->has3DNowA()">; 727def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; 728def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">; 729def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; 730def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">; 731def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; 732def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">; 733def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; 734def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">; 735def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; 736def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">; 737def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">; 738def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; 739def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">; 740def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; 741def HasAVX : Predicate<"Subtarget->hasAVX()">; 742def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; 743def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">; 744def HasAVX512 : Predicate<"Subtarget->hasAVX512()">, 745 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">; 746def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">; 747def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">; 748def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">; 749def HasCDI : Predicate<"Subtarget->hasCDI()">, 750 AssemblerPredicate<"FeatureCDI", "AVX-512 CD ISA">; 751def HasPFI : Predicate<"Subtarget->hasPFI()">, 752 AssemblerPredicate<"FeaturePFI", "AVX-512 PF ISA">; 753def HasERI : Predicate<"Subtarget->hasERI()">, 754 AssemblerPredicate<"FeatureERI", "AVX-512 ER ISA">; 755def HasDQI : Predicate<"Subtarget->hasDQI()">, 756 AssemblerPredicate<"FeatureDQI", "AVX-512 DQ ISA">; 757def NoDQI : Predicate<"!Subtarget->hasDQI()">; 758def HasBWI : Predicate<"Subtarget->hasBWI()">, 759 AssemblerPredicate<"FeatureBWI", "AVX-512 BW ISA">; 760def HasVLX : Predicate<"Subtarget->hasVLX()">, 761 AssemblerPredicate<"FeatureVLX", "AVX-512 VL ISA">; 762def NoVLX : Predicate<"!Subtarget->hasVLX()">; 763 764def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; 765def HasAES : Predicate<"Subtarget->hasAES()">; 766def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">; 767def HasFMA : Predicate<"Subtarget->hasFMA()">; 768def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">; 769def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; 770def HasXOP : Predicate<"Subtarget->hasXOP()">; 771def HasTBM : Predicate<"Subtarget->hasTBM()">; 772def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; 773def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; 774def HasF16C : Predicate<"Subtarget->hasF16C()">; 775def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">; 776def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">; 777def HasBMI : Predicate<"Subtarget->hasBMI()">; 778def HasBMI2 : Predicate<"Subtarget->hasBMI2()">; 779def HasRTM : Predicate<"Subtarget->hasRTM()">; 780def HasHLE : Predicate<"Subtarget->hasHLE()">; 781def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">; 782def HasADX : Predicate<"Subtarget->hasADX()">; 783def HasSHA : Predicate<"Subtarget->hasSHA()">; 784def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">; 785def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">; 786def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">; 787def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; 788def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; 789def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">; 790def Not64BitMode : Predicate<"!Subtarget->is64Bit()">, 791 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">; 792def In64BitMode : Predicate<"Subtarget->is64Bit()">, 793 AssemblerPredicate<"Mode64Bit", "64-bit mode">; 794def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">; 795def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">; 796def In16BitMode : Predicate<"Subtarget->is16Bit()">, 797 AssemblerPredicate<"Mode16Bit", "16-bit mode">; 798def Not16BitMode : Predicate<"!Subtarget->is16Bit()">, 799 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">; 800def In32BitMode : Predicate<"Subtarget->is32Bit()">, 801 AssemblerPredicate<"Mode32Bit", "32-bit mode">; 802def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; 803def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; 804def IsPS4 : Predicate<"Subtarget->isTargetPS4()">; 805def NotPS4 : Predicate<"!Subtarget->isTargetPS4()">; 806def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 807def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; 808def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; 809def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; 810def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&" 811 "TM.getCodeModel() != CodeModel::Kernel">; 812def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" 813 "TM.getCodeModel() == CodeModel::Kernel">; 814def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; 815def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">; 816def OptForSize : Predicate<"OptForSize">; 817def OptForSpeed : Predicate<"!OptForSize">; 818def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">; 819def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">; 820def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">; 821def NotSlowIncDec : Predicate<"!Subtarget->slowIncDec()">; 822def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">; 823 824//===----------------------------------------------------------------------===// 825// X86 Instruction Format Definitions. 826// 827 828include "X86InstrFormats.td" 829 830//===----------------------------------------------------------------------===// 831// Pattern fragments. 832// 833 834// X86 specific condition code. These correspond to CondCode in 835// X86InstrInfo.h. They must be kept in synch. 836def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE 837def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC 838def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C 839def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA 840def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z 841def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE 842def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL 843def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE 844def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG 845def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ 846def X86_COND_NO : PatLeaf<(i8 10)>; 847def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO 848def X86_COND_NS : PatLeaf<(i8 12)>; 849def X86_COND_O : PatLeaf<(i8 13)>; 850def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE 851def X86_COND_S : PatLeaf<(i8 15)>; 852 853// Predicate used to help when pattern matching LZCNT/TZCNT. 854def X86_COND_E_OR_NE : ImmLeaf<i8, [{ 855 return (Imm == X86::COND_E) || (Imm == X86::COND_NE); 856}]>; 857 858 859def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>; 860def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>; 861def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>; 862 863 864def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>; 865 866 867// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit 868// unsigned field. 869def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>; 870 871def i64immZExt32SExt8 : ImmLeaf<i64, [{ 872 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm; 873}]>; 874 875// Helper fragments for loads. 876// It's always safe to treat a anyext i16 load as a i32 load if the i16 is 877// known to be 32-bit aligned or better. Ditto for i8 to i16. 878def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ 879 LoadSDNode *LD = cast<LoadSDNode>(N); 880 ISD::LoadExtType ExtType = LD->getExtensionType(); 881 if (ExtType == ISD::NON_EXTLOAD) 882 return true; 883 if (ExtType == ISD::EXTLOAD) 884 return LD->getAlignment() >= 2 && !LD->isVolatile(); 885 return false; 886}]>; 887 888def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{ 889 LoadSDNode *LD = cast<LoadSDNode>(N); 890 ISD::LoadExtType ExtType = LD->getExtensionType(); 891 if (ExtType == ISD::EXTLOAD) 892 return LD->getAlignment() >= 2 && !LD->isVolatile(); 893 return false; 894}]>; 895 896def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ 897 LoadSDNode *LD = cast<LoadSDNode>(N); 898 ISD::LoadExtType ExtType = LD->getExtensionType(); 899 if (ExtType == ISD::NON_EXTLOAD) 900 return true; 901 if (ExtType == ISD::EXTLOAD) 902 return LD->getAlignment() >= 4 && !LD->isVolatile(); 903 return false; 904}]>; 905 906def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>; 907def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; 908def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; 909def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; 910def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; 911 912def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; 913def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; 914def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; 915def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; 916def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; 917def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; 918 919def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; 920def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; 921def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; 922def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; 923def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; 924def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; 925def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; 926def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; 927def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; 928def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; 929 930def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; 931def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; 932def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; 933def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; 934def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; 935def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; 936def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; 937def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; 938def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; 939def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; 940 941 942// An 'and' node with a single use. 943def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 944 return N->hasOneUse(); 945}]>; 946// An 'srl' node with a single use. 947def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ 948 return N->hasOneUse(); 949}]>; 950// An 'trunc' node with a single use. 951def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ 952 return N->hasOneUse(); 953}]>; 954 955//===----------------------------------------------------------------------===// 956// Instruction list. 957// 958 959// Nop 960let hasSideEffects = 0, SchedRW = [WriteZero] in { 961 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>; 962 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero), 963 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16; 964 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero), 965 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32; 966} 967 968 969// Constructing a stack frame. 970def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), 971 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>; 972 973let SchedRW = [WriteALU] in { 974let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in 975def LEAVE : I<0xC9, RawFrm, 976 (outs), (ins), "leave", [], IIC_LEAVE>, 977 Requires<[Not64BitMode]>; 978 979let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in 980def LEAVE64 : I<0xC9, RawFrm, 981 (outs), (ins), "leave", [], IIC_LEAVE>, 982 Requires<[In64BitMode]>; 983} // SchedRW 984 985//===----------------------------------------------------------------------===// 986// Miscellaneous Instructions. 987// 988 989let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in { 990let mayLoad = 1, SchedRW = [WriteLoad] in { 991def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [], 992 IIC_POP_REG16>, OpSize16; 993def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [], 994 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>; 995def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [], 996 IIC_POP_REG>, OpSize16; 997def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [], 998 IIC_POP_MEM>, OpSize16; 999def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [], 1000 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>; 1001def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [], 1002 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>; 1003} // mayLoad, SchedRW 1004 1005let mayStore = 1, SchedRW = [WriteStore] in { 1006def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[], 1007 IIC_PUSH_REG>, OpSize16; 1008def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[], 1009 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>; 1010def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[], 1011 IIC_PUSH_REG>, OpSize16; 1012def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[], 1013 IIC_PUSH_MEM>, OpSize16; 1014def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[], 1015 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>; 1016def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[], 1017 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>; 1018 1019def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm), 1020 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16, 1021 Requires<[Not64BitMode]>; 1022def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), 1023 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32, 1024 Requires<[Not64BitMode]>; 1025def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), 1026 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16, 1027 Requires<[Not64BitMode]>; 1028def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), 1029 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32, 1030 Requires<[Not64BitMode]>; 1031} // mayStore, SchedRW 1032} 1033 1034let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0, 1035 SchedRW = [WriteLoad] in { 1036def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, 1037 OpSize16; 1038def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>, 1039 OpSize32, Requires<[Not64BitMode]>; 1040} 1041 1042let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0, 1043 SchedRW = [WriteStore] in { 1044def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>, 1045 OpSize16; 1046def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>, 1047 OpSize32, Requires<[Not64BitMode]>; 1048} 1049 1050let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in { 1051let mayLoad = 1, SchedRW = [WriteLoad] in { 1052def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [], 1053 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>; 1054def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [], 1055 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>; 1056def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [], 1057 IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>; 1058} // mayLoad, SchedRW 1059let mayStore = 1, SchedRW = [WriteStore] in { 1060def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [], 1061 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>; 1062def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [], 1063 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>; 1064def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [], 1065 IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>; 1066} // mayStore, SchedRW 1067} 1068 1069let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1, 1070 SchedRW = [WriteStore] in { 1071def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), 1072 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>; 1073def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), 1074 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16, 1075 Requires<[In64BitMode]>; 1076def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm), 1077 "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32, 1078 Requires<[In64BitMode]>; 1079} 1080 1081let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in 1082def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>, 1083 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>; 1084let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in 1085def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>, 1086 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>; 1087 1088let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], 1089 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in { 1090def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>, 1091 OpSize32, Requires<[Not64BitMode]>; 1092def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>, 1093 OpSize16, Requires<[Not64BitMode]>; 1094} 1095let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], 1096 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in { 1097def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>, 1098 OpSize32, Requires<[Not64BitMode]>; 1099def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>, 1100 OpSize16, Requires<[Not64BitMode]>; 1101} 1102 1103let Constraints = "$src = $dst", SchedRW = [WriteALU] in { 1104// GR32 = bswap GR32 1105def BSWAP32r : I<0xC8, AddRegFrm, 1106 (outs GR32:$dst), (ins GR32:$src), 1107 "bswap{l}\t$dst", 1108 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB; 1109 1110def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), 1111 "bswap{q}\t$dst", 1112 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB; 1113} // Constraints = "$src = $dst", SchedRW 1114 1115// Bit scan instructions. 1116let Defs = [EFLAGS] in { 1117def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1118 "bsf{w}\t{$src, $dst|$dst, $src}", 1119 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))], 1120 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>; 1121def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1122 "bsf{w}\t{$src, $dst|$dst, $src}", 1123 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))], 1124 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>; 1125def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1126 "bsf{l}\t{$src, $dst|$dst, $src}", 1127 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))], 1128 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>; 1129def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1130 "bsf{l}\t{$src, $dst|$dst, $src}", 1131 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))], 1132 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>; 1133def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1134 "bsf{q}\t{$src, $dst|$dst, $src}", 1135 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))], 1136 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>; 1137def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1138 "bsf{q}\t{$src, $dst|$dst, $src}", 1139 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))], 1140 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>; 1141 1142def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1143 "bsr{w}\t{$src, $dst|$dst, $src}", 1144 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))], 1145 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>; 1146def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1147 "bsr{w}\t{$src, $dst|$dst, $src}", 1148 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))], 1149 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>; 1150def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1151 "bsr{l}\t{$src, $dst|$dst, $src}", 1152 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))], 1153 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>; 1154def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1155 "bsr{l}\t{$src, $dst|$dst, $src}", 1156 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))], 1157 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>; 1158def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1159 "bsr{q}\t{$src, $dst|$dst, $src}", 1160 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], 1161 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>; 1162def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1163 "bsr{q}\t{$src, $dst|$dst, $src}", 1164 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))], 1165 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>; 1166} // Defs = [EFLAGS] 1167 1168let SchedRW = [WriteMicrocoded] in { 1169// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1170let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in { 1171def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src), 1172 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>; 1173def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src), 1174 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16; 1175def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src), 1176 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32; 1177def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src), 1178 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>; 1179} 1180 1181// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1182let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in 1183def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins), 1184 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>; 1185let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in 1186def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins), 1187 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16; 1188let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in 1189def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins), 1190 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32; 1191let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in 1192def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins), 1193 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>; 1194 1195// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1196let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in 1197def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst), 1198 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>; 1199let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in 1200def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst), 1201 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16; 1202let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in 1203def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst), 1204 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32; 1205let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in 1206def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst), 1207 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>; 1208 1209// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1210let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in { 1211def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), 1212 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>; 1213def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), 1214 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16; 1215def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), 1216 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32; 1217def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), 1218 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>; 1219} 1220} // SchedRW 1221 1222//===----------------------------------------------------------------------===// 1223// Move Instructions. 1224// 1225let SchedRW = [WriteMove] in { 1226let hasSideEffects = 0 in { 1227def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), 1228 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1229def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1230 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16; 1231def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1232 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32; 1233def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1234 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1235} 1236 1237let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 1238def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), 1239 "mov{b}\t{$src, $dst|$dst, $src}", 1240 [(set GR8:$dst, imm:$src)], IIC_MOV>; 1241def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), 1242 "mov{w}\t{$src, $dst|$dst, $src}", 1243 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16; 1244def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), 1245 "mov{l}\t{$src, $dst|$dst, $src}", 1246 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32; 1247def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), 1248 "mov{q}\t{$src, $dst|$dst, $src}", 1249 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>; 1250} 1251let isReMaterializable = 1 in { 1252def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), 1253 "movabs{q}\t{$src, $dst|$dst, $src}", 1254 [(set GR64:$dst, imm:$src)], IIC_MOV>; 1255} 1256 1257// Longer forms that use a ModR/M byte. Needed for disassembler 1258let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 1259def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src), 1260 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1261def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src), 1262 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16; 1263def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src), 1264 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32; 1265} 1266} // SchedRW 1267 1268let SchedRW = [WriteStore] in { 1269def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), 1270 "mov{b}\t{$src, $dst|$dst, $src}", 1271 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>; 1272def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), 1273 "mov{w}\t{$src, $dst|$dst, $src}", 1274 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16; 1275def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), 1276 "mov{l}\t{$src, $dst|$dst, $src}", 1277 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32; 1278def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), 1279 "mov{q}\t{$src, $dst|$dst, $src}", 1280 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>; 1281} // SchedRW 1282 1283let hasSideEffects = 0 in { 1284 1285/// Memory offset versions of moves. The immediate is an address mode sized 1286/// offset from the segment base. 1287let SchedRW = [WriteALU] in { 1288let mayLoad = 1 in { 1289let Defs = [AL] in 1290def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src), 1291 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, 1292 AdSize32; 1293let Defs = [AX] in 1294def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src), 1295 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, 1296 OpSize16, AdSize32; 1297let Defs = [EAX] in 1298def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src), 1299 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, 1300 OpSize32, AdSize32; 1301let Defs = [RAX] in 1302def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src), 1303 "mov{q}\t{$src, %rax|rax, $src}", [], IIC_MOV_MEM>, 1304 AdSize32; 1305 1306let Defs = [AL] in 1307def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src), 1308 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, AdSize16; 1309let Defs = [AX] in 1310def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src), 1311 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, 1312 OpSize16, AdSize16; 1313let Defs = [EAX] in 1314def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src), 1315 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, 1316 AdSize16, OpSize32; 1317} 1318let mayStore = 1 in { 1319let Uses = [AL] in 1320def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs offset32_8:$dst), (ins), 1321 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize32; 1322let Uses = [AX] in 1323def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_16:$dst), (ins), 1324 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, 1325 OpSize16, AdSize32; 1326let Uses = [EAX] in 1327def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_32:$dst), (ins), 1328 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>, 1329 OpSize32, AdSize32; 1330let Uses = [RAX] in 1331def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs offset32_64:$dst), (ins), 1332 "mov{q}\t{%rax, $dst|$dst, rax}", [], IIC_MOV_MEM>, 1333 AdSize32; 1334 1335let Uses = [AL] in 1336def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs offset16_8:$dst), (ins), 1337 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize16; 1338let Uses = [AX] in 1339def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_16:$dst), (ins), 1340 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, 1341 OpSize16, AdSize16; 1342let Uses = [EAX] in 1343def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_32:$dst), (ins), 1344 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>, 1345 OpSize32, AdSize16; 1346} 1347} 1348 1349// These forms all have full 64-bit absolute addresses in their instructions 1350// and use the movabs mnemonic to indicate this specific form. 1351let mayLoad = 1 in { 1352let Defs = [AL] in 1353def MOV8ao64 : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src), 1354 "movabs{b}\t{$src, %al|al, $src}", []>, AdSize64; 1355let Defs = [AX] in 1356def MOV16ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src), 1357 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, AdSize64; 1358let Defs = [EAX] in 1359def MOV32ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src), 1360 "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32, 1361 AdSize64; 1362let Defs = [RAX] in 1363def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src), 1364 "movabs{q}\t{$src, %rax|rax, $src}", []>, AdSize64; 1365} 1366 1367let mayStore = 1 in { 1368let Uses = [AL] in 1369def MOV8o64a : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset64_8:$dst), (ins), 1370 "movabs{b}\t{%al, $dst|$dst, al}", []>, AdSize64; 1371let Uses = [AX] in 1372def MOV16o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_16:$dst), (ins), 1373 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, AdSize64; 1374let Uses = [EAX] in 1375def MOV32o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_32:$dst), (ins), 1376 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32, 1377 AdSize64; 1378let Uses = [RAX] in 1379def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs offset64_64:$dst), (ins), 1380 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, AdSize64; 1381} 1382} // hasSideEffects = 0 1383 1384let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, 1385 SchedRW = [WriteMove] in { 1386def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), 1387 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1388def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1389 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16; 1390def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1391 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32; 1392def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1393 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1394} 1395 1396let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in { 1397def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), 1398 "mov{b}\t{$src, $dst|$dst, $src}", 1399 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>; 1400def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1401 "mov{w}\t{$src, $dst|$dst, $src}", 1402 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16; 1403def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1404 "mov{l}\t{$src, $dst|$dst, $src}", 1405 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32; 1406def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1407 "mov{q}\t{$src, $dst|$dst, $src}", 1408 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>; 1409} 1410 1411let SchedRW = [WriteStore] in { 1412def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), 1413 "mov{b}\t{$src, $dst|$dst, $src}", 1414 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>; 1415def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1416 "mov{w}\t{$src, $dst|$dst, $src}", 1417 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16; 1418def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1419 "mov{l}\t{$src, $dst|$dst, $src}", 1420 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32; 1421def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1422 "mov{q}\t{$src, $dst|$dst, $src}", 1423 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>; 1424} // SchedRW 1425 1426// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so 1427// that they can be used for copying and storing h registers, which can't be 1428// encoded when a REX prefix is present. 1429let isCodeGenOnly = 1 in { 1430let hasSideEffects = 0 in 1431def MOV8rr_NOREX : I<0x88, MRMDestReg, 1432 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), 1433 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>, 1434 Sched<[WriteMove]>; 1435let mayStore = 1, hasSideEffects = 0 in 1436def MOV8mr_NOREX : I<0x88, MRMDestMem, 1437 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), 1438 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], 1439 IIC_MOV_MEM>, Sched<[WriteStore]>; 1440let mayLoad = 1, hasSideEffects = 0, 1441 canFoldAsLoad = 1, isReMaterializable = 1 in 1442def MOV8rm_NOREX : I<0x8A, MRMSrcMem, 1443 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), 1444 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], 1445 IIC_MOV_MEM>, Sched<[WriteLoad]>; 1446} 1447 1448 1449// Condition code ops, incl. set if equal/not equal/... 1450let SchedRW = [WriteALU] in { 1451let Defs = [EFLAGS], Uses = [AH] in 1452def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", 1453 [(set EFLAGS, (X86sahf AH))], IIC_AHF>; 1454let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in 1455def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [], 1456 IIC_AHF>; // AH = flags 1457} // SchedRW 1458 1459//===----------------------------------------------------------------------===// 1460// Bit tests instructions: BT, BTS, BTR, BTC. 1461 1462let Defs = [EFLAGS] in { 1463let SchedRW = [WriteALU] in { 1464def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1465 "bt{w}\t{$src2, $src1|$src1, $src2}", 1466 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>, 1467 OpSize16, TB; 1468def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1469 "bt{l}\t{$src2, $src1|$src1, $src2}", 1470 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>, 1471 OpSize32, TB; 1472def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1473 "bt{q}\t{$src2, $src1|$src1, $src2}", 1474 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB; 1475} // SchedRW 1476 1477// Unlike with the register+register form, the memory+register form of the 1478// bt instruction does not ignore the high bits of the index. From ISel's 1479// perspective, this is pretty bizarre. Make these instructions disassembly 1480// only for now. 1481 1482let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in { 1483 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1484 "bt{w}\t{$src2, $src1|$src1, $src2}", 1485 // [(X86bt (loadi16 addr:$src1), GR16:$src2), 1486 // (implicit EFLAGS)] 1487 [], IIC_BT_MR 1488 >, OpSize16, TB, Requires<[FastBTMem]>; 1489 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1490 "bt{l}\t{$src2, $src1|$src1, $src2}", 1491 // [(X86bt (loadi32 addr:$src1), GR32:$src2), 1492 // (implicit EFLAGS)] 1493 [], IIC_BT_MR 1494 >, OpSize32, TB, Requires<[FastBTMem]>; 1495 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1496 "bt{q}\t{$src2, $src1|$src1, $src2}", 1497 // [(X86bt (loadi64 addr:$src1), GR64:$src2), 1498 // (implicit EFLAGS)] 1499 [], IIC_BT_MR 1500 >, TB; 1501} 1502 1503let SchedRW = [WriteALU] in { 1504def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1505 "bt{w}\t{$src2, $src1|$src1, $src2}", 1506 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))], 1507 IIC_BT_RI>, OpSize16, TB; 1508def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1509 "bt{l}\t{$src2, $src1|$src1, $src2}", 1510 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))], 1511 IIC_BT_RI>, OpSize32, TB; 1512def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1513 "bt{q}\t{$src2, $src1|$src1, $src2}", 1514 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))], 1515 IIC_BT_RI>, TB; 1516} // SchedRW 1517 1518// Note that these instructions don't need FastBTMem because that 1519// only applies when the other operand is in a register. When it's 1520// an immediate, bt is still fast. 1521let SchedRW = [WriteALU] in { 1522def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1523 "bt{w}\t{$src2, $src1|$src1, $src2}", 1524 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2)) 1525 ], IIC_BT_MI>, OpSize16, TB; 1526def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1527 "bt{l}\t{$src2, $src1|$src1, $src2}", 1528 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2)) 1529 ], IIC_BT_MI>, OpSize32, TB; 1530def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1531 "bt{q}\t{$src2, $src1|$src1, $src2}", 1532 [(set EFLAGS, (X86bt (loadi64 addr:$src1), 1533 i64immSExt8:$src2))], IIC_BT_MI>, TB; 1534} // SchedRW 1535 1536let hasSideEffects = 0 in { 1537let SchedRW = [WriteALU] in { 1538def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1539 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1540 OpSize16, TB; 1541def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1542 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1543 OpSize32, TB; 1544def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1545 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; 1546} // SchedRW 1547 1548let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1549def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1550 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1551 OpSize16, TB; 1552def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1553 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1554 OpSize32, TB; 1555def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1556 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1557} 1558 1559let SchedRW = [WriteALU] in { 1560def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1561 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1562 OpSize16, TB; 1563def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1564 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1565 OpSize32, TB; 1566def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1567 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1568} // SchedRW 1569 1570let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1571def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1572 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1573 OpSize16, TB; 1574def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1575 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1576 OpSize32, TB; 1577def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1578 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1579} 1580 1581let SchedRW = [WriteALU] in { 1582def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1583 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1584 OpSize16, TB; 1585def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1586 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1587 OpSize32, TB; 1588def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1589 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1590} // SchedRW 1591 1592let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1593def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1594 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1595 OpSize16, TB; 1596def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1597 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1598 OpSize32, TB; 1599def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1600 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1601} 1602 1603let SchedRW = [WriteALU] in { 1604def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1605 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1606 OpSize16, TB; 1607def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1608 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1609 OpSize32, TB; 1610def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1611 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1612} // SchedRW 1613 1614let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1615def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1616 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1617 OpSize16, TB; 1618def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1619 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1620 OpSize32, TB; 1621def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1622 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1623} 1624 1625let SchedRW = [WriteALU] in { 1626def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1627 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1628 OpSize16, TB; 1629def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1630 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1631 OpSize32, TB; 1632def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1633 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; 1634} // SchedRW 1635 1636let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1637def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1638 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1639 OpSize16, TB; 1640def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1641 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1642 OpSize32, TB; 1643def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1644 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1645} 1646 1647let SchedRW = [WriteALU] in { 1648def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1649 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1650 OpSize16, TB; 1651def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1652 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1653 OpSize32, TB; 1654def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1655 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1656} // SchedRW 1657 1658let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1659def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1660 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1661 OpSize16, TB; 1662def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1663 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1664 OpSize32, TB; 1665def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1666 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1667} 1668} // hasSideEffects = 0 1669} // Defs = [EFLAGS] 1670 1671 1672//===----------------------------------------------------------------------===// 1673// Atomic support 1674// 1675 1676// Atomic swap. These are just normal xchg instructions. But since a memory 1677// operand is referenced, the atomicity is ensured. 1678multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag, 1679 InstrItinClass itin> { 1680 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in { 1681 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst), 1682 (ins GR8:$val, i8mem:$ptr), 1683 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 1684 [(set 1685 GR8:$dst, 1686 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))], 1687 itin>; 1688 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst), 1689 (ins GR16:$val, i16mem:$ptr), 1690 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 1691 [(set 1692 GR16:$dst, 1693 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))], 1694 itin>, OpSize16; 1695 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst), 1696 (ins GR32:$val, i32mem:$ptr), 1697 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 1698 [(set 1699 GR32:$dst, 1700 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))], 1701 itin>, OpSize32; 1702 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst), 1703 (ins GR64:$val, i64mem:$ptr), 1704 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 1705 [(set 1706 GR64:$dst, 1707 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))], 1708 itin>; 1709 } 1710} 1711 1712defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>; 1713 1714// Swap between registers. 1715let SchedRW = [WriteALU] in { 1716let Constraints = "$val = $dst" in { 1717def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src), 1718 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>; 1719def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src), 1720 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, 1721 OpSize16; 1722def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src), 1723 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, 1724 OpSize32; 1725def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src), 1726 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>; 1727} 1728 1729// Swap between EAX and other registers. 1730let Uses = [AX], Defs = [AX] in 1731def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src), 1732 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16; 1733let Uses = [EAX], Defs = [EAX] in 1734def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src), 1735 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>, 1736 OpSize32, Requires<[Not64BitMode]>; 1737let Uses = [EAX], Defs = [EAX] in 1738// Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding. 1739// xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP. 1740def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src), 1741 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>, 1742 OpSize32, Requires<[In64BitMode]>; 1743let Uses = [RAX], Defs = [RAX] in 1744def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src), 1745 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>; 1746} // SchedRW 1747 1748let SchedRW = [WriteALU] in { 1749def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 1750 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB; 1751def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1752 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB, 1753 OpSize16; 1754def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1755 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB, 1756 OpSize32; 1757def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1758 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB; 1759} // SchedRW 1760 1761let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1762def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 1763 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB; 1764def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1765 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB, 1766 OpSize16; 1767def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1768 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB, 1769 OpSize32; 1770def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1771 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB; 1772 1773} 1774 1775let SchedRW = [WriteALU] in { 1776def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 1777 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [], 1778 IIC_CMPXCHG_REG8>, TB; 1779def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1780 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [], 1781 IIC_CMPXCHG_REG>, TB, OpSize16; 1782def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1783 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [], 1784 IIC_CMPXCHG_REG>, TB, OpSize32; 1785def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1786 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [], 1787 IIC_CMPXCHG_REG>, TB; 1788} // SchedRW 1789 1790let SchedRW = [WriteALULd, WriteRMW] in { 1791let mayLoad = 1, mayStore = 1 in { 1792def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 1793 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [], 1794 IIC_CMPXCHG_MEM8>, TB; 1795def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1796 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [], 1797 IIC_CMPXCHG_MEM>, TB, OpSize16; 1798def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1799 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [], 1800 IIC_CMPXCHG_MEM>, TB, OpSize32; 1801def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1802 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [], 1803 IIC_CMPXCHG_MEM>, TB; 1804} 1805 1806let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in 1807def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), 1808 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB; 1809 1810let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in 1811def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), 1812 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>, 1813 TB, Requires<[HasCmpxchg16b]>; 1814} // SchedRW 1815 1816 1817// Lock instruction prefix 1818def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>; 1819 1820// Rex64 instruction prefix 1821def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>, 1822 Requires<[In64BitMode]>; 1823 1824// Data16 instruction prefix 1825def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>; 1826 1827// Repeat string operation instruction prefixes 1828// These uses the DF flag in the EFLAGS register to inc or dec ECX 1829let Defs = [ECX], Uses = [ECX,EFLAGS] in { 1830// Repeat (used with INS, OUTS, MOVS, LODS and STOS) 1831def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>; 1832// Repeat while not equal (used with CMPS and SCAS) 1833def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>; 1834} 1835 1836 1837// String manipulation instructions 1838let SchedRW = [WriteMicrocoded] in { 1839// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1840let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in 1841def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src), 1842 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>; 1843let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in 1844def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src), 1845 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16; 1846let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in 1847def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src), 1848 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32; 1849let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in 1850def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src), 1851 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>; 1852} 1853 1854let SchedRW = [WriteSystem] in { 1855// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1856let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in { 1857def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src), 1858 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>; 1859def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src), 1860 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16; 1861def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src), 1862 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32; 1863} 1864 1865// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1866let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in { 1867def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins), 1868 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>; 1869def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins), 1870 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16; 1871def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins), 1872 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32; 1873} 1874} 1875 1876// Flag instructions 1877let SchedRW = [WriteALU] in { 1878def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>; 1879def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>; 1880def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>; 1881def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>; 1882def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>; 1883def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>; 1884def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>; 1885 1886def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB; 1887} 1888 1889// Table lookup instructions 1890def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>, 1891 Sched<[WriteLoad]>; 1892 1893let SchedRW = [WriteMicrocoded] in { 1894// ASCII Adjust After Addition 1895// sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS 1896def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>, 1897 Requires<[Not64BitMode]>; 1898 1899// ASCII Adjust AX Before Division 1900// sets AL, AH and EFLAGS and uses AL and AH 1901def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src), 1902 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>; 1903 1904// ASCII Adjust AX After Multiply 1905// sets AL, AH and EFLAGS and uses AL 1906def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src), 1907 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>; 1908 1909// ASCII Adjust AL After Subtraction - sets 1910// sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS 1911def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>, 1912 Requires<[Not64BitMode]>; 1913 1914// Decimal Adjust AL after Addition 1915// sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS 1916def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>, 1917 Requires<[Not64BitMode]>; 1918 1919// Decimal Adjust AL after Subtraction 1920// sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS 1921def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>, 1922 Requires<[Not64BitMode]>; 1923} // SchedRW 1924 1925let SchedRW = [WriteSystem] in { 1926// Check Array Index Against Bounds 1927def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1928 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16, 1929 Requires<[Not64BitMode]>; 1930def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1931 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32, 1932 Requires<[Not64BitMode]>; 1933 1934// Adjust RPL Field of Segment Selector 1935def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1936 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>, 1937 Requires<[Not64BitMode]>; 1938def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1939 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>, 1940 Requires<[Not64BitMode]>; 1941} // SchedRW 1942 1943//===----------------------------------------------------------------------===// 1944// MOVBE Instructions 1945// 1946let Predicates = [HasMOVBE] in { 1947 let SchedRW = [WriteALULd] in { 1948 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1949 "movbe{w}\t{$src, $dst|$dst, $src}", 1950 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>, 1951 OpSize16, T8PS; 1952 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1953 "movbe{l}\t{$src, $dst|$dst, $src}", 1954 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>, 1955 OpSize32, T8PS; 1956 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1957 "movbe{q}\t{$src, $dst|$dst, $src}", 1958 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>, 1959 T8PS; 1960 } 1961 let SchedRW = [WriteStore] in { 1962 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1963 "movbe{w}\t{$src, $dst|$dst, $src}", 1964 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>, 1965 OpSize16, T8PS; 1966 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1967 "movbe{l}\t{$src, $dst|$dst, $src}", 1968 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>, 1969 OpSize32, T8PS; 1970 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1971 "movbe{q}\t{$src, $dst|$dst, $src}", 1972 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>, 1973 T8PS; 1974 } 1975} 1976 1977//===----------------------------------------------------------------------===// 1978// RDRAND Instruction 1979// 1980let Predicates = [HasRDRAND], Defs = [EFLAGS] in { 1981 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins), 1982 "rdrand{w}\t$dst", 1983 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB; 1984 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins), 1985 "rdrand{l}\t$dst", 1986 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB; 1987 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins), 1988 "rdrand{q}\t$dst", 1989 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB; 1990} 1991 1992//===----------------------------------------------------------------------===// 1993// RDSEED Instruction 1994// 1995let Predicates = [HasRDSEED], Defs = [EFLAGS] in { 1996 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins), 1997 "rdseed{w}\t$dst", 1998 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB; 1999 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins), 2000 "rdseed{l}\t$dst", 2001 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB; 2002 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins), 2003 "rdseed{q}\t$dst", 2004 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB; 2005} 2006 2007//===----------------------------------------------------------------------===// 2008// LZCNT Instruction 2009// 2010let Predicates = [HasLZCNT], Defs = [EFLAGS] in { 2011 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 2012 "lzcnt{w}\t{$src, $dst|$dst, $src}", 2013 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS, 2014 OpSize16; 2015 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2016 "lzcnt{w}\t{$src, $dst|$dst, $src}", 2017 [(set GR16:$dst, (ctlz (loadi16 addr:$src))), 2018 (implicit EFLAGS)]>, XS, OpSize16; 2019 2020 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 2021 "lzcnt{l}\t{$src, $dst|$dst, $src}", 2022 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS, 2023 OpSize32; 2024 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2025 "lzcnt{l}\t{$src, $dst|$dst, $src}", 2026 [(set GR32:$dst, (ctlz (loadi32 addr:$src))), 2027 (implicit EFLAGS)]>, XS, OpSize32; 2028 2029 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 2030 "lzcnt{q}\t{$src, $dst|$dst, $src}", 2031 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>, 2032 XS; 2033 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2034 "lzcnt{q}\t{$src, $dst|$dst, $src}", 2035 [(set GR64:$dst, (ctlz (loadi64 addr:$src))), 2036 (implicit EFLAGS)]>, XS; 2037} 2038 2039let Predicates = [HasLZCNT] in { 2040 def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E_OR_NE), 2041 (X86cmp GR16:$src, (i16 0))), 2042 (LZCNT16rr GR16:$src)>; 2043 def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E_OR_NE), 2044 (X86cmp GR32:$src, (i32 0))), 2045 (LZCNT32rr GR32:$src)>; 2046 def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E_OR_NE), 2047 (X86cmp GR64:$src, (i64 0))), 2048 (LZCNT64rr GR64:$src)>; 2049 def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E_OR_NE), 2050 (X86cmp GR16:$src, (i16 0))), 2051 (LZCNT16rr GR16:$src)>; 2052 def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E_OR_NE), 2053 (X86cmp GR32:$src, (i32 0))), 2054 (LZCNT32rr GR32:$src)>; 2055 def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E_OR_NE), 2056 (X86cmp GR64:$src, (i64 0))), 2057 (LZCNT64rr GR64:$src)>; 2058 2059 def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE), 2060 (X86cmp (loadi16 addr:$src), (i16 0))), 2061 (LZCNT16rm addr:$src)>; 2062 def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE), 2063 (X86cmp (loadi32 addr:$src), (i32 0))), 2064 (LZCNT32rm addr:$src)>; 2065 def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE), 2066 (X86cmp (loadi64 addr:$src), (i64 0))), 2067 (LZCNT64rm addr:$src)>; 2068 def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E_OR_NE), 2069 (X86cmp (loadi16 addr:$src), (i16 0))), 2070 (LZCNT16rm addr:$src)>; 2071 def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E_OR_NE), 2072 (X86cmp (loadi32 addr:$src), (i32 0))), 2073 (LZCNT32rm addr:$src)>; 2074 def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E_OR_NE), 2075 (X86cmp (loadi64 addr:$src), (i64 0))), 2076 (LZCNT64rm addr:$src)>; 2077} 2078 2079//===----------------------------------------------------------------------===// 2080// BMI Instructions 2081// 2082let Predicates = [HasBMI], Defs = [EFLAGS] in { 2083 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 2084 "tzcnt{w}\t{$src, $dst|$dst, $src}", 2085 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS, 2086 OpSize16; 2087 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2088 "tzcnt{w}\t{$src, $dst|$dst, $src}", 2089 [(set GR16:$dst, (cttz (loadi16 addr:$src))), 2090 (implicit EFLAGS)]>, XS, OpSize16; 2091 2092 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 2093 "tzcnt{l}\t{$src, $dst|$dst, $src}", 2094 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS, 2095 OpSize32; 2096 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2097 "tzcnt{l}\t{$src, $dst|$dst, $src}", 2098 [(set GR32:$dst, (cttz (loadi32 addr:$src))), 2099 (implicit EFLAGS)]>, XS, OpSize32; 2100 2101 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 2102 "tzcnt{q}\t{$src, $dst|$dst, $src}", 2103 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>, 2104 XS; 2105 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2106 "tzcnt{q}\t{$src, $dst|$dst, $src}", 2107 [(set GR64:$dst, (cttz (loadi64 addr:$src))), 2108 (implicit EFLAGS)]>, XS; 2109} 2110 2111multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM, 2112 RegisterClass RC, X86MemOperand x86memop> { 2113let hasSideEffects = 0 in { 2114 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src), 2115 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), 2116 []>, T8PS, VEX_4V; 2117 let mayLoad = 1 in 2118 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src), 2119 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), 2120 []>, T8PS, VEX_4V; 2121} 2122} 2123 2124let Predicates = [HasBMI], Defs = [EFLAGS] in { 2125 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>; 2126 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W; 2127 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>; 2128 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W; 2129 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>; 2130 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W; 2131} 2132 2133//===----------------------------------------------------------------------===// 2134// Pattern fragments to auto generate BMI instructions. 2135//===----------------------------------------------------------------------===// 2136 2137let Predicates = [HasBMI] in { 2138 // FIXME: patterns for the load versions are not implemented 2139 def : Pat<(and GR32:$src, (add GR32:$src, -1)), 2140 (BLSR32rr GR32:$src)>; 2141 def : Pat<(and GR64:$src, (add GR64:$src, -1)), 2142 (BLSR64rr GR64:$src)>; 2143 2144 def : Pat<(xor GR32:$src, (add GR32:$src, -1)), 2145 (BLSMSK32rr GR32:$src)>; 2146 def : Pat<(xor GR64:$src, (add GR64:$src, -1)), 2147 (BLSMSK64rr GR64:$src)>; 2148 2149 def : Pat<(and GR32:$src, (ineg GR32:$src)), 2150 (BLSI32rr GR32:$src)>; 2151 def : Pat<(and GR64:$src, (ineg GR64:$src)), 2152 (BLSI64rr GR64:$src)>; 2153} 2154 2155let Predicates = [HasBMI] in { 2156 def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E_OR_NE), 2157 (X86cmp GR16:$src, (i16 0))), 2158 (TZCNT16rr GR16:$src)>; 2159 def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E_OR_NE), 2160 (X86cmp GR32:$src, (i32 0))), 2161 (TZCNT32rr GR32:$src)>; 2162 def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E_OR_NE), 2163 (X86cmp GR64:$src, (i64 0))), 2164 (TZCNT64rr GR64:$src)>; 2165 def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E_OR_NE), 2166 (X86cmp GR16:$src, (i16 0))), 2167 (TZCNT16rr GR16:$src)>; 2168 def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E_OR_NE), 2169 (X86cmp GR32:$src, (i32 0))), 2170 (TZCNT32rr GR32:$src)>; 2171 def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E_OR_NE), 2172 (X86cmp GR64:$src, (i64 0))), 2173 (TZCNT64rr GR64:$src)>; 2174 2175 def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE), 2176 (X86cmp (loadi16 addr:$src), (i16 0))), 2177 (TZCNT16rm addr:$src)>; 2178 def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE), 2179 (X86cmp (loadi32 addr:$src), (i32 0))), 2180 (TZCNT32rm addr:$src)>; 2181 def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE), 2182 (X86cmp (loadi64 addr:$src), (i64 0))), 2183 (TZCNT64rm addr:$src)>; 2184 def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E_OR_NE), 2185 (X86cmp (loadi16 addr:$src), (i16 0))), 2186 (TZCNT16rm addr:$src)>; 2187 def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E_OR_NE), 2188 (X86cmp (loadi32 addr:$src), (i32 0))), 2189 (TZCNT32rm addr:$src)>; 2190 def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E_OR_NE), 2191 (X86cmp (loadi64 addr:$src), (i64 0))), 2192 (TZCNT64rm addr:$src)>; 2193} 2194 2195 2196multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC, 2197 X86MemOperand x86memop, Intrinsic Int, 2198 PatFrag ld_frag> { 2199 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2200 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2201 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>, 2202 T8PS, VEX_4VOp3; 2203 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), 2204 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2205 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)), 2206 (implicit EFLAGS)]>, T8PS, VEX_4VOp3; 2207} 2208 2209let Predicates = [HasBMI], Defs = [EFLAGS] in { 2210 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem, 2211 int_x86_bmi_bextr_32, loadi32>; 2212 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem, 2213 int_x86_bmi_bextr_64, loadi64>, VEX_W; 2214} 2215 2216let Predicates = [HasBMI2], Defs = [EFLAGS] in { 2217 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem, 2218 int_x86_bmi_bzhi_32, loadi32>; 2219 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem, 2220 int_x86_bmi_bzhi_64, loadi64>, VEX_W; 2221} 2222 2223 2224def CountTrailingOnes : SDNodeXForm<imm, [{ 2225 // Count the trailing ones in the immediate. 2226 return getI8Imm(countTrailingOnes(N->getZExtValue())); 2227}]>; 2228 2229def BZHIMask : ImmLeaf<i64, [{ 2230 return isMask_64(Imm) && (countTrailingOnes<uint64_t>(Imm) > 32); 2231}]>; 2232 2233let Predicates = [HasBMI2] in { 2234 def : Pat<(and GR64:$src, BZHIMask:$mask), 2235 (BZHI64rr GR64:$src, 2236 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2237 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; 2238 2239 def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)), 2240 (BZHI32rr GR32:$src, 2241 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2242 2243 def : Pat<(and (loadi32 addr:$src), (add (shl 1, GR8:$lz), -1)), 2244 (BZHI32rm addr:$src, 2245 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2246 2247 def : Pat<(and GR64:$src, (add (shl 1, GR8:$lz), -1)), 2248 (BZHI64rr GR64:$src, 2249 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2250 2251 def : Pat<(and (loadi64 addr:$src), (add (shl 1, GR8:$lz), -1)), 2252 (BZHI64rm addr:$src, 2253 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2254} // HasBMI2 2255 2256let Predicates = [HasBMI] in { 2257 def : Pat<(X86bextr GR32:$src1, GR32:$src2), 2258 (BEXTR32rr GR32:$src1, GR32:$src2)>; 2259 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2), 2260 (BEXTR32rm addr:$src1, GR32:$src2)>; 2261 def : Pat<(X86bextr GR64:$src1, GR64:$src2), 2262 (BEXTR64rr GR64:$src1, GR64:$src2)>; 2263 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2), 2264 (BEXTR64rm addr:$src1, GR64:$src2)>; 2265} // HasBMI 2266 2267multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC, 2268 X86MemOperand x86memop, Intrinsic Int, 2269 PatFrag ld_frag> { 2270 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2271 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2272 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>, 2273 VEX_4V; 2274 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), 2275 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2276 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V; 2277} 2278 2279let Predicates = [HasBMI2] in { 2280 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, 2281 int_x86_bmi_pdep_32, loadi32>, T8XD; 2282 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, 2283 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W; 2284 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, 2285 int_x86_bmi_pext_32, loadi32>, T8XS; 2286 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, 2287 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W; 2288} 2289 2290//===----------------------------------------------------------------------===// 2291// TBM Instructions 2292// 2293let Predicates = [HasTBM], Defs = [EFLAGS] in { 2294 2295multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr, 2296 X86MemOperand x86memop, PatFrag ld_frag, 2297 Intrinsic Int, Operand immtype, 2298 SDPatternOperator immoperator> { 2299 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl), 2300 !strconcat(OpcodeStr, 2301 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2302 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>, 2303 XOP, XOPA; 2304 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst), 2305 (ins x86memop:$src1, immtype:$cntl), 2306 !strconcat(OpcodeStr, 2307 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2308 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>, 2309 XOP, XOPA; 2310} 2311 2312defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32, 2313 int_x86_tbm_bextri_u32, i32imm, imm>; 2314let ImmT = Imm32S in 2315defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64, 2316 int_x86_tbm_bextri_u64, i64i32imm, 2317 i64immSExt32>, VEX_W; 2318 2319multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem, 2320 RegisterClass RC, string OpcodeStr, 2321 X86MemOperand x86memop, PatFrag ld_frag> { 2322let hasSideEffects = 0 in { 2323 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src), 2324 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), 2325 []>, XOP_4V, XOP9; 2326 let mayLoad = 1 in 2327 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src), 2328 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), 2329 []>, XOP_4V, XOP9; 2330} 2331} 2332 2333multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr, 2334 Format FormReg, Format FormMem> { 2335 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem, 2336 loadi32>; 2337 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem, 2338 loadi64>, VEX_W; 2339} 2340 2341defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>; 2342defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>; 2343defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>; 2344defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>; 2345defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>; 2346defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>; 2347defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>; 2348defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>; 2349defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>; 2350} // HasTBM, EFLAGS 2351 2352//===----------------------------------------------------------------------===// 2353// Pattern fragments to auto generate TBM instructions. 2354//===----------------------------------------------------------------------===// 2355 2356let Predicates = [HasTBM] in { 2357 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)), 2358 (BEXTRI32ri GR32:$src1, imm:$src2)>; 2359 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)), 2360 (BEXTRI32mi addr:$src1, imm:$src2)>; 2361 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2), 2362 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>; 2363 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2), 2364 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>; 2365 2366 // FIXME: patterns for the load versions are not implemented 2367 def : Pat<(and GR32:$src, (add GR32:$src, 1)), 2368 (BLCFILL32rr GR32:$src)>; 2369 def : Pat<(and GR64:$src, (add GR64:$src, 1)), 2370 (BLCFILL64rr GR64:$src)>; 2371 2372 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))), 2373 (BLCI32rr GR32:$src)>; 2374 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))), 2375 (BLCI64rr GR64:$src)>; 2376 2377 // Extra patterns because opt can optimize the above patterns to this. 2378 def : Pat<(or GR32:$src, (sub -2, GR32:$src)), 2379 (BLCI32rr GR32:$src)>; 2380 def : Pat<(or GR64:$src, (sub -2, GR64:$src)), 2381 (BLCI64rr GR64:$src)>; 2382 2383 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)), 2384 (BLCIC32rr GR32:$src)>; 2385 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)), 2386 (BLCIC64rr GR64:$src)>; 2387 2388 def : Pat<(xor GR32:$src, (add GR32:$src, 1)), 2389 (BLCMSK32rr GR32:$src)>; 2390 def : Pat<(xor GR64:$src, (add GR64:$src, 1)), 2391 (BLCMSK64rr GR64:$src)>; 2392 2393 def : Pat<(or GR32:$src, (add GR32:$src, 1)), 2394 (BLCS32rr GR32:$src)>; 2395 def : Pat<(or GR64:$src, (add GR64:$src, 1)), 2396 (BLCS64rr GR64:$src)>; 2397 2398 def : Pat<(or GR32:$src, (add GR32:$src, -1)), 2399 (BLSFILL32rr GR32:$src)>; 2400 def : Pat<(or GR64:$src, (add GR64:$src, -1)), 2401 (BLSFILL64rr GR64:$src)>; 2402 2403 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)), 2404 (BLSIC32rr GR32:$src)>; 2405 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)), 2406 (BLSIC64rr GR64:$src)>; 2407 2408 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)), 2409 (T1MSKC32rr GR32:$src)>; 2410 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)), 2411 (T1MSKC64rr GR64:$src)>; 2412 2413 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)), 2414 (TZMSK32rr GR32:$src)>; 2415 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)), 2416 (TZMSK64rr GR64:$src)>; 2417} // HasTBM 2418 2419//===----------------------------------------------------------------------===// 2420// Memory Instructions 2421// 2422 2423def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), 2424 "clflushopt\t$src", []>, PD; 2425def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", []>, PD; 2426def PCOMMIT : I<0xAE, MRM_F8, (outs), (ins), "pcommit", []>, PD; 2427 2428 2429//===----------------------------------------------------------------------===// 2430// Subsystems. 2431//===----------------------------------------------------------------------===// 2432 2433include "X86InstrArithmetic.td" 2434include "X86InstrCMovSetCC.td" 2435include "X86InstrExtension.td" 2436include "X86InstrControl.td" 2437include "X86InstrShiftRotate.td" 2438 2439// X87 Floating Point Stack. 2440include "X86InstrFPStack.td" 2441 2442// SIMD support (SSE, MMX and AVX) 2443include "X86InstrFragmentsSIMD.td" 2444 2445// FMA - Fused Multiply-Add support (requires FMA) 2446include "X86InstrFMA.td" 2447 2448// XOP 2449include "X86InstrXOP.td" 2450 2451// SSE, MMX and 3DNow! vector support. 2452include "X86InstrSSE.td" 2453include "X86InstrAVX512.td" 2454include "X86InstrMMX.td" 2455include "X86Instr3DNow.td" 2456 2457include "X86InstrVMX.td" 2458include "X86InstrSVM.td" 2459 2460include "X86InstrTSX.td" 2461include "X86InstrSGX.td" 2462 2463// System instructions. 2464include "X86InstrSystem.td" 2465 2466// Compiler Pseudo Instructions and Pat Patterns 2467include "X86InstrCompiler.td" 2468 2469//===----------------------------------------------------------------------===// 2470// Assembler Mnemonic Aliases 2471//===----------------------------------------------------------------------===// 2472 2473def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>; 2474def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>; 2475def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>; 2476 2477def : MnemonicAlias<"cbw", "cbtw", "att">; 2478def : MnemonicAlias<"cwde", "cwtl", "att">; 2479def : MnemonicAlias<"cwd", "cwtd", "att">; 2480def : MnemonicAlias<"cdq", "cltd", "att">; 2481def : MnemonicAlias<"cdqe", "cltq", "att">; 2482def : MnemonicAlias<"cqo", "cqto", "att">; 2483 2484// In 64-bit mode lret maps to lretl; it is not ambiguous with lretq. 2485def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>; 2486def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>; 2487 2488def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>; 2489def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>; 2490 2491def : MnemonicAlias<"loopz", "loope", "att">; 2492def : MnemonicAlias<"loopnz", "loopne", "att">; 2493 2494def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>; 2495def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>; 2496def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>; 2497def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>; 2498def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>; 2499def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>; 2500def : MnemonicAlias<"popfd", "popfl", "att">; 2501 2502// FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in 2503// all modes. However: "push (addr)" and "push $42" should default to 2504// pushl/pushq depending on the current mode. Similar for "pop %bx" 2505def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>; 2506def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>; 2507def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>; 2508def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>; 2509def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>; 2510def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 2511def : MnemonicAlias<"pushfd", "pushfl", "att">; 2512 2513def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>; 2514def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>; 2515def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>; 2516def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>; 2517def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>; 2518def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>; 2519 2520def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>; 2521def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>; 2522def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>; 2523def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>; 2524 2525def : MnemonicAlias<"repe", "rep", "att">; 2526def : MnemonicAlias<"repz", "rep", "att">; 2527def : MnemonicAlias<"repnz", "repne", "att">; 2528 2529def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>; 2530def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>; 2531def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>; 2532 2533def : MnemonicAlias<"salb", "shlb", "att">; 2534def : MnemonicAlias<"salw", "shlw", "att">; 2535def : MnemonicAlias<"sall", "shll", "att">; 2536def : MnemonicAlias<"salq", "shlq", "att">; 2537 2538def : MnemonicAlias<"smovb", "movsb", "att">; 2539def : MnemonicAlias<"smovw", "movsw", "att">; 2540def : MnemonicAlias<"smovl", "movsl", "att">; 2541def : MnemonicAlias<"smovq", "movsq", "att">; 2542 2543def : MnemonicAlias<"ud2a", "ud2", "att">; 2544def : MnemonicAlias<"verrw", "verr", "att">; 2545 2546// System instruction aliases. 2547def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>; 2548def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>; 2549def : MnemonicAlias<"sysret", "sysretl", "att">; 2550def : MnemonicAlias<"sysexit", "sysexitl", "att">; 2551 2552def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>; 2553def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>; 2554def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>; 2555def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>; 2556def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>; 2557def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>; 2558def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>; 2559def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>; 2560def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>; 2561def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>; 2562def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>; 2563def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>; 2564 2565 2566// Floating point stack aliases. 2567def : MnemonicAlias<"fcmovz", "fcmove", "att">; 2568def : MnemonicAlias<"fcmova", "fcmovnbe", "att">; 2569def : MnemonicAlias<"fcmovnae", "fcmovb", "att">; 2570def : MnemonicAlias<"fcmovna", "fcmovbe", "att">; 2571def : MnemonicAlias<"fcmovae", "fcmovnb", "att">; 2572def : MnemonicAlias<"fcomip", "fcompi", "att">; 2573def : MnemonicAlias<"fildq", "fildll", "att">; 2574def : MnemonicAlias<"fistpq", "fistpll", "att">; 2575def : MnemonicAlias<"fisttpq", "fisttpll", "att">; 2576def : MnemonicAlias<"fldcww", "fldcw", "att">; 2577def : MnemonicAlias<"fnstcww", "fnstcw", "att">; 2578def : MnemonicAlias<"fnstsww", "fnstsw", "att">; 2579def : MnemonicAlias<"fucomip", "fucompi", "att">; 2580def : MnemonicAlias<"fwait", "wait">; 2581 2582def : MnemonicAlias<"fxsaveq", "fxsave64", "att">; 2583def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">; 2584def : MnemonicAlias<"xsaveq", "xsave64", "att">; 2585def : MnemonicAlias<"xrstorq", "xrstor64", "att">; 2586def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">; 2587 2588 2589class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond, 2590 string VariantName> 2591 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix), 2592 !strconcat(Prefix, NewCond, Suffix), VariantName>; 2593 2594/// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of 2595/// MnemonicAlias's that canonicalize the condition code in a mnemonic, for 2596/// example "setz" -> "sete". 2597multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix, 2598 string V = ""> { 2599 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb 2600 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete 2601 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe 2602 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae 2603 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae 2604 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle 2605 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge 2606 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne 2607 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp 2608 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp 2609 2610 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb 2611 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta 2612 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl 2613 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg 2614} 2615 2616// Aliases for set<CC> 2617defm : IntegerCondCodeMnemonicAlias<"set", "">; 2618// Aliases for j<CC> 2619defm : IntegerCondCodeMnemonicAlias<"j", "">; 2620// Aliases for cmov<CC>{w,l,q} 2621defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">; 2622defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">; 2623defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">; 2624// No size suffix for intel-style asm. 2625defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">; 2626 2627 2628//===----------------------------------------------------------------------===// 2629// Assembler Instruction Aliases 2630//===----------------------------------------------------------------------===// 2631 2632// aad/aam default to base 10 if no operand is specified. 2633def : InstAlias<"aad", (AAD8i8 10)>; 2634def : InstAlias<"aam", (AAM8i8 10)>; 2635 2636// Disambiguate the mem/imm form of bt-without-a-suffix as btl. 2637// Likewise for btc/btr/bts. 2638def : InstAlias<"bt {$imm, $mem|$mem, $imm}", 2639 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2640def : InstAlias<"btc {$imm, $mem|$mem, $imm}", 2641 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2642def : InstAlias<"btr {$imm, $mem|$mem, $imm}", 2643 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2644def : InstAlias<"bts {$imm, $mem|$mem, $imm}", 2645 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2646 2647// clr aliases. 2648def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>; 2649def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>; 2650def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>; 2651def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>; 2652 2653// lods aliases. Accept the destination being omitted because it's implicit 2654// in the mnemonic, or the mnemonic suffix being omitted because it's implicit 2655// in the destination. 2656def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>; 2657def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>; 2658def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>; 2659def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 2660def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>; 2661def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>; 2662def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>; 2663def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 2664 2665// stos aliases. Accept the source being omitted because it's implicit in 2666// the mnemonic, or the mnemonic suffix being omitted because it's implicit 2667// in the source. 2668def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>; 2669def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>; 2670def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>; 2671def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2672def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>; 2673def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>; 2674def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>; 2675def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2676 2677// scas aliases. Accept the destination being omitted because it's implicit 2678// in the mnemonic, or the mnemonic suffix being omitted because it's implicit 2679// in the destination. 2680def : InstAlias<"scasb $dst", (SCASB dstidx8:$dst), 0>; 2681def : InstAlias<"scasw $dst", (SCASW dstidx16:$dst), 0>; 2682def : InstAlias<"scas{l|d} $dst", (SCASL dstidx32:$dst), 0>; 2683def : InstAlias<"scasq $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2684def : InstAlias<"scas {$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>; 2685def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>; 2686def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>; 2687def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2688 2689// div and idiv aliases for explicit A register. 2690def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>; 2691def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>; 2692def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>; 2693def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>; 2694def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>; 2695def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>; 2696def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>; 2697def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>; 2698def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>; 2699def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>; 2700def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>; 2701def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>; 2702def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>; 2703def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>; 2704def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>; 2705def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>; 2706 2707 2708 2709// Various unary fpstack operations default to operating on on ST1. 2710// For example, "fxch" -> "fxch %st(1)" 2711def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; 2712def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>; 2713def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>; 2714def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>; 2715def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>; 2716def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>; 2717def : InstAlias<"fxch", (XCH_F ST1), 0>; 2718def : InstAlias<"fcom", (COM_FST0r ST1), 0>; 2719def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>; 2720def : InstAlias<"fcomi", (COM_FIr ST1), 0>; 2721def : InstAlias<"fcompi", (COM_FIPr ST1), 0>; 2722def : InstAlias<"fucom", (UCOM_Fr ST1), 0>; 2723def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>; 2724def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>; 2725def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>; 2726 2727// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. 2728// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate 2729// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with 2730// gas. 2731multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> { 2732 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"), 2733 (Inst RST:$op), EmitAlias>; 2734 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"), 2735 (Inst ST0), EmitAlias>; 2736} 2737 2738defm : FpUnaryAlias<"fadd", ADD_FST0r>; 2739defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; 2740defm : FpUnaryAlias<"fsub", SUB_FST0r>; 2741defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>; 2742defm : FpUnaryAlias<"fsubr", SUBR_FST0r>; 2743defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>; 2744defm : FpUnaryAlias<"fmul", MUL_FST0r>; 2745defm : FpUnaryAlias<"fmulp", MUL_FPrST0>; 2746defm : FpUnaryAlias<"fdiv", DIV_FST0r>; 2747defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>; 2748defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; 2749defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>; 2750defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; 2751defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; 2752defm : FpUnaryAlias<"fcompi", COM_FIPr>; 2753defm : FpUnaryAlias<"fucompi", UCOM_FIPr>; 2754 2755 2756// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they 2757// commute. We also allow fdiv[r]p/fsubrp even though they don't commute, 2758// solely because gas supports it. 2759def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>; 2760def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>; 2761def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>; 2762def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>; 2763def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>; 2764def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>; 2765 2766// We accept "fnstsw %eax" even though it only writes %ax. 2767def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>; 2768def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>; 2769def : InstAlias<"fnstsw" , (FNSTSW16r)>; 2770 2771// lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but 2772// this is compatible with what GAS does. 2773def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>; 2774def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>; 2775def : InstAlias<"lcall {*}$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>; 2776def : InstAlias<"ljmp {*}$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>; 2777def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 2778def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 2779def : InstAlias<"lcall {*}$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>; 2780def : InstAlias<"ljmp {*}$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>; 2781 2782def : InstAlias<"call {*}$dst", (CALL64m i64mem:$dst), 0>, Requires<[In64BitMode]>; 2783def : InstAlias<"jmp {*}$dst", (JMP64m i64mem:$dst), 0>, Requires<[In64BitMode]>; 2784def : InstAlias<"call {*}$dst", (CALL32m i32mem:$dst), 0>, Requires<[In32BitMode]>; 2785def : InstAlias<"jmp {*}$dst", (JMP32m i32mem:$dst), 0>, Requires<[In32BitMode]>; 2786def : InstAlias<"call {*}$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>; 2787def : InstAlias<"jmp {*}$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>; 2788 2789 2790// "imul <imm>, B" is an alias for "imul <imm>, B, B". 2791def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>; 2792def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>; 2793def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>; 2794def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>; 2795def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>; 2796def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>; 2797 2798// inb %dx -> inb %al, %dx 2799def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>; 2800def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>; 2801def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>; 2802def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>; 2803def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>; 2804def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>; 2805 2806 2807// jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp 2808def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 2809def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 2810def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>; 2811def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>; 2812def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>; 2813def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>; 2814def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; 2815def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; 2816 2817// Force mov without a suffix with a segment and mem to prefer the 'l' form of 2818// the move. All segment/mem forms are equivalent, this has the shortest 2819// encoding. 2820def : InstAlias<"mov {$mem, $seg|$seg, $mem}", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>; 2821def : InstAlias<"mov {$seg, $mem|$mem, $seg}", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>; 2822 2823// Match 'movq <largeimm>, <reg>' as an alias for movabsq. 2824def : InstAlias<"movq {$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>; 2825 2826// Match 'movq GR64, MMX' as an alias for movd. 2827def : InstAlias<"movq {$src, $dst|$dst, $src}", 2828 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; 2829def : InstAlias<"movq {$src, $dst|$dst, $src}", 2830 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; 2831 2832// movsx aliases 2833def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>; 2834def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>; 2835def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>; 2836def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>; 2837def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>; 2838def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>; 2839def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>; 2840 2841// movzx aliases 2842def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>; 2843def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>; 2844def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>; 2845def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>; 2846def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>; 2847def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>; 2848// Note: No GR32->GR64 movzx form. 2849 2850// outb %dx -> outb %al, %dx 2851def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>; 2852def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>; 2853def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>; 2854def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>; 2855def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>; 2856def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>; 2857 2858// 'sldt <mem>' can be encoded with either sldtw or sldtq with the same 2859// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity 2860// errors, since its encoding is the most compact. 2861def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>; 2862 2863// shld/shrd op,op -> shld op, op, CL 2864def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>; 2865def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>; 2866def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>; 2867def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>; 2868def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>; 2869def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>; 2870 2871def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>; 2872def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>; 2873def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>; 2874def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>; 2875def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>; 2876def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>; 2877 2878/* FIXME: This is disabled because the asm matcher is currently incapable of 2879 * matching a fixed immediate like $1. 2880// "shl X, $1" is an alias for "shl X". 2881multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> { 2882 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 2883 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>; 2884 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 2885 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>; 2886 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 2887 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>; 2888 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 2889 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>; 2890 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 2891 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>; 2892 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 2893 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>; 2894 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 2895 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>; 2896 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 2897 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>; 2898} 2899 2900defm : ShiftRotateByOneAlias<"rcl", "RCL">; 2901defm : ShiftRotateByOneAlias<"rcr", "RCR">; 2902defm : ShiftRotateByOneAlias<"rol", "ROL">; 2903defm : ShiftRotateByOneAlias<"ror", "ROR">; 2904FIXME */ 2905 2906// test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms. 2907def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}", 2908 (TEST8rm GR8 :$val, i8mem :$mem), 0>; 2909def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}", 2910 (TEST16rm GR16:$val, i16mem:$mem), 0>; 2911def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}", 2912 (TEST32rm GR32:$val, i32mem:$mem), 0>; 2913def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}", 2914 (TEST64rm GR64:$val, i64mem:$mem), 0>; 2915 2916// xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms. 2917def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", 2918 (XCHG8rm GR8 :$val, i8mem :$mem), 0>; 2919def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", 2920 (XCHG16rm GR16:$val, i16mem:$mem), 0>; 2921def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", 2922 (XCHG32rm GR32:$val, i32mem:$mem), 0>; 2923def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", 2924 (XCHG64rm GR64:$val, i64mem:$mem), 0>; 2925 2926// xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms. 2927def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>; 2928def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", 2929 (XCHG32ar GR32:$src), 0>, Requires<[Not64BitMode]>; 2930def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", 2931 (XCHG32ar64 GR32_NOAX:$src), 0>, Requires<[In64BitMode]>; 2932def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>; 2933