1/*
2 * Copyright (C) 2010 The Android Open Source Project
3 * Copyright (c) 2008 ARM Ltd
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 * 3. The name of the company may not be used to endorse or promote
15 *    products derived from this software without specific prior written
16 *    permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
24 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
25 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
26 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Android adaptation and tweak by Jim Huang <jserv@0xlab.org>.
30 */
31
32#include <machine/cpu-features.h>
33#include <private/bionic_asm.h>
34
35.syntax unified
36
37ENTRY(strcpy)
38	pld	[r1, #0]
39	eor	r2, r0, r1
40	mov	ip, r0
41	tst	r2, #3
42	bne	4f
43	tst	r1, #3
44	bne	3f
455:
46	str	r5, [sp, #-4]!
47	mov	r5, #0x01
48	orr	r5, r5, r5, lsl #8
49	orr	r5, r5, r5, lsl #16
50
51	str	r4, [sp, #-4]!
52	tst	r1, #4
53	ldr	r3, [r1], #4
54	beq	2f
55	sub	r2, r3, r5
56	bics	r2, r2, r3
57	tst	r2, r5, lsl #7
58	itt	eq
59	streq	r3, [ip], #4
60	ldreq	r3, [r1], #4
61	bne	1f
62       /* Inner loop.  We now know that r1 is 64-bit aligned, so we
63	  can safely fetch up to two words.  This allows us to avoid
64	  load stalls.  */
65	.p2align 2
662:
67	pld	[r1, #8]
68	ldr	r4, [r1], #4
69	sub	r2, r3, r5
70	bics	r2, r2, r3
71	tst	r2, r5, lsl #7
72	sub	r2, r4, r5
73	bne	1f
74	str	r3, [ip], #4
75	bics	r2, r2, r4
76	tst	r2, r5, lsl #7
77	itt	eq
78	ldreq	r3, [r1], #4
79	streq	r4, [ip], #4
80	beq	2b
81	mov	r3, r4
821:
83#ifdef __ARMEB__
84	rors	r3, r3, #24
85#endif
86	strb	r3, [ip], #1
87	tst	r3, #0xff
88#ifdef __ARMEL__
89	ror	r3, r3, #8
90#endif
91	bne	1b
92	ldr	r4, [sp], #4
93	ldr	r5, [sp], #4
94	bx	lr
95
96       /* Strings have the same offset from word alignment, but it's
97	  not zero.  */
983:
99	tst	r1, #1
100	beq	1f
101	ldrb	r2, [r1], #1
102	strb	r2, [ip], #1
103	cmp	r2, #0
104	it	eq
105	bxeq	lr
1061:
107	tst	r1, #2
108	beq	5b
109	ldrh	r2, [r1], #2
110#ifdef __ARMEB__
111	tst	r2, #0xff00
112	iteet	ne
113	strhne	r2, [ip], #2
114	lsreq	r2, r2, #8
115	strbeq	r2, [ip]
116	tstne	r2, #0xff
117#else
118	tst	r2, #0xff
119	itet	ne
120	strhne	r2, [ip], #2
121	strbeq	r2, [ip]
122	tstne	r2, #0xff00
123#endif
124	bne	5b
125	bx	lr
126
127       /* src and dst do not have a common word-alignement.  Fall back to
128	  byte copying.  */
1294:
130	ldrb	r2, [r1], #1
131	strb	r2, [ip], #1
132	cmp	r2, #0
133	bne	4b
134	bx	lr
135END(strcpy)
136