1 /******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20
21 /*****************************************************************************/
22 /* */
23 /* File Name : ih264d_api.c */
24 /* */
25 /* Description : Has all API related functions */
26 /* */
27 /* */
28 /* List of Functions : api_check_struct_sanity */
29 /* ih264d_set_processor */
30 /* ih264d_get_num_rec */
31 /* ih264d_init_decoder */
32 /* ih264d_init_video_decoder */
33 /* ih264d_fill_num_mem_rec */
34 /* ih264d_clr */
35 /* ih264d_init */
36 /* ih264d_map_error */
37 /* ih264d_video_decode */
38 /* ih264d_get_version */
39 /* ih264d_get_display_frame */
40 /* ih264d_set_display_frame */
41 /* ih264d_set_flush_mode */
42 /* ih264d_get_status */
43 /* ih264d_get_buf_info */
44 /* ih264d_set_params */
45 /* ih264d_set_default_params */
46 /* ih264d_reset */
47 /* ih264d_ctl */
48 /* ih264d_rel_display_frame */
49 /* ih264d_set_degrade */
50 /* ih264d_get_frame_dimensions */
51 /* ih264d_set_num_cores */
52 /* ih264d_fill_output_struct_from_context */
53 /* ih264d_api_function */
54 /* */
55 /* Issues / Problems : None */
56 /* */
57 /* Revision History : */
58 /* */
59 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
60 /* 14 10 2008 100356(SKV) Draft */
61 /* */
62 /*****************************************************************************/
63 #include "ih264_typedefs.h"
64 #include "ih264_macros.h"
65 #include "ih264_platform_macros.h"
66 #include "ih264d_tables.h"
67 #include "iv.h"
68 #include "ivd.h"
69 #include "ih264d.h"
70 #include "ih264d_defs.h"
71
72 #include <string.h>
73 #include <limits.h>
74 #include <stddef.h>
75
76 #include "ih264d_inter_pred.h"
77
78 #include "ih264d_structs.h"
79 #include "ih264d_nal.h"
80 #include "ih264d_error_handler.h"
81
82 #include "ih264d_defs.h"
83
84 #include "ithread.h"
85 #include "ih264d_parse_slice.h"
86 #include "ih264d_function_selector.h"
87 #include "ih264_error.h"
88 #include "ih264_disp_mgr.h"
89 #include "ih264_buf_mgr.h"
90 #include "ih264d_deblocking.h"
91 #include "ih264d_parse_cavlc.h"
92 #include "ih264d_parse_cabac.h"
93 #include "ih264d_utils.h"
94 #include "ih264d_format_conv.h"
95 #include "ih264d_parse_headers.h"
96 #include "ih264d_thread_compute_bs.h"
97 #include <assert.h>
98
99
100 /*********************/
101 /* Codec Versioning */
102 /*********************/
103 //Move this to where it is used
104 #define CODEC_NAME "H264VDEC"
105 #define CODEC_RELEASE_TYPE "production"
106 #define CODEC_RELEASE_VER "04.00"
107 #define CODEC_VENDOR "ITTIAM"
108 #define MAXVERSION_STRLEN 511
109 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
110 snprintf(version_string, MAXVERSION_STRLEN, \
111 "@(#)Id:%s_%s Ver:%s Released by %s Build: %s @ %s", \
112 codec_name, codec_release_type, codec_release_ver, codec_vendor, __DATE__, __TIME__)
113
114 #define MAX_NAL_UNIT_SIZE MAX((H264_MAX_FRAME_HEIGHT * H264_MAX_FRAME_HEIGHT),MIN_NALUNIT_SIZE)
115 #define MIN_NALUNIT_SIZE 200000
116
117
118 #define MIN_IN_BUFS 1
119 #define MIN_OUT_BUFS_420 3
120 #define MIN_OUT_BUFS_422ILE 1
121 #define MIN_OUT_BUFS_RGB565 1
122 #define MIN_OUT_BUFS_420SP 2
123 #define MIN_IN_BUF_SIZE (2*1024*1024) // Currently, i4_size set to 500kb, CHECK LATER
124
125 #define NUM_FRAMES_LIMIT_ENABLED 0
126
127 #if NUM_FRAMES_LIMIT_ENABLED
128 #define NUM_FRAMES_LIMIT 10000
129 #else
130 #define NUM_FRAMES_LIMIT 0x7FFFFFFF
131 #endif
132
133
134 UWORD32 ih264d_get_extra_mem_external(UWORD32 width, UWORD32 height);
135 WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl,
136 void *pv_api_ip,
137 void *pv_api_op);
138 WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op);
139
140 WORD32 ih264d_deblock_display(dec_struct_t *ps_dec);
141
142 void ih264d_signal_decode_thread(dec_struct_t *ps_dec);
143
144 void ih264d_signal_bs_deblk_thread(dec_struct_t *ps_dec);
145 void ih264d_decode_picture_thread(dec_struct_t *ps_dec);
146
147 WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj,
148 void *pv_api_ip,
149 void *pv_api_op);
150
151 void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec,
152 ivd_video_decode_op_t *ps_dec_op);
153
api_check_struct_sanity(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op)154 static IV_API_CALL_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle,
155 void *pv_api_ip,
156 void *pv_api_op)
157 {
158 IVD_API_COMMAND_TYPE_T e_cmd;
159 UWORD32 *pu4_api_ip;
160 UWORD32 *pu4_api_op;
161 UWORD32 i, j;
162
163 if(NULL == pv_api_op)
164 return (IV_FAIL);
165
166 if(NULL == pv_api_ip)
167 return (IV_FAIL);
168
169 pu4_api_ip = (UWORD32 *)pv_api_ip;
170 pu4_api_op = (UWORD32 *)pv_api_op;
171 e_cmd = *(pu4_api_ip + 1);
172
173 /* error checks on handle */
174 switch((WORD32)e_cmd)
175 {
176 case IV_CMD_GET_NUM_MEM_REC:
177 case IV_CMD_FILL_NUM_MEM_REC:
178 break;
179 case IV_CMD_INIT:
180 if(ps_handle == NULL)
181 {
182 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
183 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
184 return IV_FAIL;
185 }
186
187 if(ps_handle->u4_size != sizeof(iv_obj_t))
188 {
189 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
190 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
191 H264_DEC_DEBUG_PRINT(
192 "Sizes do not match. Expected: %d, Got: %d",
193 sizeof(iv_obj_t), ps_handle->u4_size);
194 return IV_FAIL;
195 }
196 break;
197 case IVD_CMD_REL_DISPLAY_FRAME:
198 case IVD_CMD_SET_DISPLAY_FRAME:
199 case IVD_CMD_GET_DISPLAY_FRAME:
200 case IVD_CMD_VIDEO_DECODE:
201 case IV_CMD_RETRIEVE_MEMREC:
202 case IVD_CMD_VIDEO_CTL:
203 if(ps_handle == NULL)
204 {
205 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
206 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
207 return IV_FAIL;
208 }
209
210 if(ps_handle->u4_size != sizeof(iv_obj_t))
211 {
212 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
213 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
214 return IV_FAIL;
215 }
216
217 if(ps_handle->pv_fxns != ih264d_api_function)
218 {
219 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
220 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
221 return IV_FAIL;
222 }
223
224 if(ps_handle->pv_codec_handle == NULL)
225 {
226 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
227 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
228 return IV_FAIL;
229 }
230 break;
231 default:
232 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
233 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD;
234 return IV_FAIL;
235 }
236
237 switch((WORD32)e_cmd)
238 {
239 case IV_CMD_GET_NUM_MEM_REC:
240 {
241 ih264d_num_mem_rec_ip_t *ps_ip =
242 (ih264d_num_mem_rec_ip_t *)pv_api_ip;
243 ih264d_num_mem_rec_op_t *ps_op =
244 (ih264d_num_mem_rec_op_t *)pv_api_op;
245 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code = 0;
246
247 if(ps_ip->s_ivd_num_mem_rec_ip_t.u4_size
248 != sizeof(ih264d_num_mem_rec_ip_t))
249 {
250 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1
251 << IVD_UNSUPPORTEDPARAM;
252 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |=
253 IVD_IP_API_STRUCT_SIZE_INCORRECT;
254 return (IV_FAIL);
255 }
256
257 if(ps_op->s_ivd_num_mem_rec_op_t.u4_size
258 != sizeof(ih264d_num_mem_rec_op_t))
259 {
260 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1
261 << IVD_UNSUPPORTEDPARAM;
262 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |=
263 IVD_OP_API_STRUCT_SIZE_INCORRECT;
264 return (IV_FAIL);
265 }
266 }
267 break;
268 case IV_CMD_FILL_NUM_MEM_REC:
269 {
270 ih264d_fill_mem_rec_ip_t *ps_ip =
271 (ih264d_fill_mem_rec_ip_t *)pv_api_ip;
272 ih264d_fill_mem_rec_op_t *ps_op =
273 (ih264d_fill_mem_rec_op_t *)pv_api_op;
274 iv_mem_rec_t *ps_mem_rec;
275 WORD32 max_wd = ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd;
276 WORD32 max_ht = ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht;
277
278 max_wd = ALIGN16(max_wd);
279 max_ht = ALIGN32(max_ht);
280
281 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0;
282
283 if((ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size
284 > sizeof(ih264d_fill_mem_rec_ip_t))
285 || (ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size
286 < sizeof(iv_fill_mem_rec_ip_t)))
287 {
288 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
289 << IVD_UNSUPPORTEDPARAM;
290 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
291 IVD_IP_API_STRUCT_SIZE_INCORRECT;
292 return (IV_FAIL);
293 }
294
295 if((ps_op->s_ivd_fill_mem_rec_op_t.u4_size
296 != sizeof(ih264d_fill_mem_rec_op_t))
297 && (ps_op->s_ivd_fill_mem_rec_op_t.u4_size
298 != sizeof(iv_fill_mem_rec_op_t)))
299 {
300 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
301 << IVD_UNSUPPORTEDPARAM;
302 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
303 IVD_OP_API_STRUCT_SIZE_INCORRECT;
304 return (IV_FAIL);
305 }
306
307 if(max_wd < H264_MIN_FRAME_WIDTH)
308 {
309 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
310 << IVD_UNSUPPORTEDPARAM;
311 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
312 IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
313 return (IV_FAIL);
314 }
315
316 if(max_wd > H264_MAX_FRAME_WIDTH)
317 {
318 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
319 << IVD_UNSUPPORTEDPARAM;
320 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
321 IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
322 return (IV_FAIL);
323 }
324
325 if(max_ht < H264_MIN_FRAME_HEIGHT)
326 {
327 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
328 << IVD_UNSUPPORTEDPARAM;
329 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
330 IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
331 return (IV_FAIL);
332 }
333
334 if((max_ht * max_wd)
335 > (H264_MAX_FRAME_HEIGHT * H264_MAX_FRAME_WIDTH))
336
337 {
338 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
339 << IVD_UNSUPPORTEDPARAM;
340 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
341 IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
342 return (IV_FAIL);
343 }
344
345 if(NULL == ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location)
346 {
347 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
348 << IVD_UNSUPPORTEDPARAM;
349 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
350 IVD_NUM_REC_NOT_SUFFICIENT;
351 return (IV_FAIL);
352 }
353
354 /* check memrecords sizes are correct */
355 ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
356 for(i = 0; i < MEM_REC_CNT; i++)
357 {
358 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
359 {
360 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
361 << IVD_UNSUPPORTEDPARAM;
362 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
363 IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
364 return IV_FAIL;
365 }
366 }
367 }
368 break;
369
370 case IV_CMD_INIT:
371 {
372 ih264d_init_ip_t *ps_ip = (ih264d_init_ip_t *)pv_api_ip;
373 ih264d_init_op_t *ps_op = (ih264d_init_op_t *)pv_api_op;
374 iv_mem_rec_t *ps_mem_rec;
375 WORD32 max_wd = ps_ip->s_ivd_init_ip_t.u4_frm_max_wd;
376 WORD32 max_ht = ps_ip->s_ivd_init_ip_t.u4_frm_max_ht;
377
378 max_wd = ALIGN16(max_wd);
379 max_ht = ALIGN32(max_ht);
380
381 ps_op->s_ivd_init_op_t.u4_error_code = 0;
382
383 if((ps_ip->s_ivd_init_ip_t.u4_size > sizeof(ih264d_init_ip_t))
384 || (ps_ip->s_ivd_init_ip_t.u4_size
385 < sizeof(ivd_init_ip_t)))
386 {
387 ps_op->s_ivd_init_op_t.u4_error_code |= 1
388 << IVD_UNSUPPORTEDPARAM;
389 ps_op->s_ivd_init_op_t.u4_error_code |=
390 IVD_IP_API_STRUCT_SIZE_INCORRECT;
391 H264_DEC_DEBUG_PRINT("\n");
392 return (IV_FAIL);
393 }
394
395 if((ps_op->s_ivd_init_op_t.u4_size != sizeof(ih264d_init_op_t))
396 && (ps_op->s_ivd_init_op_t.u4_size
397 != sizeof(ivd_init_op_t)))
398 {
399 ps_op->s_ivd_init_op_t.u4_error_code |= 1
400 << IVD_UNSUPPORTEDPARAM;
401 ps_op->s_ivd_init_op_t.u4_error_code |=
402 IVD_OP_API_STRUCT_SIZE_INCORRECT;
403 H264_DEC_DEBUG_PRINT("\n");
404 return (IV_FAIL);
405 }
406
407 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec != MEM_REC_CNT)
408 {
409 ps_op->s_ivd_init_op_t.u4_error_code |= 1
410 << IVD_UNSUPPORTEDPARAM;
411 ps_op->s_ivd_init_op_t.u4_error_code |=
412 IVD_INIT_DEC_NOT_SUFFICIENT;
413 H264_DEC_DEBUG_PRINT("\n");
414 return (IV_FAIL);
415 }
416
417 if(max_wd < H264_MIN_FRAME_WIDTH)
418 {
419 ps_op->s_ivd_init_op_t.u4_error_code |= 1
420 << IVD_UNSUPPORTEDPARAM;
421 ps_op->s_ivd_init_op_t.u4_error_code |=
422 IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
423 H264_DEC_DEBUG_PRINT("\n");
424 return (IV_FAIL);
425 }
426
427 if(max_wd > H264_MAX_FRAME_WIDTH)
428 {
429 ps_op->s_ivd_init_op_t.u4_error_code |= 1
430 << IVD_UNSUPPORTEDPARAM;
431 ps_op->s_ivd_init_op_t.u4_error_code |=
432 IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
433 H264_DEC_DEBUG_PRINT("\n");
434 return (IV_FAIL);
435 }
436
437 if(max_ht < H264_MIN_FRAME_HEIGHT)
438 {
439 ps_op->s_ivd_init_op_t.u4_error_code |= 1
440 << IVD_UNSUPPORTEDPARAM;
441 ps_op->s_ivd_init_op_t.u4_error_code |=
442 IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
443 H264_DEC_DEBUG_PRINT("\n");
444 return (IV_FAIL);
445 }
446
447 if((max_ht * max_wd)
448 > (H264_MAX_FRAME_HEIGHT * H264_MAX_FRAME_WIDTH))
449
450 {
451 ps_op->s_ivd_init_op_t.u4_error_code |= 1
452 << IVD_UNSUPPORTEDPARAM;
453 ps_op->s_ivd_init_op_t.u4_error_code |=
454 IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
455 H264_DEC_DEBUG_PRINT("\n");
456 return (IV_FAIL);
457 }
458
459 if(NULL == ps_ip->s_ivd_init_ip_t.pv_mem_rec_location)
460 {
461 ps_op->s_ivd_init_op_t.u4_error_code |= 1
462 << IVD_UNSUPPORTEDPARAM;
463 ps_op->s_ivd_init_op_t.u4_error_code |=
464 IVD_NUM_REC_NOT_SUFFICIENT;
465 H264_DEC_DEBUG_PRINT("\n");
466 return (IV_FAIL);
467 }
468
469 if((ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P)
470 && (ps_ip->s_ivd_init_ip_t.e_output_format
471 != IV_YUV_422ILE)
472 && (ps_ip->s_ivd_init_ip_t.e_output_format
473 != IV_RGB_565)
474 && (ps_ip->s_ivd_init_ip_t.e_output_format
475 != IV_YUV_420SP_UV)
476 && (ps_ip->s_ivd_init_ip_t.e_output_format
477 != IV_YUV_420SP_VU))
478 {
479 ps_op->s_ivd_init_op_t.u4_error_code |= 1
480 << IVD_UNSUPPORTEDPARAM;
481 ps_op->s_ivd_init_op_t.u4_error_code |=
482 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
483 H264_DEC_DEBUG_PRINT("\n");
484 return (IV_FAIL);
485 }
486
487 /* verify number of mem records */
488 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec < MEM_REC_CNT)
489 {
490 ps_op->s_ivd_init_op_t.u4_error_code |= 1
491 << IVD_UNSUPPORTEDPARAM;
492 ps_op->s_ivd_init_op_t.u4_error_code |=
493 IVD_INIT_DEC_MEM_REC_NOT_SUFFICIENT;
494 H264_DEC_DEBUG_PRINT("\n");
495 return IV_FAIL;
496 }
497
498 ps_mem_rec = ps_ip->s_ivd_init_ip_t.pv_mem_rec_location;
499 /* check memrecords sizes are correct */
500 for(i = 0; i < ps_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++)
501 {
502 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
503 {
504 ps_op->s_ivd_init_op_t.u4_error_code |= 1
505 << IVD_UNSUPPORTEDPARAM;
506 ps_op->s_ivd_init_op_t.u4_error_code |=
507 IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
508 H264_DEC_DEBUG_PRINT("i: %d\n", i);
509 return IV_FAIL;
510 }
511 /* check memrecords pointers are not NULL */
512
513 if(ps_mem_rec[i].pv_base == NULL)
514 {
515
516 ps_op->s_ivd_init_op_t.u4_error_code |= 1
517 << IVD_UNSUPPORTEDPARAM;
518 ps_op->s_ivd_init_op_t.u4_error_code |=
519 IVD_INIT_DEC_MEM_REC_BASE_NULL;
520 H264_DEC_DEBUG_PRINT("i: %d\n", i);
521 return IV_FAIL;
522
523 }
524
525 }
526
527 /* verify memtabs for overlapping regions */
528 {
529 void *start[MEM_REC_CNT];
530 void *end[MEM_REC_CNT];
531
532 start[0] = (void *)(ps_mem_rec[0].pv_base);
533 end[0] = (void *)((UWORD8 *)ps_mem_rec[0].pv_base
534 + ps_mem_rec[0].u4_mem_size - 1);
535 for(i = 1; i < MEM_REC_CNT; i++)
536 {
537 /* This array is populated to check memtab overlapp */
538 start[i] = (void *)(ps_mem_rec[i].pv_base);
539 end[i] = (void *)((UWORD8 *)ps_mem_rec[i].pv_base
540 + ps_mem_rec[i].u4_mem_size - 1);
541
542 for(j = 0; j < i; j++)
543 {
544 if((start[i] >= start[j]) && (start[i] <= end[j]))
545 {
546 ps_op->s_ivd_init_op_t.u4_error_code |= 1
547 << IVD_UNSUPPORTEDPARAM;
548 ps_op->s_ivd_init_op_t.u4_error_code |=
549 IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
550 H264_DEC_DEBUG_PRINT("i: %d, j: %d\n", i, j);
551 return IV_FAIL;
552 }
553
554 if((end[i] >= start[j]) && (end[i] <= end[j]))
555 {
556 ps_op->s_ivd_init_op_t.u4_error_code |= 1
557 << IVD_UNSUPPORTEDPARAM;
558 ps_op->s_ivd_init_op_t.u4_error_code |=
559 IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
560 H264_DEC_DEBUG_PRINT("i: %d, j: %d\n", i, j);
561 return IV_FAIL;
562 }
563
564 if((start[i] < start[j]) && (end[i] > end[j]))
565 {
566 ps_op->s_ivd_init_op_t.u4_error_code |= 1
567 << IVD_UNSUPPORTEDPARAM;
568 ps_op->s_ivd_init_op_t.u4_error_code |=
569 IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
570 H264_DEC_DEBUG_PRINT("i: %d, j: %d\n", i, j);
571 return IV_FAIL;
572 }
573 }
574
575 }
576 }
577
578 {
579 iv_mem_rec_t mem_rec_ittiam_api[MEM_REC_CNT];
580 ih264d_fill_mem_rec_ip_t s_fill_mem_rec_ip;
581 ih264d_fill_mem_rec_op_t s_fill_mem_rec_op;
582 IV_API_CALL_STATUS_T e_status;
583
584 UWORD32 i;
585 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.e_cmd =
586 IV_CMD_FILL_NUM_MEM_REC;
587 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location =
588 mem_rec_ittiam_api;
589 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd =
590 max_wd;
591 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht =
592 max_ht;
593
594 if(ps_ip->s_ivd_init_ip_t.u4_size
595 > offsetof(ih264d_init_ip_t, i4_level))
596 {
597 s_fill_mem_rec_ip.i4_level = ps_ip->i4_level;
598 }
599 else
600 {
601 s_fill_mem_rec_ip.i4_level = H264_LEVEL_3_1;
602 }
603
604 if(ps_ip->s_ivd_init_ip_t.u4_size
605 > offsetof(ih264d_init_ip_t, u4_num_ref_frames))
606 {
607 s_fill_mem_rec_ip.u4_num_ref_frames =
608 ps_ip->u4_num_ref_frames;
609 }
610 else
611 {
612 s_fill_mem_rec_ip.u4_num_ref_frames =
613 (H264_MAX_REF_PICS + 1);
614 }
615
616 if(ps_ip->s_ivd_init_ip_t.u4_size
617 > offsetof(ih264d_init_ip_t,
618 u4_num_reorder_frames))
619 {
620 s_fill_mem_rec_ip.u4_num_reorder_frames =
621 ps_ip->u4_num_reorder_frames;
622 }
623 else
624 {
625 s_fill_mem_rec_ip.u4_num_reorder_frames = (H264_MAX_REF_PICS
626 + 1);
627 }
628
629 if(ps_ip->s_ivd_init_ip_t.u4_size
630 > offsetof(ih264d_init_ip_t,
631 u4_num_extra_disp_buf))
632 {
633 s_fill_mem_rec_ip.u4_num_extra_disp_buf =
634 ps_ip->u4_num_extra_disp_buf;
635 }
636 else
637 {
638 s_fill_mem_rec_ip.u4_num_extra_disp_buf = 0;
639 }
640
641 if(ps_ip->s_ivd_init_ip_t.u4_size
642 > offsetof(ih264d_init_ip_t, u4_share_disp_buf))
643 {
644 #ifndef LOGO_EN
645 s_fill_mem_rec_ip.u4_share_disp_buf =
646 ps_ip->u4_share_disp_buf;
647 #else
648 s_fill_mem_rec_ip.u4_share_disp_buf = 0;
649 #endif
650 }
651 else
652 {
653 s_fill_mem_rec_ip.u4_share_disp_buf = 0;
654 }
655
656 s_fill_mem_rec_ip.e_output_format =
657 ps_ip->s_ivd_init_ip_t.e_output_format;
658
659 if((s_fill_mem_rec_ip.e_output_format != IV_YUV_420P)
660 && (s_fill_mem_rec_ip.e_output_format
661 != IV_YUV_420SP_UV)
662 && (s_fill_mem_rec_ip.e_output_format
663 != IV_YUV_420SP_VU))
664 {
665 s_fill_mem_rec_ip.u4_share_disp_buf = 0;
666 }
667
668 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_size =
669 sizeof(ih264d_fill_mem_rec_ip_t);
670 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_size =
671 sizeof(ih264d_fill_mem_rec_op_t);
672
673 for(i = 0; i < MEM_REC_CNT; i++)
674 mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t);
675
676 e_status = ih264d_api_function(NULL,
677 (void *)&s_fill_mem_rec_ip,
678 (void *)&s_fill_mem_rec_op);
679 if(IV_FAIL == e_status)
680 {
681 ps_op->s_ivd_init_op_t.u4_error_code =
682 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_error_code;
683 H264_DEC_DEBUG_PRINT("Fail\n");
684 return (IV_FAIL);
685 }
686
687 for(i = 0; i < MEM_REC_CNT; i++)
688 {
689 if(ps_mem_rec[i].u4_mem_size
690 < mem_rec_ittiam_api[i].u4_mem_size)
691 {
692 ps_op->s_ivd_init_op_t.u4_error_code |= 1
693 << IVD_UNSUPPORTEDPARAM;
694 ps_op->s_ivd_init_op_t.u4_error_code |=
695 IVD_INIT_DEC_MEM_REC_INSUFFICIENT_SIZE;
696 H264_DEC_DEBUG_PRINT("i: %d \n", i);
697 return IV_FAIL;
698 }
699 if(ps_mem_rec[i].u4_mem_alignment
700 != mem_rec_ittiam_api[i].u4_mem_alignment)
701 {
702 ps_op->s_ivd_init_op_t.u4_error_code |= 1
703 << IVD_UNSUPPORTEDPARAM;
704 ps_op->s_ivd_init_op_t.u4_error_code |=
705 IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR;
706 H264_DEC_DEBUG_PRINT("i: %d \n", i);
707 return IV_FAIL;
708 }
709 if(ps_mem_rec[i].e_mem_type
710 != mem_rec_ittiam_api[i].e_mem_type)
711 {
712 UWORD32 check = IV_SUCCESS;
713 UWORD32 diff = mem_rec_ittiam_api[i].e_mem_type
714 - ps_mem_rec[i].e_mem_type;
715
716 if((ps_mem_rec[i].e_mem_type
717 <= IV_EXTERNAL_CACHEABLE_SCRATCH_MEM)
718 && (mem_rec_ittiam_api[i].e_mem_type
719 >= IV_INTERNAL_NONCACHEABLE_PERSISTENT_MEM))
720 {
721 check = IV_FAIL;
722 }
723 if(3 != MOD(mem_rec_ittiam_api[i].e_mem_type, 4))
724 {
725 /*
726 * It is not IV_EXTERNAL_NONCACHEABLE_PERSISTENT_MEM or IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM
727 */
728 if((diff < 1) || (diff > 3))
729 {
730 // Difference between 1 and 3 is okay for all cases other than the two filtered
731 // with the MOD condition above
732 check = IV_FAIL;
733 }
734 }
735 else
736 {
737 if(diff == 1)
738 {
739 /*
740 * This particular case is when codec asked for External Persistent, but got
741 * Internal Scratch.
742 */
743 check = IV_FAIL;
744 }
745 if((diff != 2) && (diff != 3))
746 {
747 check = IV_FAIL;
748 }
749 }
750 if(check == IV_FAIL)
751 {
752 ps_op->s_ivd_init_op_t.u4_error_code |= 1
753 << IVD_UNSUPPORTEDPARAM;
754 ps_op->s_ivd_init_op_t.u4_error_code |=
755 IVD_INIT_DEC_MEM_REC_INCORRECT_TYPE;
756 H264_DEC_DEBUG_PRINT("i: %d \n", i);
757 return IV_FAIL;
758 }
759 }
760 }
761 }
762
763 }
764 break;
765
766 case IVD_CMD_GET_DISPLAY_FRAME:
767 {
768 ih264d_get_display_frame_ip_t *ps_ip =
769 (ih264d_get_display_frame_ip_t *)pv_api_ip;
770 ih264d_get_display_frame_op_t *ps_op =
771 (ih264d_get_display_frame_op_t *)pv_api_op;
772
773 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0;
774
775 if((ps_ip->s_ivd_get_display_frame_ip_t.u4_size
776 != sizeof(ih264d_get_display_frame_ip_t))
777 && (ps_ip->s_ivd_get_display_frame_ip_t.u4_size
778 != sizeof(ivd_get_display_frame_ip_t)))
779 {
780 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
781 << IVD_UNSUPPORTEDPARAM;
782 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
783 IVD_IP_API_STRUCT_SIZE_INCORRECT;
784 return (IV_FAIL);
785 }
786
787 if((ps_op->s_ivd_get_display_frame_op_t.u4_size
788 != sizeof(ih264d_get_display_frame_op_t))
789 && (ps_op->s_ivd_get_display_frame_op_t.u4_size
790 != sizeof(ivd_get_display_frame_op_t)))
791 {
792 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
793 << IVD_UNSUPPORTEDPARAM;
794 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
795 IVD_OP_API_STRUCT_SIZE_INCORRECT;
796 return (IV_FAIL);
797 }
798 }
799 break;
800
801 case IVD_CMD_REL_DISPLAY_FRAME:
802 {
803 ih264d_rel_display_frame_ip_t *ps_ip =
804 (ih264d_rel_display_frame_ip_t *)pv_api_ip;
805 ih264d_rel_display_frame_op_t *ps_op =
806 (ih264d_rel_display_frame_op_t *)pv_api_op;
807
808 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0;
809
810 if((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
811 != sizeof(ih264d_rel_display_frame_ip_t))
812 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
813 != sizeof(ivd_rel_display_frame_ip_t)))
814 {
815 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
816 << IVD_UNSUPPORTEDPARAM;
817 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
818 IVD_IP_API_STRUCT_SIZE_INCORRECT;
819 return (IV_FAIL);
820 }
821
822 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size
823 != sizeof(ih264d_rel_display_frame_op_t))
824 && (ps_op->s_ivd_rel_display_frame_op_t.u4_size
825 != sizeof(ivd_rel_display_frame_op_t)))
826 {
827 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
828 << IVD_UNSUPPORTEDPARAM;
829 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
830 IVD_OP_API_STRUCT_SIZE_INCORRECT;
831 return (IV_FAIL);
832 }
833
834 }
835 break;
836
837 case IVD_CMD_SET_DISPLAY_FRAME:
838 {
839 ih264d_set_display_frame_ip_t *ps_ip =
840 (ih264d_set_display_frame_ip_t *)pv_api_ip;
841 ih264d_set_display_frame_op_t *ps_op =
842 (ih264d_set_display_frame_op_t *)pv_api_op;
843 UWORD32 j;
844
845 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0;
846
847 if((ps_ip->s_ivd_set_display_frame_ip_t.u4_size
848 != sizeof(ih264d_set_display_frame_ip_t))
849 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size
850 != sizeof(ivd_set_display_frame_ip_t)))
851 {
852 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
853 << IVD_UNSUPPORTEDPARAM;
854 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
855 IVD_IP_API_STRUCT_SIZE_INCORRECT;
856 return (IV_FAIL);
857 }
858
859 if((ps_op->s_ivd_set_display_frame_op_t.u4_size
860 != sizeof(ih264d_set_display_frame_op_t))
861 && (ps_op->s_ivd_set_display_frame_op_t.u4_size
862 != sizeof(ivd_set_display_frame_op_t)))
863 {
864 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
865 << IVD_UNSUPPORTEDPARAM;
866 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
867 IVD_OP_API_STRUCT_SIZE_INCORRECT;
868 return (IV_FAIL);
869 }
870
871 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0)
872 {
873 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
874 << IVD_UNSUPPORTEDPARAM;
875 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
876 IVD_DISP_FRM_ZERO_OP_BUFS;
877 return IV_FAIL;
878 }
879
880 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs;
881 j++)
882 {
883 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs
884 == 0)
885 {
886 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
887 << IVD_UNSUPPORTEDPARAM;
888 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
889 IVD_DISP_FRM_ZERO_OP_BUFS;
890 return IV_FAIL;
891 }
892
893 for(i = 0;
894 i
895 < ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs;
896 i++)
897 {
898 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i]
899 == NULL)
900 {
901 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
902 << IVD_UNSUPPORTEDPARAM;
903 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
904 IVD_DISP_FRM_OP_BUF_NULL;
905 return IV_FAIL;
906 }
907
908 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i]
909 == 0)
910 {
911 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
912 << IVD_UNSUPPORTEDPARAM;
913 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
914 IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
915 return IV_FAIL;
916 }
917 }
918 }
919 }
920 break;
921
922 case IVD_CMD_VIDEO_DECODE:
923 {
924 ih264d_video_decode_ip_t *ps_ip =
925 (ih264d_video_decode_ip_t *)pv_api_ip;
926 ih264d_video_decode_op_t *ps_op =
927 (ih264d_video_decode_op_t *)pv_api_op;
928
929 H264_DEC_DEBUG_PRINT("The input bytes is: %d",
930 ps_ip->s_ivd_video_decode_ip_t.u4_num_Bytes);
931 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0;
932
933 if(ps_ip->s_ivd_video_decode_ip_t.u4_size
934 != sizeof(ih264d_video_decode_ip_t)&&
935 ps_ip->s_ivd_video_decode_ip_t.u4_size != offsetof(ivd_video_decode_ip_t, s_out_buffer))
936 {
937 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
938 << IVD_UNSUPPORTEDPARAM;
939 ps_op->s_ivd_video_decode_op_t.u4_error_code |=
940 IVD_IP_API_STRUCT_SIZE_INCORRECT;
941 return (IV_FAIL);
942 }
943
944 if(ps_op->s_ivd_video_decode_op_t.u4_size
945 != sizeof(ih264d_video_decode_op_t)&&
946 ps_op->s_ivd_video_decode_op_t.u4_size != offsetof(ivd_video_decode_op_t, u4_output_present))
947 {
948 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
949 << IVD_UNSUPPORTEDPARAM;
950 ps_op->s_ivd_video_decode_op_t.u4_error_code |=
951 IVD_OP_API_STRUCT_SIZE_INCORRECT;
952 return (IV_FAIL);
953 }
954
955 }
956 break;
957
958 case IV_CMD_RETRIEVE_MEMREC:
959 {
960 ih264d_retrieve_mem_rec_ip_t *ps_ip =
961 (ih264d_retrieve_mem_rec_ip_t *)pv_api_ip;
962 ih264d_retrieve_mem_rec_op_t *ps_op =
963 (ih264d_retrieve_mem_rec_op_t *)pv_api_op;
964 iv_mem_rec_t *ps_mem_rec;
965
966 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = 0;
967
968 if(ps_ip->s_ivd_retrieve_mem_rec_ip_t.u4_size
969 != sizeof(ih264d_retrieve_mem_rec_ip_t))
970 {
971 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1
972 << IVD_UNSUPPORTEDPARAM;
973 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |=
974 IVD_IP_API_STRUCT_SIZE_INCORRECT;
975 return (IV_FAIL);
976 }
977
978 if(ps_op->s_ivd_retrieve_mem_rec_op_t.u4_size
979 != sizeof(ih264d_retrieve_mem_rec_op_t))
980 {
981 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1
982 << IVD_UNSUPPORTEDPARAM;
983 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |=
984 IVD_OP_API_STRUCT_SIZE_INCORRECT;
985 return (IV_FAIL);
986 }
987
988 ps_mem_rec = ps_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location;
989 /* check memrecords sizes are correct */
990 for(i = 0; i < MEM_REC_CNT; i++)
991 {
992 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
993 {
994 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1
995 << IVD_UNSUPPORTEDPARAM;
996 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |=
997 IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
998 return IV_FAIL;
999 }
1000 }
1001 }
1002 break;
1003
1004 case IVD_CMD_VIDEO_CTL:
1005 {
1006 UWORD32 *pu4_ptr_cmd;
1007 UWORD32 sub_command;
1008
1009 pu4_ptr_cmd = (UWORD32 *)pv_api_ip;
1010 pu4_ptr_cmd += 2;
1011 sub_command = *pu4_ptr_cmd;
1012
1013 switch(sub_command)
1014 {
1015 case IVD_CMD_CTL_SETPARAMS:
1016 {
1017 ih264d_ctl_set_config_ip_t *ps_ip;
1018 ih264d_ctl_set_config_op_t *ps_op;
1019 ps_ip = (ih264d_ctl_set_config_ip_t *)pv_api_ip;
1020 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op;
1021
1022 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size
1023 != sizeof(ih264d_ctl_set_config_ip_t))
1024 {
1025 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
1026 << IVD_UNSUPPORTEDPARAM;
1027 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
1028 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1029 return IV_FAIL;
1030 }
1031 }
1032 //no break; is needed here
1033 case IVD_CMD_CTL_SETDEFAULT:
1034 {
1035 ih264d_ctl_set_config_op_t *ps_op;
1036 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op;
1037 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size
1038 != sizeof(ih264d_ctl_set_config_op_t))
1039 {
1040 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
1041 << IVD_UNSUPPORTEDPARAM;
1042 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
1043 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1044 return IV_FAIL;
1045 }
1046 }
1047 break;
1048
1049 case IVD_CMD_CTL_GETPARAMS:
1050 {
1051 ih264d_ctl_getstatus_ip_t *ps_ip;
1052 ih264d_ctl_getstatus_op_t *ps_op;
1053
1054 ps_ip = (ih264d_ctl_getstatus_ip_t *)pv_api_ip;
1055 ps_op = (ih264d_ctl_getstatus_op_t *)pv_api_op;
1056 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size
1057 != sizeof(ih264d_ctl_getstatus_ip_t))
1058 {
1059 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
1060 << IVD_UNSUPPORTEDPARAM;
1061 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
1062 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1063 return IV_FAIL;
1064 }
1065 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size
1066 != sizeof(ih264d_ctl_getstatus_op_t))
1067 {
1068 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
1069 << IVD_UNSUPPORTEDPARAM;
1070 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
1071 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1072 return IV_FAIL;
1073 }
1074 }
1075 break;
1076
1077 case IVD_CMD_CTL_GETBUFINFO:
1078 {
1079 ih264d_ctl_getbufinfo_ip_t *ps_ip;
1080 ih264d_ctl_getbufinfo_op_t *ps_op;
1081 ps_ip = (ih264d_ctl_getbufinfo_ip_t *)pv_api_ip;
1082 ps_op = (ih264d_ctl_getbufinfo_op_t *)pv_api_op;
1083
1084 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size
1085 != sizeof(ih264d_ctl_getbufinfo_ip_t))
1086 {
1087 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
1088 << IVD_UNSUPPORTEDPARAM;
1089 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
1090 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1091 return IV_FAIL;
1092 }
1093 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size
1094 != sizeof(ih264d_ctl_getbufinfo_op_t))
1095 {
1096 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
1097 << IVD_UNSUPPORTEDPARAM;
1098 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
1099 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1100 return IV_FAIL;
1101 }
1102 }
1103 break;
1104
1105 case IVD_CMD_CTL_GETVERSION:
1106 {
1107 ih264d_ctl_getversioninfo_ip_t *ps_ip;
1108 ih264d_ctl_getversioninfo_op_t *ps_op;
1109 ps_ip = (ih264d_ctl_getversioninfo_ip_t *)pv_api_ip;
1110 ps_op = (ih264d_ctl_getversioninfo_op_t *)pv_api_op;
1111 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size
1112 != sizeof(ih264d_ctl_getversioninfo_ip_t))
1113 {
1114 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
1115 << IVD_UNSUPPORTEDPARAM;
1116 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
1117 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1118 return IV_FAIL;
1119 }
1120 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size
1121 != sizeof(ih264d_ctl_getversioninfo_op_t))
1122 {
1123 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
1124 << IVD_UNSUPPORTEDPARAM;
1125 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
1126 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1127 return IV_FAIL;
1128 }
1129 }
1130 break;
1131
1132 case IVD_CMD_CTL_FLUSH:
1133 {
1134 ih264d_ctl_flush_ip_t *ps_ip;
1135 ih264d_ctl_flush_op_t *ps_op;
1136 ps_ip = (ih264d_ctl_flush_ip_t *)pv_api_ip;
1137 ps_op = (ih264d_ctl_flush_op_t *)pv_api_op;
1138 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size
1139 != sizeof(ih264d_ctl_flush_ip_t))
1140 {
1141 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
1142 << IVD_UNSUPPORTEDPARAM;
1143 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
1144 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1145 return IV_FAIL;
1146 }
1147 if(ps_op->s_ivd_ctl_flush_op_t.u4_size
1148 != sizeof(ih264d_ctl_flush_op_t))
1149 {
1150 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
1151 << IVD_UNSUPPORTEDPARAM;
1152 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
1153 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1154 return IV_FAIL;
1155 }
1156 }
1157 break;
1158
1159 case IVD_CMD_CTL_RESET:
1160 {
1161 ih264d_ctl_reset_ip_t *ps_ip;
1162 ih264d_ctl_reset_op_t *ps_op;
1163 ps_ip = (ih264d_ctl_reset_ip_t *)pv_api_ip;
1164 ps_op = (ih264d_ctl_reset_op_t *)pv_api_op;
1165 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size
1166 != sizeof(ih264d_ctl_reset_ip_t))
1167 {
1168 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
1169 << IVD_UNSUPPORTEDPARAM;
1170 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
1171 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1172 return IV_FAIL;
1173 }
1174 if(ps_op->s_ivd_ctl_reset_op_t.u4_size
1175 != sizeof(ih264d_ctl_reset_op_t))
1176 {
1177 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
1178 << IVD_UNSUPPORTEDPARAM;
1179 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
1180 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1181 return IV_FAIL;
1182 }
1183 }
1184 break;
1185
1186 case IH264D_CMD_CTL_DEGRADE:
1187 {
1188 ih264d_ctl_degrade_ip_t *ps_ip;
1189 ih264d_ctl_degrade_op_t *ps_op;
1190
1191 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip;
1192 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op;
1193
1194 if(ps_ip->u4_size != sizeof(ih264d_ctl_degrade_ip_t))
1195 {
1196 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1197 ps_op->u4_error_code |=
1198 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1199 return IV_FAIL;
1200 }
1201
1202 if(ps_op->u4_size != sizeof(ih264d_ctl_degrade_op_t))
1203 {
1204 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1205 ps_op->u4_error_code |=
1206 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1207 return IV_FAIL;
1208 }
1209
1210 if((ps_ip->i4_degrade_pics < 0)
1211 || (ps_ip->i4_degrade_pics > 4)
1212 || (ps_ip->i4_nondegrade_interval < 0)
1213 || (ps_ip->i4_degrade_type < 0)
1214 || (ps_ip->i4_degrade_type > 15))
1215 {
1216 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1217 return IV_FAIL;
1218 }
1219
1220 break;
1221 }
1222
1223 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS:
1224 {
1225 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip;
1226 ih264d_ctl_get_frame_dimensions_op_t *ps_op;
1227
1228 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
1229 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op;
1230
1231 if(ps_ip->u4_size
1232 != sizeof(ih264d_ctl_get_frame_dimensions_ip_t))
1233 {
1234 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1235 ps_op->u4_error_code |=
1236 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1237 return IV_FAIL;
1238 }
1239
1240 if(ps_op->u4_size
1241 != sizeof(ih264d_ctl_get_frame_dimensions_op_t))
1242 {
1243 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1244 ps_op->u4_error_code |=
1245 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1246 return IV_FAIL;
1247 }
1248
1249 break;
1250 }
1251
1252 case IH264D_CMD_CTL_SET_NUM_CORES:
1253 {
1254 ih264d_ctl_set_num_cores_ip_t *ps_ip;
1255 ih264d_ctl_set_num_cores_op_t *ps_op;
1256
1257 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip;
1258 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op;
1259
1260 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_num_cores_ip_t))
1261 {
1262 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1263 ps_op->u4_error_code |=
1264 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1265 return IV_FAIL;
1266 }
1267
1268 if(ps_op->u4_size != sizeof(ih264d_ctl_set_num_cores_op_t))
1269 {
1270 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1271 ps_op->u4_error_code |=
1272 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1273 return IV_FAIL;
1274 }
1275
1276 if((ps_ip->u4_num_cores != 1) && (ps_ip->u4_num_cores != 2)
1277 && (ps_ip->u4_num_cores != 3)
1278 && (ps_ip->u4_num_cores != 4))
1279 {
1280 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1281 return IV_FAIL;
1282 }
1283 break;
1284 }
1285 case IH264D_CMD_CTL_SET_PROCESSOR:
1286 {
1287 ih264d_ctl_set_processor_ip_t *ps_ip;
1288 ih264d_ctl_set_processor_op_t *ps_op;
1289
1290 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip;
1291 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op;
1292
1293 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_processor_ip_t))
1294 {
1295 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1296 ps_op->u4_error_code |=
1297 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1298 return IV_FAIL;
1299 }
1300
1301 if(ps_op->u4_size != sizeof(ih264d_ctl_set_processor_op_t))
1302 {
1303 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1304 ps_op->u4_error_code |=
1305 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1306 return IV_FAIL;
1307 }
1308
1309 break;
1310 }
1311 default:
1312 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
1313 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD;
1314 return IV_FAIL;
1315 break;
1316 }
1317 }
1318 break;
1319 }
1320
1321 return IV_SUCCESS;
1322 }
1323
1324
1325 /**
1326 *******************************************************************************
1327 *
1328 * @brief
1329 * Sets Processor type
1330 *
1331 * @par Description:
1332 * Sets Processor type
1333 *
1334 * @param[in] ps_codec_obj
1335 * Pointer to codec object at API level
1336 *
1337 * @param[in] pv_api_ip
1338 * Pointer to input argument structure
1339 *
1340 * @param[out] pv_api_op
1341 * Pointer to output argument structure
1342 *
1343 * @returns Status
1344 *
1345 * @remarks
1346 *
1347 *
1348 *******************************************************************************
1349 */
1350
ih264d_set_processor(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)1351 WORD32 ih264d_set_processor(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
1352 {
1353 ih264d_ctl_set_processor_ip_t *ps_ip;
1354 ih264d_ctl_set_processor_op_t *ps_op;
1355 dec_struct_t *ps_codec = (dec_struct_t *)dec_hdl->pv_codec_handle;
1356
1357 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip;
1358 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op;
1359
1360 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch;
1361 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc;
1362
1363 ih264d_init_function_ptr(ps_codec);
1364
1365 ps_op->u4_error_code = 0;
1366 return IV_SUCCESS;
1367 }
1368 /*****************************************************************************/
1369 /* */
1370 /* Function Name : ih264d_get_num_rec */
1371 /* */
1372 /* Description : returns number of mem records required */
1373 /* */
1374 /* Inputs : pv_api_ip input api structure */
1375 /* : pv_api_op output api structure */
1376 /* Outputs : */
1377 /* Outputs : */
1378 /* Returns : void */
1379 /* */
1380 /* Issues : none */
1381 /* */
1382 /* Revision History: */
1383 /* */
1384 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1385 /* 22 10 2008 100356 Draft */
1386 /* */
1387 /*****************************************************************************/
ih264d_get_num_rec(void * pv_api_ip,void * pv_api_op)1388 WORD32 ih264d_get_num_rec(void *pv_api_ip, void *pv_api_op)
1389 {
1390 iv_num_mem_rec_ip_t *ps_mem_q_ip;
1391 iv_num_mem_rec_op_t *ps_mem_q_op;
1392 ps_mem_q_ip = (iv_num_mem_rec_ip_t *)pv_api_ip;
1393 ps_mem_q_op = (iv_num_mem_rec_op_t *)pv_api_op;
1394 UNUSED(ps_mem_q_ip);
1395 ps_mem_q_op->u4_num_mem_rec = MEM_REC_CNT;
1396
1397 return IV_SUCCESS;
1398
1399 }
1400
1401
1402 /**************************************************************************
1403 * \if Function name : ih264d_init_decoder \endif
1404 *
1405 *
1406 * \brief
1407 * Initializes the decoder
1408 *
1409 * \param apiVersion : Version of the api being used.
1410 * \param errorHandlingMechanism : Mechanism to be used for errror handling.
1411 * \param postFilteringType: Type of post filtering operation to be used.
1412 * \param uc_outputFormat: Format of the decoded picture [default 4:2:0].
1413 * \param uc_dispBufs: Number of Display Buffers.
1414 * \param p_NALBufAPI: Pointer to NAL Buffer API.
1415 * \param p_DispBufAPI: Pointer to Display Buffer API.
1416 * \param ih264d_dec_mem_manager :Pointer to the function that will be called by decoder
1417 * for memory allocation and freeing.
1418 *
1419 * \return
1420 * 0 on Success and -1 on error
1421 *
1422 **************************************************************************
1423 */
ih264d_init_decoder(void * ps_dec_params)1424 void ih264d_init_decoder(void * ps_dec_params)
1425 {
1426 dec_struct_t * ps_dec = (dec_struct_t *)ps_dec_params;
1427 dec_slice_params_t *ps_cur_slice;
1428 pocstruct_t *ps_prev_poc, *ps_cur_poc;
1429
1430
1431
1432 /* Set pic_parameter_set_id to -1 */
1433
1434
1435
1436 ps_cur_slice = ps_dec->ps_cur_slice;
1437 ps_dec->init_done = 0;
1438
1439 ps_dec->u4_num_cores = 1;
1440
1441 ps_dec->u2_pic_ht = ps_dec->u2_pic_wd = 0;
1442
1443 ps_dec->u1_separate_parse = DEFAULT_SEPARATE_PARSE;
1444 ps_dec->u4_app_disable_deblk_frm = 0;
1445 ps_dec->i4_degrade_type = 0;
1446 ps_dec->i4_degrade_pics = 0;
1447
1448 ps_dec->i4_app_skip_mode = IVD_SKIP_NONE;
1449 ps_dec->i4_dec_skip_mode = IVD_SKIP_NONE;
1450
1451 memset(ps_dec->ps_pps, 0,
1452 ((sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS));
1453 memset(ps_dec->ps_sps, 0,
1454 ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS));
1455
1456 /* Initialization of function pointers ih264d_deblock_picture function*/
1457
1458 ps_dec->p_DeblockPicture[0] = ih264d_deblock_picture_non_mbaff;
1459 ps_dec->p_DeblockPicture[1] = ih264d_deblock_picture_mbaff;
1460
1461 ps_dec->s_cab_dec_env.pv_codec_handle = ps_dec;
1462
1463 ps_dec->u4_num_fld_in_frm = 0;
1464
1465 ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec;
1466
1467 /* Initialize the sei validity u4_flag with zero indiacting sei is not valid*/
1468 ps_dec->ps_sei->u1_is_valid = 0;
1469
1470 /* decParams Initializations */
1471 ps_dec->ps_cur_pps = NULL;
1472 ps_dec->ps_cur_sps = NULL;
1473 ps_dec->u1_init_dec_flag = 0;
1474 ps_dec->u1_first_slice_in_stream = 1;
1475 ps_dec->u1_first_pb_nal_in_pic = 1;
1476 ps_dec->u1_last_pic_not_decoded = 0;
1477 ps_dec->u4_app_disp_width = 0;
1478 ps_dec->i4_header_decoded = 0;
1479 ps_dec->u4_total_frames_decoded = 0;
1480
1481 ps_dec->i4_error_code = 0;
1482 ps_dec->i4_content_type = -1;
1483 ps_dec->ps_cur_slice->u1_mbaff_frame_flag = 0;
1484
1485 ps_dec->ps_dec_err_status->u1_err_flag = ACCEPT_ALL_PICS; //REJECT_PB_PICS;
1486 ps_dec->ps_dec_err_status->u1_cur_pic_type = PIC_TYPE_UNKNOWN;
1487 ps_dec->ps_dec_err_status->u4_frm_sei_sync = SYNC_FRM_DEFAULT;
1488 ps_dec->ps_dec_err_status->u4_cur_frm = INIT_FRAME;
1489 ps_dec->ps_dec_err_status->u1_pic_aud_i = PIC_TYPE_UNKNOWN;
1490
1491 ps_dec->u1_pr_sl_type = 0xFF;
1492 ps_dec->u2_mbx = 0xffff;
1493 ps_dec->u2_mby = 0;
1494 ps_dec->u2_total_mbs_coded = 0;
1495
1496 /* POC initializations */
1497 ps_prev_poc = &ps_dec->s_prev_pic_poc;
1498 ps_cur_poc = &ps_dec->s_cur_pic_poc;
1499 ps_prev_poc->i4_pic_order_cnt_lsb = ps_cur_poc->i4_pic_order_cnt_lsb = 0;
1500 ps_prev_poc->i4_pic_order_cnt_msb = ps_cur_poc->i4_pic_order_cnt_msb = 0;
1501 ps_prev_poc->i4_delta_pic_order_cnt_bottom =
1502 ps_cur_poc->i4_delta_pic_order_cnt_bottom = 0;
1503 ps_prev_poc->i4_delta_pic_order_cnt[0] =
1504 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0;
1505 ps_prev_poc->i4_delta_pic_order_cnt[1] =
1506 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0;
1507 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
1508 ps_prev_poc->i4_top_field_order_count = ps_cur_poc->i4_top_field_order_count =
1509 0;
1510 ps_prev_poc->i4_bottom_field_order_count =
1511 ps_cur_poc->i4_bottom_field_order_count = 0;
1512 ps_prev_poc->u1_bot_field = ps_cur_poc->u1_bot_field = 0;
1513 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
1514 ps_prev_poc->i4_prev_frame_num_ofst = ps_cur_poc->i4_prev_frame_num_ofst = 0;
1515 ps_cur_slice->u1_mmco_equalto5 = 0;
1516 ps_cur_slice->u2_frame_num = 0;
1517
1518 ps_dec->i4_max_poc = 0;
1519 ps_dec->i4_prev_max_display_seq = 0;
1520 ps_dec->u1_recon_mb_grp = 4;
1521
1522 /* Field PIC initializations */
1523 ps_dec->u1_second_field = 0;
1524 ps_dec->s_prev_seq_params.u1_eoseq_pending = 0;
1525
1526 /* Set the cropping parameters as zero */
1527 ps_dec->u2_crop_offset_y = 0;
1528 ps_dec->u2_crop_offset_uv = 0;
1529
1530 /* The Initial Frame Rate Info is not Present */
1531 ps_dec->i4_vui_frame_rate = -1;
1532 ps_dec->i4_pic_type = -1;
1533 ps_dec->i4_frametype = -1;
1534 ps_dec->i4_content_type = -1;
1535
1536 ps_dec->u1_res_changed = 0;
1537
1538
1539 ps_dec->u1_frame_decoded_flag = 0;
1540
1541 /* Set the default frame seek mask mode */
1542 ps_dec->u4_skip_frm_mask = SKIP_NONE;
1543
1544 /********************************************************/
1545 /* Initialize CAVLC residual decoding function pointers */
1546 /********************************************************/
1547 ps_dec->pf_cavlc_4x4res_block[0] = ih264d_cavlc_4x4res_block_totalcoeff_1;
1548 ps_dec->pf_cavlc_4x4res_block[1] =
1549 ih264d_cavlc_4x4res_block_totalcoeff_2to10;
1550 ps_dec->pf_cavlc_4x4res_block[2] =
1551 ih264d_cavlc_4x4res_block_totalcoeff_11to16;
1552
1553 ps_dec->pf_cavlc_parse4x4coeff[0] = ih264d_cavlc_parse4x4coeff_n0to7;
1554 ps_dec->pf_cavlc_parse4x4coeff[1] = ih264d_cavlc_parse4x4coeff_n8;
1555
1556 ps_dec->pf_cavlc_parse_8x8block[0] =
1557 ih264d_cavlc_parse_8x8block_none_available;
1558 ps_dec->pf_cavlc_parse_8x8block[1] =
1559 ih264d_cavlc_parse_8x8block_left_available;
1560 ps_dec->pf_cavlc_parse_8x8block[2] =
1561 ih264d_cavlc_parse_8x8block_top_available;
1562 ps_dec->pf_cavlc_parse_8x8block[3] =
1563 ih264d_cavlc_parse_8x8block_both_available;
1564
1565 /***************************************************************************/
1566 /* Initialize Bs calculation function pointers for P and B, 16x16/non16x16 */
1567 /***************************************************************************/
1568 ps_dec->pf_fill_bs1[0][0] = ih264d_fill_bs1_16x16mb_pslice;
1569 ps_dec->pf_fill_bs1[0][1] = ih264d_fill_bs1_non16x16mb_pslice;
1570
1571 ps_dec->pf_fill_bs1[1][0] = ih264d_fill_bs1_16x16mb_bslice;
1572 ps_dec->pf_fill_bs1[1][1] = ih264d_fill_bs1_non16x16mb_bslice;
1573
1574 ps_dec->pf_fill_bs_xtra_left_edge[0] =
1575 ih264d_fill_bs_xtra_left_edge_cur_frm;
1576 ps_dec->pf_fill_bs_xtra_left_edge[1] =
1577 ih264d_fill_bs_xtra_left_edge_cur_fld;
1578
1579 /* Initialize Reference Pic Buffers */
1580 ih264d_init_ref_bufs(ps_dec->ps_dpb_mgr);
1581
1582 #if VERT_SCALE_UP_AND_422
1583 ps_dec->u1_vert_up_scale_flag = 1;
1584 #else
1585 ps_dec->u1_vert_up_scale_flag = 0;
1586 #endif
1587
1588 ps_dec->u2_prv_frame_num = 0;
1589 ps_dec->u1_top_bottom_decoded = 0;
1590 ps_dec->u1_dangling_field = 0;
1591
1592 ps_dec->s_cab_dec_env.cabac_table = gau4_ih264d_cabac_table;
1593
1594 ps_dec->pu1_left_mv_ctxt_inc = ps_dec->u1_left_mv_ctxt_inc_arr[0];
1595 ps_dec->pi1_left_ref_idx_ctxt_inc =
1596 &ps_dec->i1_left_ref_idx_ctx_inc_arr[0][0];
1597 ps_dec->pu1_left_yuv_dc_csbp = &ps_dec->u1_yuv_dc_csbp_topmb;
1598
1599 /* ! */
1600 /* Initializing flush frame u4_flag */
1601 ps_dec->u1_flushfrm = 0;
1602
1603 {
1604 ps_dec->s_cab_dec_env.pv_codec_handle = (void*)ps_dec;
1605 ps_dec->ps_bitstrm->pv_codec_handle = (void*)ps_dec;
1606 ps_dec->ps_cur_slice->pv_codec_handle = (void*)ps_dec;
1607 ps_dec->ps_dpb_mgr->pv_codec_handle = (void*)ps_dec;
1608 }
1609
1610 memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t));
1611 memset(ps_dec->u4_disp_buf_mapping, 0,
1612 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1613 memset(ps_dec->u4_disp_buf_to_be_freed, 0,
1614 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1615
1616 ih264d_init_arch(ps_dec);
1617 ih264d_init_function_ptr(ps_dec);
1618
1619 ps_dec->init_done = 1;
1620 ps_dec->process_called = 1;
1621
1622 ps_dec->pv_pic_buf_mgr = NULL;
1623 ps_dec->pv_mv_buf_mgr = NULL;
1624 }
1625
1626 /**************************************************************************
1627 * \if Function name : ih264d_init_video_decoder \endif
1628 *
1629 * \brief
1630 * Wrapper for the decoder init
1631 *
1632 * \param p_NALBufAPI: Pointer to NAL Buffer API.
1633 * \param ih264d_dec_mem_manager :Pointer to the function that will be called by decoder
1634 * for memory allocation and freeing.
1635 *
1636 * \return
1637 * pointer to the decparams
1638 *
1639 **************************************************************************
1640 */
1641
ih264d_init_video_decoder(iv_obj_t * dec_hdl,ih264d_init_ip_t * ps_init_ip,ih264d_init_op_t * ps_init_op)1642 WORD32 ih264d_init_video_decoder(iv_obj_t *dec_hdl,
1643 ih264d_init_ip_t *ps_init_ip,
1644 ih264d_init_op_t *ps_init_op)
1645 {
1646 dec_struct_t * ps_dec;
1647 iv_mem_rec_t *memtab;
1648 UWORD8 *pu1_extra_mem_base,*pu1_mem_base;
1649
1650 memtab = ps_init_ip->s_ivd_init_ip_t.pv_mem_rec_location;
1651
1652 dec_hdl->pv_codec_handle = memtab[MEM_REC_CODEC].pv_base;
1653 ps_dec = dec_hdl->pv_codec_handle;
1654
1655 memset(ps_dec, 0, sizeof(dec_struct_t));
1656
1657 if(ps_init_ip->s_ivd_init_ip_t.u4_size
1658 > offsetof(ih264d_init_ip_t, i4_level))
1659 {
1660 ps_dec->u4_level_at_init = ps_init_ip->i4_level;
1661 }
1662 else
1663 {
1664 ps_dec->u4_level_at_init = H264_LEVEL_3_1;
1665 }
1666
1667 if(ps_init_ip->s_ivd_init_ip_t.u4_size
1668 > offsetof(ih264d_init_ip_t, u4_num_ref_frames))
1669 {
1670 ps_dec->u4_num_ref_frames_at_init = ps_init_ip->u4_num_ref_frames;
1671 }
1672 else
1673 {
1674 ps_dec->u4_num_ref_frames_at_init = H264_MAX_REF_PICS;
1675 }
1676
1677 if(ps_init_ip->s_ivd_init_ip_t.u4_size
1678 > offsetof(ih264d_init_ip_t, u4_num_reorder_frames))
1679 {
1680 ps_dec->u4_num_reorder_frames_at_init =
1681 ps_init_ip->u4_num_reorder_frames;
1682 }
1683 else
1684 {
1685 ps_dec->u4_num_reorder_frames_at_init = H264_MAX_REF_PICS;
1686 }
1687
1688 if(ps_init_ip->s_ivd_init_ip_t.u4_size
1689 > offsetof(ih264d_init_ip_t, u4_num_extra_disp_buf))
1690 {
1691 ps_dec->u4_num_extra_disp_bufs_at_init =
1692 ps_init_ip->u4_num_extra_disp_buf;
1693 }
1694 else
1695 {
1696 ps_dec->u4_num_extra_disp_bufs_at_init = 0;
1697 }
1698
1699 if(ps_init_ip->s_ivd_init_ip_t.u4_size
1700 > offsetof(ih264d_init_ip_t, u4_share_disp_buf))
1701 {
1702 #ifndef LOGO_EN
1703 ps_dec->u4_share_disp_buf = ps_init_ip->u4_share_disp_buf;
1704 #else
1705 ps_dec->u4_share_disp_buf = 0;
1706 #endif
1707 }
1708 else
1709 {
1710 ps_dec->u4_share_disp_buf = 0;
1711 }
1712
1713 if((ps_init_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P)
1714 && (ps_init_ip->s_ivd_init_ip_t.e_output_format
1715 != IV_YUV_420SP_UV)
1716 && (ps_init_ip->s_ivd_init_ip_t.e_output_format
1717 != IV_YUV_420SP_VU))
1718 {
1719 ps_dec->u4_share_disp_buf = 0;
1720 }
1721
1722 if((ps_dec->u4_level_at_init < MIN_LEVEL_SUPPORTED)
1723 || (ps_dec->u4_level_at_init > MAX_LEVEL_SUPPORTED))
1724 {
1725 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_LEVEL_UNSUPPORTED;
1726 return (IV_FAIL);
1727 }
1728
1729 if(ps_dec->u4_num_ref_frames_at_init > H264_MAX_REF_PICS)
1730 {
1731 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_NUM_REF;
1732 ps_dec->u4_num_ref_frames_at_init = H264_MAX_REF_PICS;
1733 }
1734
1735 if(ps_dec->u4_num_reorder_frames_at_init > H264_MAX_REF_PICS)
1736 {
1737 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_NUM_REF;
1738 ps_dec->u4_num_reorder_frames_at_init = H264_MAX_REF_PICS;
1739 }
1740
1741 if(ps_dec->u4_num_extra_disp_bufs_at_init > H264_MAX_REF_PICS)
1742 {
1743 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_NUM_REF;
1744 ps_dec->u4_num_extra_disp_bufs_at_init = 0;
1745 }
1746
1747 if(0 == ps_dec->u4_share_disp_buf)
1748 ps_dec->u4_num_extra_disp_bufs_at_init = 0;
1749
1750 ps_dec->u4_num_disp_bufs_requested = 1;
1751
1752 ps_dec->u4_width_at_init = ps_init_ip->s_ivd_init_ip_t.u4_frm_max_wd;
1753 ps_dec->u4_height_at_init = ps_init_ip->s_ivd_init_ip_t.u4_frm_max_ht;
1754
1755 ps_dec->u4_width_at_init = ALIGN16(ps_dec->u4_width_at_init);
1756 ps_dec->u4_height_at_init = ALIGN32(ps_dec->u4_height_at_init);
1757
1758 ps_dec->pv_dec_thread_handle = memtab[MEM_REC_THREAD_HANDLE].pv_base;
1759
1760 pu1_mem_base = memtab[MEM_REC_THREAD_HANDLE].pv_base;
1761 ps_dec->pv_bs_deblk_thread_handle = pu1_mem_base
1762 + ithread_get_handle_size();
1763
1764 ps_dec->u4_extra_mem_used = 0;
1765
1766 pu1_extra_mem_base = memtab[MEM_REC_EXTRA_MEM].pv_base;
1767
1768 ps_dec->ps_dec_err_status = (dec_err_status_t *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used);
1769 ps_dec->u4_extra_mem_used += (((sizeof(dec_err_status_t) + 127) >> 7) << 7);
1770
1771 ps_dec->ps_mem_tab = memtab[MEM_REC_BACKUP].pv_base;
1772
1773 memcpy(ps_dec->ps_mem_tab, memtab, sizeof(iv_mem_rec_t) * MEM_REC_CNT);
1774
1775 ps_dec->ps_pps = memtab[MEM_REC_PPS].pv_base;
1776
1777 ps_dec->ps_sps = memtab[MEM_REC_SPS].pv_base;
1778
1779 ps_dec->ps_sei = (sei *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used);
1780 ps_dec->u4_extra_mem_used += sizeof(sei);
1781
1782 ps_dec->ps_dpb_mgr = memtab[MEM_REC_DPB_MGR].pv_base;
1783
1784 ps_dec->ps_dpb_cmds = (dpb_commands_t *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used);
1785 ps_dec->u4_extra_mem_used += sizeof(dpb_commands_t);
1786
1787 ps_dec->ps_bitstrm = (dec_bit_stream_t *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used);
1788 ps_dec->u4_extra_mem_used += sizeof(dec_bit_stream_t);
1789
1790 ps_dec->ps_cur_slice =(dec_slice_params_t *) (pu1_extra_mem_base + ps_dec->u4_extra_mem_used);
1791 ps_dec->u4_extra_mem_used += sizeof(dec_slice_params_t);
1792
1793 ps_dec->pv_scratch_sps_pps = (void *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used);
1794
1795
1796 ps_dec->u4_extra_mem_used += MAX(sizeof(dec_seq_params_t),
1797 sizeof(dec_pic_params_t));
1798 ps_dec->ps_pred_pkd = memtab[MEM_REC_PRED_INFO_PKD].pv_base;
1799
1800
1801 ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec;
1802
1803 ps_dec->pv_dec_out = (void *)ps_init_op;
1804 ps_dec->pv_dec_in = (void *)ps_init_ip;
1805
1806 ps_dec->u1_chroma_format =
1807 (UWORD8)(ps_init_ip->s_ivd_init_ip_t.e_output_format);
1808
1809
1810
1811 ih264d_init_decoder(ps_dec);
1812
1813 return (IV_SUCCESS);
1814
1815 }
1816
1817
1818 /*****************************************************************************/
1819 /* */
1820 /* Function Name : ih264d_fill_num_mem_rec */
1821 /* */
1822 /* Description : fills memory records */
1823 /* */
1824 /* Inputs : pv_api_ip input api structure */
1825 /* : pv_api_op output api structure */
1826 /* Outputs : */
1827 /* Returns : void */
1828 /* */
1829 /* Issues : none */
1830 /* */
1831 /* Revision History: */
1832 /* */
1833 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1834 /* 22 10 2008 100356 Draft */
1835 /* */
1836 /*****************************************************************************/
ih264d_fill_num_mem_rec(void * pv_api_ip,void * pv_api_op)1837 WORD32 ih264d_fill_num_mem_rec(void *pv_api_ip, void *pv_api_op)
1838 {
1839
1840 ih264d_fill_mem_rec_ip_t *ps_mem_q_ip;
1841 ih264d_fill_mem_rec_op_t *ps_mem_q_op;
1842 WORD32 level;
1843 UWORD32 num_reorder_frames;
1844 UWORD32 num_ref_frames;
1845 UWORD32 num_extra_disp_bufs;
1846 UWORD32 u4_dpb_size_num_frames;
1847 iv_mem_rec_t *memTab;
1848
1849 UWORD32 chroma_format, u4_share_disp_buf;
1850 UWORD32 u4_total_num_mbs;
1851 UWORD32 luma_width, luma_width_in_mbs;
1852 UWORD32 luma_height, luma_height_in_mbs;
1853 UWORD32 max_dpb_size;
1854
1855 ps_mem_q_ip = (ih264d_fill_mem_rec_ip_t *)pv_api_ip;
1856 ps_mem_q_op = (ih264d_fill_mem_rec_op_t *)pv_api_op;
1857
1858 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
1859 > offsetof(ih264d_fill_mem_rec_ip_t, i4_level))
1860 {
1861 level = ps_mem_q_ip->i4_level;
1862 }
1863 else
1864 {
1865 level = H264_LEVEL_3_1;
1866 }
1867
1868 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
1869 > offsetof(ih264d_fill_mem_rec_ip_t, u4_num_reorder_frames))
1870 {
1871 num_reorder_frames = ps_mem_q_ip->u4_num_reorder_frames;
1872 }
1873 else
1874 {
1875 num_reorder_frames = H264_MAX_REF_PICS;
1876 }
1877
1878 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
1879 > offsetof(ih264d_fill_mem_rec_ip_t, u4_num_ref_frames))
1880 {
1881 num_ref_frames = ps_mem_q_ip->u4_num_ref_frames;
1882 }
1883 else
1884 {
1885 num_ref_frames = H264_MAX_REF_PICS;
1886 }
1887
1888 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
1889 > offsetof(ih264d_fill_mem_rec_ip_t, u4_num_extra_disp_buf))
1890 {
1891 num_extra_disp_bufs = ps_mem_q_ip->u4_num_extra_disp_buf;
1892 }
1893 else
1894 {
1895 num_extra_disp_bufs = 0;
1896 }
1897
1898 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
1899 > offsetof(ih264d_fill_mem_rec_ip_t, u4_share_disp_buf))
1900 {
1901 #ifndef LOGO_EN
1902 u4_share_disp_buf = ps_mem_q_ip->u4_share_disp_buf;
1903 #else
1904 u4_share_disp_buf = 0;
1905 #endif
1906 }
1907 else
1908 {
1909 u4_share_disp_buf = 0;
1910 }
1911
1912 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
1913 > offsetof(ih264d_fill_mem_rec_ip_t, e_output_format))
1914 {
1915 chroma_format = ps_mem_q_ip->e_output_format;
1916 }
1917 else
1918 {
1919 chroma_format = -1;
1920 }
1921
1922 if((chroma_format != IV_YUV_420P) && (chroma_format != IV_YUV_420SP_UV)
1923 && (chroma_format != IV_YUV_420SP_VU))
1924 {
1925 u4_share_disp_buf = 0;
1926 }
1927 if(0 == u4_share_disp_buf)
1928 num_extra_disp_bufs = 0;
1929
1930 {
1931
1932 luma_height = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht;
1933 luma_width = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd;
1934
1935 luma_height = ALIGN32(luma_height);
1936 luma_width = ALIGN16(luma_width);
1937 luma_width_in_mbs = luma_width >> 4;
1938 luma_height_in_mbs = luma_height >> 4;
1939 u4_total_num_mbs = (luma_height * luma_width) >> 8;
1940 }
1941 /*
1942 * If level is lesser than 31 and the resolution required is higher,
1943 * then make the level at least 31.
1944 */
1945 if(u4_total_num_mbs > MAX_MBS_LEVEL_30 && level < H264_LEVEL_3_1)
1946 {
1947 level = H264_LEVEL_3_1;
1948 }
1949
1950 if((level < MIN_LEVEL_SUPPORTED) || (level > MAX_LEVEL_SUPPORTED))
1951 {
1952 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
1953 ERROR_LEVEL_UNSUPPORTED;
1954 return (IV_FAIL);
1955 }
1956
1957 if(num_ref_frames > H264_MAX_REF_PICS)
1958 {
1959 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= ERROR_NUM_REF;
1960 num_ref_frames = H264_MAX_REF_PICS;
1961 }
1962
1963 if(num_reorder_frames > H264_MAX_REF_PICS)
1964 {
1965 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= ERROR_NUM_REF;
1966 num_reorder_frames = H264_MAX_REF_PICS;
1967 }
1968 memTab = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
1969
1970 memTab[MEM_REC_IV_OBJ].u4_mem_size = sizeof(iv_obj_t);
1971 memTab[MEM_REC_IV_OBJ].u4_mem_alignment = (128 * 8) / CHAR_BIT;
1972 memTab[MEM_REC_IV_OBJ].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
1973 H264_DEC_DEBUG_PRINT("MEM_REC_IV_OBJ MEM Size = %d\n",
1974 memTab[MEM_REC_IV_OBJ].u4_mem_size);
1975
1976 memTab[MEM_REC_CODEC].u4_mem_alignment = (128 * 8) / CHAR_BIT;
1977 memTab[MEM_REC_CODEC].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
1978 memTab[MEM_REC_CODEC].u4_mem_size = sizeof(dec_struct_t);
1979
1980 {
1981 UWORD32 mvinfo_size, mv_info_size_pad;
1982 UWORD32 MVbank, MVbank_pad;
1983 UWORD32 Ysize;
1984 UWORD32 UVsize;
1985 UWORD32 one_frm_size;
1986
1987 UWORD32 extra_mem = 0;
1988
1989 UWORD32 pad_len_h, pad_len_v;
1990
1991 /*
1992 * For low_delay, use num_buf as 2 -
1993 * num_buf = (num_buf_ref) + 1;
1994 * where num_buf_ref is 1.
1995 */
1996 UWORD32 num_buf;
1997
1998 {
1999 UWORD32 num_bufs_app, num_bufs_level;
2000
2001 num_bufs_app = num_ref_frames + num_reorder_frames + 1;
2002
2003 if(num_bufs_app <= 1)
2004 num_bufs_app = 2;
2005
2006 num_bufs_level = ih264d_get_dpb_size_new(level, (luma_width >> 4),
2007 (luma_height >> 4));
2008
2009 max_dpb_size = num_bufs_level;
2010
2011 num_bufs_level = num_bufs_level * 2 + 1;
2012
2013 num_buf = MIN(num_bufs_level, num_bufs_app);
2014
2015 num_buf += num_extra_disp_bufs;
2016
2017 }
2018
2019 mvinfo_size = ((luma_width * (luma_height)) >> 4);
2020
2021 mv_info_size_pad = ((luma_width * (PAD_MV_BANK_ROW)) >> 4);
2022
2023 Ysize = ALIGN32((luma_width + (PAD_LEN_Y_H << 1)))
2024 * (luma_height + (PAD_LEN_Y_V << 2));
2025
2026
2027 UVsize = Ysize >> 2;
2028 if(u4_share_disp_buf == 1)
2029 {
2030 /* In case of buffers getting shared between application and library
2031 there is no need of reference memtabs. Instead of setting the i4_size
2032 to zero, it is reduced to a small i4_size to ensure that changes
2033 in the code are minimal */
2034
2035 if((chroma_format == IV_YUV_420P)
2036 || (chroma_format == IV_YUV_420SP_UV)
2037 || (chroma_format == IV_YUV_420SP_VU))
2038 {
2039 Ysize = 64;
2040 }
2041 if(chroma_format == IV_YUV_420SP_UV)
2042 {
2043 UVsize = 64;
2044 }
2045 }
2046
2047 one_frm_size = (((Ysize + 127) >> 7) << 7)
2048 + ((((UVsize << 1) + 127) >> 7) << 7);
2049
2050 //Note that for ARM RVDS WS the sizeof(mv_pred_t) is 16
2051
2052 /*Add memory for colocated MB*/
2053 MVbank = sizeof(mv_pred_t) * mvinfo_size;
2054 MVbank_pad = sizeof(mv_pred_t) * mv_info_size_pad;
2055
2056 MVbank = (((MVbank + 127) >> 7) << 7);
2057
2058 MVbank_pad = (((MVbank_pad + 127) >> 7) << 7);
2059
2060 memTab[MEM_REC_MVBANK].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2061 memTab[MEM_REC_MVBANK].e_mem_type =
2062 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2063 memTab[MEM_REC_MVBANK].u4_mem_size = (MVbank + MVbank_pad)
2064 * (MIN(max_dpb_size, num_ref_frames) + 1);
2065
2066
2067 memTab[MEM_REC_REF_PIC].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2068 memTab[MEM_REC_REF_PIC].e_mem_type =
2069 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2070 memTab[MEM_REC_REF_PIC].u4_mem_size = one_frm_size * num_buf;
2071
2072 }
2073
2074 memTab[MEM_REC_DEBLK_MB_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2075 memTab[MEM_REC_DEBLK_MB_INFO].e_mem_type =
2076 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2077 memTab[MEM_REC_DEBLK_MB_INFO].u4_mem_size = (((((u4_total_num_mbs
2078 + (luma_width >> 4)) * sizeof(deblk_mb_t)) + 127) >> 7) << 7);
2079
2080 memTab[MEM_REC_NEIGHBOR_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2081 memTab[MEM_REC_NEIGHBOR_INFO].e_mem_type =
2082 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2083 memTab[MEM_REC_NEIGHBOR_INFO].u4_mem_size = sizeof(mb_neigbour_params_t)
2084 * ((luma_width + 16) >> 4) * 2 * 2;
2085 {
2086 WORD32 size;
2087 WORD32 num_entries;
2088
2089 num_entries = MIN(MAX_FRAMES, num_ref_frames);
2090 num_entries = 2 * ((2 * num_entries) + 1);
2091
2092 size = num_entries * sizeof(void *);
2093 size += PAD_MAP_IDX_POC * sizeof(void *);
2094 size *= u4_total_num_mbs;
2095 size += sizeof(dec_slice_struct_t) * u4_total_num_mbs;
2096 memTab[MEM_REC_SLICE_HDR].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2097 memTab[MEM_REC_SLICE_HDR].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2098 memTab[MEM_REC_SLICE_HDR].u4_mem_size = size;
2099 }
2100 {
2101
2102 UWORD32 u4_num_entries;
2103
2104 u4_num_entries = u4_total_num_mbs;
2105
2106 memTab[MEM_REC_MB_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2107 memTab[MEM_REC_MB_INFO].e_mem_type =
2108 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2109 memTab[MEM_REC_MB_INFO].u4_mem_size = sizeof(dec_mb_info_t)
2110 * u4_num_entries;
2111
2112 memTab[MEM_REC_PRED_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2113 memTab[MEM_REC_PRED_INFO].e_mem_type =
2114 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2115
2116 memTab[MEM_REC_PRED_INFO].u4_mem_size = sizeof(pred_info_t) * 2*32;
2117
2118 memTab[MEM_REC_COEFF_DATA].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2119 memTab[MEM_REC_COEFF_DATA].e_mem_type =
2120 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2121 memTab[MEM_REC_COEFF_DATA].u4_mem_size = MB_LUM_SIZE * sizeof(WORD16);
2122 /*For I16x16 MBs, 16 4x4 AC coeffs and 1 4x4 DC coeff TU blocks will be sent
2123 For all MBs along with 8 4x4 AC coeffs 2 2x2 DC coeff TU blocks will be sent
2124 So use 17 4x4 TU blocks for luma and 9 4x4 TU blocks for chroma */
2125 memTab[MEM_REC_COEFF_DATA].u4_mem_size += u4_num_entries
2126 * (MAX(17 * sizeof(tu_sblk4x4_coeff_data_t),4 * sizeof(tu_blk8x8_coeff_data_t))
2127 + 9 * sizeof(tu_sblk4x4_coeff_data_t));
2128 //32 bytes for each mb to store u1_prev_intra4x4_pred_mode and u1_rem_intra4x4_pred_mode data
2129 memTab[MEM_REC_COEFF_DATA].u4_mem_size += u4_num_entries * 32;
2130
2131 }
2132
2133 memTab[MEM_REC_SPS].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2134 memTab[MEM_REC_SPS].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2135 memTab[MEM_REC_SPS].u4_mem_size = ((sizeof(dec_seq_params_t))
2136 * MAX_NUM_SEQ_PARAMS);
2137
2138 memTab[MEM_REC_PPS].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2139 memTab[MEM_REC_PPS].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2140 memTab[MEM_REC_PPS].u4_mem_size = (sizeof(dec_pic_params_t))
2141 * MAX_NUM_PIC_PARAMS;
2142
2143 {
2144 UWORD32 u4_mem_size;
2145
2146 u4_mem_size = 0;
2147 u4_mem_size += (((sizeof(dec_err_status_t) + 127) >> 7) << 7);
2148 u4_mem_size += sizeof(sei);
2149 u4_mem_size += sizeof(dpb_commands_t);
2150 u4_mem_size += sizeof(dec_bit_stream_t);
2151 u4_mem_size += sizeof(dec_slice_params_t);
2152 u4_mem_size += MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t));
2153
2154 memTab[MEM_REC_EXTRA_MEM].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2155 memTab[MEM_REC_EXTRA_MEM].e_mem_type =
2156 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2157 memTab[MEM_REC_EXTRA_MEM].u4_mem_size = u4_mem_size;
2158 }
2159
2160 {
2161
2162 UWORD32 u4_mem_size;
2163
2164 u4_mem_size = 0;
2165 u4_mem_size += ((TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC) * sizeof(void *));
2166 u4_mem_size = ALIGN64(u4_mem_size);
2167 u4_mem_size += (sizeof(bin_ctxt_model_t) * NUM_CABAC_CTXTS);
2168 u4_mem_size = ALIGN64(u4_mem_size);
2169 u4_mem_size += sizeof(ctxt_inc_mb_info_t);
2170 u4_mem_size = ALIGN64(u4_mem_size);
2171 u4_mem_size += sizeof(UWORD32) * (MAX_REF_BUFS * MAX_REF_BUFS);
2172 u4_mem_size = ALIGN64(u4_mem_size);
2173
2174 u4_mem_size += MAX_REF_BUF_SIZE * 2;
2175 u4_mem_size = ALIGN64(u4_mem_size);
2176 u4_mem_size += ((sizeof(WORD16)) * PRED_BUFFER_WIDTH
2177 * PRED_BUFFER_HEIGHT * 2);
2178 u4_mem_size = ALIGN64(u4_mem_size);
2179 u4_mem_size += sizeof(UWORD8) * (MB_LUM_SIZE);
2180 u4_mem_size = ALIGN64(u4_mem_size);
2181 u4_mem_size += sizeof(parse_pmbarams_t) * luma_width_in_mbs; //Max recon mb group*/
2182 u4_mem_size = ALIGN64(u4_mem_size);
2183 u4_mem_size += (sizeof(parse_part_params_t) * luma_width_in_mbs) << 4; //Max recon mb group*/
2184 u4_mem_size = ALIGN64(u4_mem_size);
2185
2186 u4_mem_size += 2 * MAX_REF_BUFS * sizeof(struct pic_buffer_t);
2187 u4_mem_size = ALIGN64(u4_mem_size);
2188 u4_mem_size += 2 * MAX_REF_BUFS * sizeof(struct pic_buffer_t);
2189 u4_mem_size = ALIGN64(u4_mem_size);
2190 u4_mem_size += (sizeof(UWORD32) * 3 * (MAX_REF_BUFS * MAX_REF_BUFS)) << 3;
2191 u4_mem_size = ALIGN64(u4_mem_size);
2192
2193 u4_mem_size += sizeof(UWORD32) * 2 * 3 * (MAX_REF_BUFS * MAX_REF_BUFS);
2194 u4_mem_size = ALIGN64(u4_mem_size);
2195
2196 memTab[MEM_REC_INTERNAL_SCRATCH].u4_mem_alignment =
2197 (128 * 8) / CHAR_BIT;
2198 memTab[MEM_REC_INTERNAL_SCRATCH].e_mem_type =
2199 IV_EXTERNAL_CACHEABLE_SCRATCH_MEM;
2200 memTab[MEM_REC_INTERNAL_SCRATCH].u4_mem_size = u4_mem_size;
2201 }
2202
2203 {
2204
2205 UWORD32 u4_mem_used;
2206 UWORD32 u4_numRows = MB_SIZE << 1;
2207 UWORD32 u4_blk_wd = ((luma_width_in_mbs << 4) >> 1) + 8;
2208
2209 u4_mem_used = 0;
2210 u4_mem_used += ((luma_width_in_mbs * sizeof(deblkmb_neighbour_t)) << 1);
2211 u4_mem_used = ALIGN64(u4_mem_used);
2212 u4_mem_used += (sizeof(neighbouradd_t) << 2);
2213 u4_mem_used = ALIGN64(u4_mem_used);
2214 u4_mem_used += ((sizeof(ctxt_inc_mb_info_t))
2215 * (((luma_width_in_mbs + 1) << 1) + 1));
2216 u4_mem_used = ALIGN64(u4_mem_used);
2217
2218 u4_mem_used += (sizeof(mv_pred_t) * luma_width_in_mbs * 16);
2219 u4_mem_used = ALIGN64(u4_mem_used);
2220 u4_mem_used += (sizeof(mv_pred_t) * luma_width_in_mbs * 16);
2221 u4_mem_used = ALIGN64(u4_mem_used);
2222 u4_mem_used += (sizeof(mv_pred_t) * luma_width_in_mbs * 4
2223 * MV_SCRATCH_BUFS);
2224 u4_mem_used = ALIGN64(u4_mem_used);
2225 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd;
2226 u4_mem_used = ALIGN64(u4_mem_used);
2227 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd;
2228 u4_mem_used = ALIGN64(u4_mem_used);
2229 u4_numRows = BLK8x8SIZE << 1;
2230
2231 u4_blk_wd = ((luma_width_in_mbs << 3) >> 1) + 8;
2232
2233 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd;
2234 u4_mem_used = ALIGN64(u4_mem_used);
2235 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd;
2236 u4_mem_used = ALIGN64(u4_mem_used);
2237 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd;
2238 u4_mem_used = ALIGN64(u4_mem_used);
2239 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd;
2240 u4_mem_used += 32;
2241 u4_mem_used = ALIGN64(u4_mem_used);
2242 u4_mem_used += sizeof(UWORD8) * (luma_width + 16) * 2;
2243 u4_mem_used = ALIGN64(u4_mem_used);
2244 u4_mem_used += sizeof(UWORD8) * (luma_width + 16) * 2;
2245 u4_mem_used = ALIGN64(u4_mem_used);
2246 u4_mem_used += sizeof(UWORD8) * (luma_width + 16) * 2;
2247 u4_mem_used = ALIGN64(u4_mem_used);
2248 u4_mem_used += sizeof(mb_neigbour_params_t) * (luma_width_in_mbs + 1)
2249 * luma_height_in_mbs;
2250 u4_mem_used += luma_width;
2251 u4_mem_used = ALIGN64(u4_mem_used);
2252 u4_mem_used += luma_width;
2253 u4_mem_used = ALIGN64(u4_mem_used);
2254 u4_mem_used += luma_width;
2255 u4_mem_used = ALIGN64(u4_mem_used);
2256
2257 u4_mem_used += ((MB_SIZE + 4) << 1) * PAD_LEN_Y_H;
2258 u4_mem_used = ALIGN64(u4_mem_used);
2259 u4_mem_used += ((BLK8x8SIZE + 2) << 1) * PAD_LEN_UV_H;
2260 u4_mem_used = ALIGN64(u4_mem_used);
2261 u4_mem_used += ((BLK8x8SIZE + 2) << 1) * PAD_LEN_UV_H;
2262 u4_mem_used = ALIGN64(u4_mem_used);
2263 memTab[MEM_REC_INTERNAL_PERSIST].u4_mem_alignment =
2264 (128 * 8) / CHAR_BIT;
2265 memTab[MEM_REC_INTERNAL_PERSIST].e_mem_type =
2266 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2267 memTab[MEM_REC_INTERNAL_PERSIST].u4_mem_size = u4_mem_used;
2268 }
2269
2270 memTab[MEM_REC_BITSBUF].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2271 memTab[MEM_REC_BITSBUF].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2272 memTab[MEM_REC_BITSBUF].u4_mem_size = MAX(256000, (luma_width * luma_height * 3 / 2));
2273
2274 {
2275
2276 UWORD32 u4_thread_struct_size = ithread_get_handle_size();
2277
2278 memTab[MEM_REC_THREAD_HANDLE].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2279 memTab[MEM_REC_THREAD_HANDLE].e_mem_type =
2280 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2281 memTab[MEM_REC_THREAD_HANDLE].u4_mem_size = u4_thread_struct_size * 2;
2282
2283 }
2284
2285 memTab[MEM_REC_PARSE_MAP].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2286 memTab[MEM_REC_PARSE_MAP].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2287 memTab[MEM_REC_PARSE_MAP].u4_mem_size = u4_total_num_mbs;
2288
2289 memTab[MEM_REC_PROC_MAP].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2290 memTab[MEM_REC_PROC_MAP].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2291 memTab[MEM_REC_PROC_MAP].u4_mem_size = u4_total_num_mbs;
2292
2293 memTab[MEM_REC_SLICE_NUM_MAP].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2294 memTab[MEM_REC_SLICE_NUM_MAP].e_mem_type =
2295 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2296 memTab[MEM_REC_SLICE_NUM_MAP].u4_mem_size = u4_total_num_mbs
2297 * sizeof(UWORD16);
2298
2299 memTab[MEM_REC_DPB_MGR].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2300 memTab[MEM_REC_DPB_MGR].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2301 memTab[MEM_REC_DPB_MGR].u4_mem_size = sizeof(dpb_manager_t);
2302
2303 memTab[MEM_REC_BACKUP].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2304 memTab[MEM_REC_BACKUP].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2305 memTab[MEM_REC_BACKUP].u4_mem_size = sizeof(iv_mem_rec_t) * MEM_REC_CNT;
2306
2307 {
2308
2309 UWORD32 u4_mem_size;
2310
2311 u4_mem_size = sizeof(disp_mgr_t);
2312 u4_mem_size += sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
2313 u4_mem_size += sizeof(struct pic_buffer_t) * (H264_MAX_REF_PICS * 2);
2314
2315 memTab[MEM_REC_PIC_BUF_MGR].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2316 memTab[MEM_REC_PIC_BUF_MGR].e_mem_type =
2317 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2318 memTab[MEM_REC_PIC_BUF_MGR].u4_mem_size = u4_mem_size;
2319 }
2320
2321 {
2322 UWORD32 u4_mem_size;
2323
2324 u4_mem_size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
2325 u4_mem_size += sizeof(col_mv_buf_t) * (H264_MAX_REF_PICS * 2);
2326 u4_mem_size = ALIGN128(u4_mem_size);
2327 u4_mem_size += ((luma_width * luma_height) >> 4)
2328 * (MIN(max_dpb_size, num_ref_frames) + 1);
2329 memTab[MEM_REC_MV_BUF_MGR].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2330 memTab[MEM_REC_MV_BUF_MGR].e_mem_type =
2331 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2332 memTab[MEM_REC_MV_BUF_MGR].u4_mem_size = u4_mem_size;
2333 }
2334
2335 memTab[MEM_REC_PRED_INFO_PKD].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2336 memTab[MEM_REC_PRED_INFO_PKD].e_mem_type =
2337 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2338
2339 {
2340 UWORD32 u4_num_entries;
2341 u4_num_entries = u4_total_num_mbs;
2342
2343 if(1 == num_ref_frames)
2344 u4_num_entries *= 16;
2345 else
2346 u4_num_entries *= 16 * 2;
2347
2348 memTab[MEM_REC_PRED_INFO_PKD].u4_mem_size = sizeof(pred_info_pkd_t)
2349 * u4_num_entries;
2350 }
2351
2352 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_num_mem_rec_filled = MEM_REC_CNT;
2353
2354
2355 return IV_SUCCESS;
2356 }
2357 /*****************************************************************************/
2358 /* */
2359 /* Function Name : ih264d_clr */
2360 /* */
2361 /* Description : returns memory records to app */
2362 /* */
2363 /* Inputs :iv_obj_t decoder handle */
2364 /* :pv_api_ip pointer to input structure */
2365 /* :pv_api_op pointer to output structure */
2366 /* Outputs : */
2367 /* Returns : void */
2368 /* */
2369 /* Issues : none */
2370 /* */
2371 /* Revision History: */
2372 /* */
2373 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2374 /* 22 10 2008 100356 Draft */
2375 /* */
2376 /*****************************************************************************/
ih264d_clr(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)2377 WORD32 ih264d_clr(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2378 {
2379
2380 dec_struct_t * ps_dec;
2381 iv_retrieve_mem_rec_ip_t *dec_clr_ip;
2382 iv_retrieve_mem_rec_op_t *dec_clr_op;
2383
2384 dec_clr_ip = (iv_retrieve_mem_rec_ip_t *)pv_api_ip;
2385 dec_clr_op = (iv_retrieve_mem_rec_op_t *)pv_api_op;
2386 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
2387
2388 if(ps_dec->init_done != 1)
2389 {
2390 //return a proper Error Code
2391 return IV_FAIL;
2392 }
2393
2394 if(ps_dec->pv_pic_buf_mgr)
2395 ih264_buf_mgr_free((buf_mgr_t *)ps_dec->pv_pic_buf_mgr);
2396 if(ps_dec->pv_mv_buf_mgr)
2397 ih264_buf_mgr_free((buf_mgr_t *)ps_dec->pv_mv_buf_mgr);
2398
2399 memcpy(dec_clr_ip->pv_mem_rec_location, ps_dec->ps_mem_tab,
2400 MEM_REC_CNT * (sizeof(iv_mem_rec_t)));
2401 dec_clr_op->u4_num_mem_rec_filled = MEM_REC_CNT;
2402
2403 H264_DEC_DEBUG_PRINT("The clear non-conceal num mem recs: %d\n",
2404 dec_clr_op->u4_num_mem_rec_filled);
2405
2406 return IV_SUCCESS;
2407
2408 }
2409
2410 /*****************************************************************************/
2411 /* */
2412 /* Function Name : ih264d_init */
2413 /* */
2414 /* Description : initializes decoder */
2415 /* */
2416 /* Inputs :iv_obj_t decoder handle */
2417 /* :pv_api_ip pointer to input structure */
2418 /* :pv_api_op pointer to output structure */
2419 /* Outputs : */
2420 /* Returns : void */
2421 /* */
2422 /* Issues : none */
2423 /* */
2424 /* Revision History: */
2425 /* */
2426 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2427 /* 22 10 2008 100356 Draft */
2428 /* */
2429 /*****************************************************************************/
ih264d_init(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)2430 WORD32 ih264d_init(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2431 {
2432 ih264d_init_ip_t *ps_init_ip;
2433 ih264d_init_op_t *ps_init_op;
2434 WORD32 init_status = IV_SUCCESS;
2435 ps_init_ip = (ih264d_init_ip_t *)pv_api_ip;
2436 ps_init_op = (ih264d_init_op_t *)pv_api_op;
2437
2438 init_status = ih264d_init_video_decoder(dec_hdl, ps_init_ip, ps_init_op);
2439
2440 if(IV_SUCCESS != init_status)
2441 {
2442 return init_status;
2443 }
2444
2445 return init_status;
2446 }
2447 /*****************************************************************************/
2448 /* */
2449 /* Function Name : ih264d_map_error */
2450 /* */
2451 /* Description : Maps error codes to IVD error groups */
2452 /* */
2453 /* Inputs : */
2454 /* Globals : <Does it use any global variables?> */
2455 /* Outputs : */
2456 /* Returns : void */
2457 /* */
2458 /* Issues : none */
2459 /* */
2460 /* Revision History: */
2461 /* */
2462 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2463 /* 22 10 2008 100356 Draft */
2464 /* */
2465 /*****************************************************************************/
ih264d_map_error(UWORD32 i4_err_status)2466 UWORD32 ih264d_map_error(UWORD32 i4_err_status)
2467 {
2468 UWORD32 temp = 0;
2469
2470 switch(i4_err_status)
2471 {
2472 case ERROR_MEM_ALLOC_ISRAM_T:
2473 case ERROR_MEM_ALLOC_SDRAM_T:
2474 case ERROR_BUF_MGR:
2475 case ERROR_MB_GROUP_ASSGN_T:
2476 case ERROR_FRAME_LIMIT_OVER:
2477 case ERROR_ACTUAL_RESOLUTION_GREATER_THAN_INIT:
2478 case ERROR_PROFILE_NOT_SUPPORTED:
2479 case ERROR_INIT_NOT_DONE:
2480 temp = 1 << IVD_FATALERROR;
2481 H264_DEC_DEBUG_PRINT("\nFatal Error\n");
2482 break;
2483
2484 case ERROR_DBP_MANAGER_T:
2485 case ERROR_GAPS_IN_FRM_NUM:
2486 case ERROR_UNKNOWN_NAL:
2487 case ERROR_INV_MB_SLC_GRP_T:
2488 case ERROR_MULTIPLE_SLC_GRP_T:
2489 case ERROR_UNKNOWN_LEVEL:
2490 case ERROR_UNAVAIL_PICBUF_T:
2491 case ERROR_UNAVAIL_MVBUF_T:
2492 case ERROR_UNAVAIL_DISPBUF_T:
2493 case ERROR_NUM_REF:
2494 case ERROR_REFIDX_ORDER_T:
2495 case ERROR_PIC0_NOT_FOUND_T:
2496 case ERROR_MB_TYPE:
2497 case ERROR_SUB_MB_TYPE:
2498 case ERROR_CBP:
2499 case ERROR_REF_IDX:
2500 case ERROR_NUM_MV:
2501 case ERROR_CHROMA_PRED_MODE:
2502 case ERROR_INTRAPRED:
2503 case ERROR_NEXT_MB_ADDRESS_T:
2504 case ERROR_MB_ADDRESS_T:
2505 case ERROR_PIC1_NOT_FOUND_T:
2506 case ERROR_CAVLC_NUM_COEFF_T:
2507 case ERROR_CAVLC_SCAN_POS_T:
2508 case ERROR_PRED_WEIGHT_TABLE_T:
2509 case ERROR_CORRUPTED_SLICE:
2510 temp = 1 << IVD_CORRUPTEDDATA;
2511 break;
2512
2513 case ERROR_NOT_SUPP_RESOLUTION:
2514 case ERROR_FEATURE_UNAVAIL:
2515 case ERROR_ACTUAL_LEVEL_GREATER_THAN_INIT:
2516 temp = 1 << IVD_UNSUPPORTEDINPUT;
2517 break;
2518
2519 case ERROR_INVALID_PIC_PARAM:
2520 case ERROR_INVALID_SEQ_PARAM:
2521 case ERROR_EGC_EXCEED_32_1_T:
2522 case ERROR_EGC_EXCEED_32_2_T:
2523 case ERROR_INV_RANGE_TEV_T:
2524 case ERROR_INV_SLC_TYPE_T:
2525 case ERROR_INV_POC_TYPE_T:
2526 case ERROR_INV_RANGE_QP_T:
2527 case ERROR_INV_SPS_PPS_T:
2528 case ERROR_INV_SLICE_HDR_T:
2529 temp = 1 << IVD_CORRUPTEDHEADER;
2530 break;
2531
2532 case ERROR_EOB_FLUSHBITS_T:
2533 case ERROR_EOB_GETBITS_T:
2534 case ERROR_EOB_GETBIT_T:
2535 case ERROR_EOB_BYPASS_T:
2536 case ERROR_EOB_DECISION_T:
2537 case ERROR_EOB_TERMINATE_T:
2538 case ERROR_EOB_READCOEFF4X4CAB_T:
2539 temp = 1 << IVD_INSUFFICIENTDATA;
2540 break;
2541 case ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED:
2542 case ERROR_DISP_WIDTH_RESET_TO_PIC_WIDTH:
2543 temp = 1 << IVD_UNSUPPORTEDPARAM | 1 << IVD_FATALERROR;
2544 break;
2545
2546 case ERROR_DANGLING_FIELD_IN_PIC:
2547 temp = 1 << IVD_APPLIEDCONCEALMENT;
2548 break;
2549
2550 }
2551
2552 return temp;
2553
2554 }
2555
2556 /*****************************************************************************/
2557 /* */
2558 /* Function Name : ih264d_video_decode */
2559 /* */
2560 /* Description : handle video decode API command */
2561 /* */
2562 /* Inputs :iv_obj_t decoder handle */
2563 /* :pv_api_ip pointer to input structure */
2564 /* :pv_api_op pointer to output structure */
2565 /* Outputs : */
2566 /* Returns : void */
2567 /* */
2568 /* Issues : none */
2569 /* */
2570 /* Revision History: */
2571 /* */
2572 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2573 /* 22 10 2008 100356 Draft */
2574 /* */
2575 /*****************************************************************************/
2576
ih264d_video_decode(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)2577 WORD32 ih264d_video_decode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2578 {
2579 /* ! */
2580
2581 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
2582
2583 WORD32 i4_err_status = 0;
2584 UWORD8 *pu1_buf = NULL;
2585 WORD32 buflen;
2586 UWORD32 u4_max_ofst, u4_length_of_start_code = 0;
2587
2588 UWORD32 bytes_consumed = 0;
2589 UWORD32 cur_slice_is_nonref = 0;
2590 UWORD32 u4_next_is_aud;
2591 UWORD32 u4_first_start_code_found = 0;
2592 WORD32 ret = 0,api_ret_value = IV_SUCCESS;
2593 WORD32 header_data_left = 0,frame_data_left = 0;
2594 UWORD8 *pu1_bitstrm_buf;
2595 ivd_video_decode_ip_t *ps_dec_ip;
2596 ivd_video_decode_op_t *ps_dec_op;
2597
2598 ithread_set_name((void*)"Parse_thread");
2599
2600 ps_dec_ip = (ivd_video_decode_ip_t *)pv_api_ip;
2601 ps_dec_op = (ivd_video_decode_op_t *)pv_api_op;
2602 ps_dec->pv_dec_out = ps_dec_op;
2603 ps_dec->process_called = 1;
2604 if(ps_dec->init_done != 1)
2605 {
2606 return IV_FAIL;
2607 }
2608
2609 /*Data memory barries instruction,so that bitstream write by the application is complete*/
2610 DATA_SYNC();
2611
2612 if(0 == ps_dec->u1_flushfrm)
2613 {
2614 if(ps_dec_ip->pv_stream_buffer == NULL)
2615 {
2616 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2617 ps_dec_op->u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL;
2618 return IV_FAIL;
2619 }
2620 if(ps_dec_ip->u4_num_Bytes <= 0)
2621 {
2622 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2623 ps_dec_op->u4_error_code |= IVD_DEC_NUMBYTES_INV;
2624 return IV_FAIL;
2625
2626 }
2627 }
2628 ps_dec->u1_pic_decode_done = 0;
2629
2630 ps_dec_op->u4_num_bytes_consumed = 0;
2631
2632 ps_dec->ps_out_buffer = NULL;
2633
2634 if(ps_dec_ip->u4_size
2635 >= offsetof(ivd_video_decode_ip_t, s_out_buffer))
2636 ps_dec->ps_out_buffer = &ps_dec_ip->s_out_buffer;
2637
2638 ps_dec->u4_fmt_conv_cur_row = 0;
2639
2640 ps_dec->u4_output_present = 0;
2641 ps_dec->s_disp_op.u4_error_code = 1;
2642 ps_dec->u4_fmt_conv_num_rows = FMT_CONV_NUM_ROWS;
2643 ps_dec->u4_stop_threads = 0;
2644 if(0 == ps_dec->u4_share_disp_buf
2645 && ps_dec->i4_decode_header == 0)
2646 {
2647 UWORD32 i;
2648 if(ps_dec->ps_out_buffer->u4_num_bufs == 0)
2649 {
2650 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2651 ps_dec_op->u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2652 return IV_FAIL;
2653 }
2654
2655 for(i = 0; i < ps_dec->ps_out_buffer->u4_num_bufs; i++)
2656 {
2657 if(ps_dec->ps_out_buffer->pu1_bufs[i] == NULL)
2658 {
2659 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2660 ps_dec_op->u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2661 return IV_FAIL;
2662 }
2663
2664 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i] == 0)
2665 {
2666 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2667 ps_dec_op->u4_error_code |=
2668 IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2669 return IV_FAIL;
2670 }
2671 }
2672 }
2673
2674 if(ps_dec->u4_total_frames_decoded >= NUM_FRAMES_LIMIT)
2675 {
2676 ps_dec_op->u4_error_code = ERROR_FRAME_LIMIT_OVER;
2677 return IV_FAIL;
2678 }
2679
2680 /* ! */
2681 ps_dec->u4_ts = ps_dec_ip->u4_ts;
2682
2683 ps_dec_op->u4_error_code = 0;
2684 ps_dec_op->e_pic_type = -1;
2685 ps_dec_op->u4_output_present = 0;
2686 ps_dec_op->u4_frame_decoded_flag = 0;
2687
2688 ps_dec->i4_frametype = -1;
2689 ps_dec->i4_content_type = -1;
2690 /*
2691 * For field pictures, set the bottom and top picture decoded u4_flag correctly.
2692 */
2693 {
2694 if((TOP_FIELD_ONLY | BOT_FIELD_ONLY) == ps_dec->u1_top_bottom_decoded)
2695 {
2696 ps_dec->u1_top_bottom_decoded = 0;
2697 }
2698 }
2699 ps_dec->u4_slice_start_code_found = 0;
2700
2701 /* In case the deocder is not in flush mode(in shared mode),
2702 then decoder has to pick up a buffer to write current frame.
2703 Check if a frame is available in such cases */
2704
2705 if(ps_dec->u1_init_dec_flag == 1 && ps_dec->u4_share_disp_buf == 1
2706 && ps_dec->u1_flushfrm == 0)
2707 {
2708 UWORD32 i;
2709
2710 WORD32 disp_avail = 0, free_id;
2711
2712 /* Check if at least one buffer is available with the codec */
2713 /* If not then return to application with error */
2714 for(i = 0; i < ps_dec->u1_pic_bufs; i++)
2715 {
2716 if(0 == ps_dec->u4_disp_buf_mapping[i]
2717 || 1 == ps_dec->u4_disp_buf_to_be_freed[i])
2718 {
2719 disp_avail = 1;
2720 break;
2721 }
2722
2723 }
2724
2725 if(0 == disp_avail)
2726 {
2727 /* If something is queued for display wait for that buffer to be returned */
2728
2729 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL;
2730 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
2731 return (IV_FAIL);
2732 }
2733
2734 while(1)
2735 {
2736 pic_buffer_t *ps_pic_buf;
2737 ps_pic_buf = (pic_buffer_t *)ih264_buf_mgr_get_next_free(
2738 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, &free_id);
2739
2740 if(ps_pic_buf == NULL)
2741 {
2742 UWORD32 i, display_queued = 0;
2743
2744 /* check if any buffer was given for display which is not returned yet */
2745 for(i = 0; i < (MAX_DISP_BUFS_NEW); i++)
2746 {
2747 if(0 != ps_dec->u4_disp_buf_mapping[i])
2748 {
2749 display_queued = 1;
2750 break;
2751 }
2752 }
2753 /* If some buffer is queued for display, then codec has to singal an error and wait
2754 for that buffer to be returned.
2755 If nothing is queued for display then codec has ownership of all display buffers
2756 and it can reuse any of the existing buffers and continue decoding */
2757
2758 if(1 == display_queued)
2759 {
2760 /* If something is queued for display wait for that buffer to be returned */
2761 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL;
2762 ps_dec_op->u4_error_code |= (1
2763 << IVD_UNSUPPORTEDPARAM);
2764 return (IV_FAIL);
2765 }
2766 }
2767 else
2768 {
2769 /* If the buffer is with display, then mark it as in use and then look for a buffer again */
2770 if(1 == ps_dec->u4_disp_buf_mapping[free_id])
2771 {
2772 ih264_buf_mgr_set_status(
2773 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
2774 free_id,
2775 BUF_MGR_IO);
2776 }
2777 else
2778 {
2779 /**
2780 * Found a free buffer for present call. Release it now.
2781 * Will be again obtained later.
2782 */
2783 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
2784 free_id,
2785 BUF_MGR_IO);
2786 break;
2787 }
2788 }
2789 }
2790
2791 }
2792
2793 if(ps_dec->u1_flushfrm && ps_dec->u1_init_dec_flag)
2794 {
2795
2796 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer,
2797 &(ps_dec->s_disp_op));
2798 if(0 == ps_dec->s_disp_op.u4_error_code)
2799 {
2800 ps_dec->u4_fmt_conv_cur_row = 0;
2801 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht;
2802 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op),
2803 ps_dec->u4_fmt_conv_cur_row,
2804 ps_dec->u4_fmt_conv_num_rows);
2805 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows;
2806 ps_dec->u4_output_present = 1;
2807
2808 }
2809 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op));
2810
2811 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
2812 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
2813
2814 ps_dec_op->u4_new_seq = 0;
2815
2816 ps_dec_op->u4_output_present = ps_dec->u4_output_present;
2817 ps_dec_op->u4_progressive_frame_flag =
2818 ps_dec->s_disp_op.u4_progressive_frame_flag;
2819 ps_dec_op->e_output_format =
2820 ps_dec->s_disp_op.e_output_format;
2821 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf;
2822 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type;
2823 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts;
2824 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
2825
2826 /*In the case of flush ,since no frame is decoded set pic type as invalid*/
2827 ps_dec_op->u4_is_ref_flag = -1;
2828 ps_dec_op->e_pic_type = IV_NA_FRAME;
2829 ps_dec_op->u4_frame_decoded_flag = 0;
2830
2831 if(0 == ps_dec->s_disp_op.u4_error_code)
2832 {
2833 return (IV_SUCCESS);
2834 }
2835 else
2836 return (IV_FAIL);
2837
2838 }
2839 if(ps_dec->u1_res_changed == 1)
2840 {
2841 /*if resolution has changed and all buffers have been flushed, reset decoder*/
2842 ih264d_init_decoder(ps_dec);
2843 }
2844
2845 ps_dec->u4_prev_nal_skipped = 0;
2846
2847 ps_dec->u2_cur_mb_addr = 0;
2848 ps_dec->u2_total_mbs_coded = 0;
2849 ps_dec->u2_cur_slice_num = 0;
2850 ps_dec->cur_dec_mb_num = 0;
2851 ps_dec->cur_recon_mb_num = 0;
2852 ps_dec->u4_first_slice_in_pic = 2;
2853 ps_dec->u1_slice_header_done = 0;
2854 ps_dec->u1_dangling_field = 0;
2855
2856 ps_dec->u4_dec_thread_created = 0;
2857 ps_dec->u4_bs_deblk_thread_created = 0;
2858 ps_dec->u4_cur_bs_mb_num = 0;
2859
2860 DEBUG_THREADS_PRINTF(" Starting process call\n");
2861
2862 ps_dec->u4_pic_buf_got = 0;
2863
2864 do
2865 {
2866
2867 pu1_buf = (UWORD8*)ps_dec_ip->pv_stream_buffer
2868 + ps_dec_op->u4_num_bytes_consumed;
2869
2870 u4_max_ofst = ps_dec_ip->u4_num_Bytes
2871 - ps_dec_op->u4_num_bytes_consumed;
2872 pu1_bitstrm_buf = ps_dec->ps_mem_tab[MEM_REC_BITSBUF].pv_base;
2873
2874 u4_next_is_aud = 0;
2875
2876 buflen = ih264d_find_start_code(pu1_buf, 0, u4_max_ofst,
2877 &u4_length_of_start_code,
2878 &u4_next_is_aud);
2879
2880 if(buflen == -1)
2881 buflen = 0;
2882 /* Ignore bytes beyond the allocated size of intermediate buffer */
2883 buflen = MIN(buflen, (WORD32)ps_dec->ps_mem_tab[MEM_REC_BITSBUF].u4_mem_size);
2884
2885 bytes_consumed = buflen + u4_length_of_start_code;
2886 ps_dec_op->u4_num_bytes_consumed += bytes_consumed;
2887
2888 if(buflen >= MAX_NAL_UNIT_SIZE)
2889 {
2890
2891 ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op);
2892 H264_DEC_DEBUG_PRINT(
2893 "\nNal Size exceeded %d, Processing Stopped..\n",
2894 MAX_NAL_UNIT_SIZE);
2895 ps_dec->i4_error_code = 1 << IVD_CORRUPTEDDATA;
2896
2897 ps_dec_op->e_pic_type = -1;
2898 /*signal the decode thread*/
2899 ih264d_signal_decode_thread(ps_dec);
2900 /*signal end of frame decode for curren frame*/
2901
2902 if(ps_dec->u4_pic_buf_got == 0)
2903 {
2904 if(ps_dec->i4_header_decoded == 3)
2905 {
2906 ps_dec->u2_total_mbs_coded =
2907 ps_dec->ps_cur_sps->u2_max_mb_addr + 1;
2908 }
2909
2910 /* close deblock thread if it is not closed yet*/
2911 if(ps_dec->u4_num_cores == 3)
2912 {
2913 ih264d_signal_bs_deblk_thread(ps_dec);
2914 }
2915 return IV_FAIL;
2916 }
2917 else
2918 {
2919 ps_dec->u1_pic_decode_done = 1;
2920 continue;
2921 }
2922 }
2923
2924 {
2925 UWORD8 u1_firstbyte, u1_nal_ref_idc;
2926
2927 if(ps_dec->i4_app_skip_mode == IVD_SKIP_B)
2928 {
2929 u1_firstbyte = *(pu1_buf + u4_length_of_start_code);
2930 u1_nal_ref_idc = (UWORD8)(NAL_REF_IDC(u1_firstbyte));
2931 if(u1_nal_ref_idc == 0)
2932 {
2933 /*skip non reference frames*/
2934 cur_slice_is_nonref = 1;
2935 continue;
2936 }
2937 else
2938 {
2939 if(1 == cur_slice_is_nonref)
2940 {
2941 /*We have encountered a referenced frame,return to app*/
2942 ps_dec_op->u4_num_bytes_consumed -=
2943 bytes_consumed;
2944 ps_dec_op->e_pic_type = IV_B_FRAME;
2945 ps_dec_op->u4_error_code =
2946 IVD_DEC_FRM_SKIPPED;
2947 ps_dec_op->u4_error_code |= (1
2948 << IVD_UNSUPPORTEDPARAM);
2949 ps_dec_op->u4_frame_decoded_flag = 0;
2950 ps_dec_op->u4_size =
2951 sizeof(ivd_video_decode_op_t);
2952 /*signal the decode thread*/
2953 ih264d_signal_decode_thread(ps_dec);
2954 /* close deblock thread if it is not closed yet*/
2955 if(ps_dec->u4_num_cores == 3)
2956 {
2957 ih264d_signal_bs_deblk_thread(ps_dec);
2958 }
2959
2960 return (IV_FAIL);
2961 }
2962 }
2963
2964 }
2965
2966 }
2967
2968
2969 if(buflen)
2970 {
2971 memcpy(pu1_bitstrm_buf, pu1_buf + u4_length_of_start_code,
2972 buflen);
2973 u4_first_start_code_found = 1;
2974
2975 }
2976 else
2977 {
2978 /*start code not found*/
2979
2980 if(u4_first_start_code_found == 0)
2981 {
2982 /*no start codes found in current process call*/
2983
2984 ps_dec->i4_error_code = ERROR_START_CODE_NOT_FOUND;
2985 ps_dec_op->u4_error_code |= 1 << IVD_INSUFFICIENTDATA;
2986
2987 if(ps_dec->u4_pic_buf_got == 0)
2988 {
2989
2990 ih264d_fill_output_struct_from_context(ps_dec,
2991 ps_dec_op);
2992
2993 ps_dec_op->u4_error_code = ps_dec->i4_error_code;
2994 ps_dec_op->u4_frame_decoded_flag = 0;
2995
2996 return (IV_FAIL);
2997 }
2998 else
2999 {
3000 ps_dec->u1_pic_decode_done = 1;
3001 continue;
3002 }
3003 }
3004 else
3005 {
3006 /* a start code has already been found earlier in the same process call*/
3007 frame_data_left = 0;
3008 continue;
3009 }
3010
3011 }
3012
3013 ps_dec->u4_return_to_app = 0;
3014 ret = ih264d_parse_nal_unit(dec_hdl, ps_dec_op,
3015 pu1_bitstrm_buf, buflen);
3016 if(ret != OK)
3017 {
3018 UWORD32 error = ih264d_map_error(ret);
3019 ps_dec_op->u4_error_code = error | ret;
3020 api_ret_value = IV_FAIL;
3021
3022 if((ret == IVD_RES_CHANGED)
3023 || (ret == IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED)
3024 || (ret == ERROR_UNAVAIL_PICBUF_T)
3025 || (ret == ERROR_UNAVAIL_MVBUF_T))
3026 {
3027 break;
3028 }
3029
3030 if((ret == ERROR_INCOMPLETE_FRAME) || (ret == ERROR_DANGLING_FIELD_IN_PIC))
3031 {
3032 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
3033 api_ret_value = IV_FAIL;
3034 break;
3035 }
3036
3037 if(ret == ERROR_IN_LAST_SLICE_OF_PIC)
3038 {
3039 api_ret_value = IV_FAIL;
3040 break;
3041 }
3042
3043 }
3044
3045 if(ps_dec->u4_return_to_app)
3046 {
3047 /*We have encountered a referenced frame,return to app*/
3048 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
3049 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED;
3050 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
3051 ps_dec_op->u4_frame_decoded_flag = 0;
3052 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t);
3053 /*signal the decode thread*/
3054 ih264d_signal_decode_thread(ps_dec);
3055 /* close deblock thread if it is not closed yet*/
3056 if(ps_dec->u4_num_cores == 3)
3057 {
3058 ih264d_signal_bs_deblk_thread(ps_dec);
3059 }
3060 return (IV_FAIL);
3061
3062 }
3063
3064
3065
3066 header_data_left = ((ps_dec->i4_decode_header == 1)
3067 && (ps_dec->i4_header_decoded != 3)
3068 && (ps_dec_op->u4_num_bytes_consumed
3069 < ps_dec_ip->u4_num_Bytes));
3070 frame_data_left = (((ps_dec->i4_decode_header == 0)
3071 && ((ps_dec->u1_pic_decode_done == 0)
3072 || (u4_next_is_aud == 1)))
3073 && (ps_dec_op->u4_num_bytes_consumed
3074 < ps_dec_ip->u4_num_Bytes));
3075 }
3076 while(( header_data_left == 1)||(frame_data_left == 1));
3077
3078 if((ps_dec->u4_slice_start_code_found == 1)
3079 && ps_dec->u2_total_mbs_coded < ps_dec->u2_frm_ht_in_mbs * ps_dec->u2_frm_wd_in_mbs)
3080 {
3081 // last slice - missing/corruption
3082 WORD32 num_mb_skipped;
3083 WORD32 prev_slice_err;
3084 pocstruct_t temp_poc;
3085 WORD32 ret1;
3086
3087 num_mb_skipped = (ps_dec->u2_frm_ht_in_mbs * ps_dec->u2_frm_wd_in_mbs)
3088 - ps_dec->u2_total_mbs_coded;
3089
3090 if(ps_dec->u4_first_slice_in_pic)
3091 prev_slice_err = 1;
3092 else
3093 prev_slice_err = 2;
3094
3095 ret1 = ih264d_mark_err_slice_skip(ps_dec, num_mb_skipped, ps_dec->u1_nal_unit_type == IDR_SLICE_NAL, ps_dec->ps_cur_slice->u2_frame_num,
3096 &temp_poc, prev_slice_err);
3097
3098 if((ret1 == ERROR_UNAVAIL_PICBUF_T) || (ret1 == ERROR_UNAVAIL_MVBUF_T))
3099 {
3100 return IV_FAIL;
3101 }
3102 }
3103
3104 if((ret == IVD_RES_CHANGED)
3105 || (ret == IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED)
3106 || (ret == ERROR_UNAVAIL_PICBUF_T)
3107 || (ret == ERROR_UNAVAIL_MVBUF_T))
3108 {
3109
3110 /* signal the decode thread */
3111 ih264d_signal_decode_thread(ps_dec);
3112 /* close deblock thread if it is not closed yet */
3113 if(ps_dec->u4_num_cores == 3)
3114 {
3115 ih264d_signal_bs_deblk_thread(ps_dec);
3116 }
3117 /* dont consume bitstream */
3118 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
3119 return IV_FAIL;
3120 }
3121
3122
3123 if(ps_dec->u1_separate_parse)
3124 {
3125 /* If Format conversion is not complete,
3126 complete it here */
3127 if(ps_dec->u4_num_cores == 2)
3128 {
3129
3130 /*do deblocking of all mbs*/
3131 if((ps_dec->u4_nmb_deblk == 0) &&(ps_dec->u4_start_recon_deblk == 1) && (ps_dec->ps_cur_sps->u1_mb_aff_flag == 0))
3132 {
3133 UWORD32 u4_num_mbs,u4_max_addr;
3134 tfr_ctxt_t s_tfr_ctxt;
3135 tfr_ctxt_t *ps_tfr_cxt = &s_tfr_ctxt;
3136 pad_mgr_t *ps_pad_mgr = &ps_dec->s_pad_mgr;
3137
3138 /*BS is done for all mbs while parsing*/
3139 u4_max_addr = (ps_dec->u2_frm_wd_in_mbs * ps_dec->u2_frm_ht_in_mbs) - 1;
3140 ps_dec->u4_cur_bs_mb_num = u4_max_addr + 1;
3141
3142
3143 ih264d_init_deblk_tfr_ctxt(ps_dec, ps_pad_mgr, ps_tfr_cxt,
3144 ps_dec->u2_frm_wd_in_mbs, 0);
3145
3146
3147 u4_num_mbs = u4_max_addr
3148 - ps_dec->u4_cur_deblk_mb_num + 1;
3149
3150 DEBUG_PERF_PRINTF("mbs left for deblocking= %d \n",u4_num_mbs);
3151
3152 if(u4_num_mbs != 0)
3153 ih264d_check_mb_map_deblk(ps_dec, u4_num_mbs,
3154 ps_tfr_cxt,1);
3155
3156 ps_dec->u4_start_recon_deblk = 0;
3157
3158 }
3159
3160 }
3161
3162 /*signal the decode thread*/
3163 ih264d_signal_decode_thread(ps_dec);
3164 /* close deblock thread if it is not closed yet*/
3165 if(ps_dec->u4_num_cores == 3)
3166 {
3167 ih264d_signal_bs_deblk_thread(ps_dec);
3168 }
3169 }
3170
3171
3172 DATA_SYNC();
3173
3174
3175 if((ps_dec_op->u4_error_code & 0xff)
3176 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
3177 {
3178 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
3179 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
3180 }
3181
3182 //Report if header (sps and pps) has not been decoded yet
3183 if(ps_dec->i4_header_decoded != 3)
3184 {
3185 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA);
3186
3187 }
3188
3189 if(ps_dec->i4_decode_header == 1 && ps_dec->i4_header_decoded != 3)
3190 {
3191 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA);
3192
3193 }
3194 if(ps_dec->u4_prev_nal_skipped)
3195 {
3196 /*We have encountered a referenced frame,return to app*/
3197 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED;
3198 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
3199 ps_dec_op->u4_frame_decoded_flag = 0;
3200 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t);
3201 /* close deblock thread if it is not closed yet*/
3202 if(ps_dec->u4_num_cores == 3)
3203 {
3204 ih264d_signal_bs_deblk_thread(ps_dec);
3205 }
3206 return (IV_FAIL);
3207
3208 }
3209
3210 if((ps_dec->u4_slice_start_code_found == 1)
3211 && (ERROR_DANGLING_FIELD_IN_PIC != i4_err_status))
3212 {
3213 /*
3214 * For field pictures, set the bottom and top picture decoded u4_flag correctly.
3215 */
3216
3217 if(ps_dec->ps_cur_slice->u1_field_pic_flag)
3218 {
3219 if(1 == ps_dec->ps_cur_slice->u1_bottom_field_flag)
3220 {
3221 ps_dec->u1_top_bottom_decoded |= BOT_FIELD_ONLY;
3222 }
3223 else
3224 {
3225 ps_dec->u1_top_bottom_decoded |= TOP_FIELD_ONLY;
3226 }
3227 }
3228
3229 /* if new frame in not found (if we are still getting slices from previous frame)
3230 * ih264d_deblock_display is not called. Such frames will not be added to reference /display
3231 */
3232 if((ps_dec->ps_dec_err_status->u1_err_flag & REJECT_CUR_PIC) == 0)
3233 {
3234 /* Calling Function to deblock Picture and Display */
3235 ret = ih264d_deblock_display(ps_dec);
3236 if(ret != 0)
3237 {
3238 return IV_FAIL;
3239 }
3240 }
3241
3242
3243 /*set to complete ,as we dont support partial frame decode*/
3244 if(ps_dec->i4_header_decoded == 3)
3245 {
3246 ps_dec->u2_total_mbs_coded = ps_dec->ps_cur_sps->u2_max_mb_addr + 1;
3247 }
3248
3249 /*Update the i4_frametype at the end of picture*/
3250 if(ps_dec->ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL)
3251 {
3252 ps_dec->i4_frametype = IV_IDR_FRAME;
3253 }
3254 else if(ps_dec->i4_pic_type == B_SLICE)
3255 {
3256 ps_dec->i4_frametype = IV_B_FRAME;
3257 }
3258 else if(ps_dec->i4_pic_type == P_SLICE)
3259 {
3260 ps_dec->i4_frametype = IV_P_FRAME;
3261 }
3262 else if(ps_dec->i4_pic_type == I_SLICE)
3263 {
3264 ps_dec->i4_frametype = IV_I_FRAME;
3265 }
3266 else
3267 {
3268 H264_DEC_DEBUG_PRINT("Shouldn't come here\n");
3269 }
3270
3271 //Update the content type
3272 ps_dec->i4_content_type = ps_dec->ps_cur_slice->u1_field_pic_flag;
3273
3274 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded + 2;
3275 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded
3276 - ps_dec->ps_cur_slice->u1_field_pic_flag;
3277
3278 }
3279
3280 /* close deblock thread if it is not closed yet*/
3281 if(ps_dec->u4_num_cores == 3)
3282 {
3283 ih264d_signal_bs_deblk_thread(ps_dec);
3284 }
3285
3286
3287 {
3288 /* In case the decoder is configured to run in low delay mode,
3289 * then get display buffer and then format convert.
3290 * Note in this mode, format conversion does not run paralelly in a thread and adds to the codec cycles
3291 */
3292
3293 if((0 == ps_dec->u4_num_reorder_frames_at_init)
3294 && ps_dec->u1_init_dec_flag)
3295 {
3296
3297 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer,
3298 &(ps_dec->s_disp_op));
3299 if(0 == ps_dec->s_disp_op.u4_error_code)
3300 {
3301 ps_dec->u4_fmt_conv_cur_row = 0;
3302 ps_dec->u4_output_present = 1;
3303 }
3304 }
3305
3306 ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op);
3307
3308 /* If Format conversion is not complete,
3309 complete it here */
3310 if(ps_dec->u4_output_present &&
3311 (ps_dec->u4_fmt_conv_cur_row < ps_dec->s_disp_frame_info.u4_y_ht))
3312 {
3313 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht
3314 - ps_dec->u4_fmt_conv_cur_row;
3315 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op),
3316 ps_dec->u4_fmt_conv_cur_row,
3317 ps_dec->u4_fmt_conv_num_rows);
3318 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows;
3319 }
3320
3321 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op));
3322 }
3323
3324 if(ps_dec->i4_decode_header == 1 && (ps_dec->i4_header_decoded & 1) == 1)
3325 {
3326 ps_dec_op->u4_progressive_frame_flag = 1;
3327 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3328 {
3329 if((0 == ps_dec->ps_sps->u1_frame_mbs_only_flag)
3330 && (0 == ps_dec->ps_sps->u1_mb_aff_flag))
3331 ps_dec_op->u4_progressive_frame_flag = 0;
3332
3333 }
3334 }
3335
3336 /*Data memory barrier instruction,so that yuv write by the library is complete*/
3337 DATA_SYNC();
3338
3339 H264_DEC_DEBUG_PRINT("The num bytes consumed: %d\n",
3340 ps_dec_op->u4_num_bytes_consumed);
3341 return api_ret_value;
3342 }
3343
ih264d_get_version(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3344 WORD32 ih264d_get_version(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3345 {
3346 char version_string[MAXVERSION_STRLEN + 1];
3347 UWORD32 version_string_len;
3348
3349 ivd_ctl_getversioninfo_ip_t *ps_ip;
3350 ivd_ctl_getversioninfo_op_t *ps_op;
3351
3352 ps_ip = (ivd_ctl_getversioninfo_ip_t *)pv_api_ip;
3353 ps_op = (ivd_ctl_getversioninfo_op_t *)pv_api_op;
3354 UNUSED(dec_hdl);
3355 ps_op->u4_error_code = IV_SUCCESS;
3356
3357 VERSION(version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER,
3358 CODEC_VENDOR);
3359
3360 if((WORD32)ps_ip->u4_version_buffer_size <= 0)
3361 {
3362 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT;
3363 return (IV_FAIL);
3364 }
3365
3366 version_string_len = strlen(version_string) + 1;
3367
3368 if(ps_ip->u4_version_buffer_size >= version_string_len) //(WORD32)sizeof(sizeof(version_string)))
3369 {
3370 memcpy(ps_ip->pv_version_buffer, version_string, version_string_len);
3371 ps_op->u4_error_code = IV_SUCCESS;
3372 }
3373 else
3374 {
3375 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT;
3376 return IV_FAIL;
3377 }
3378 return (IV_SUCCESS);
3379 }
3380
3381 /*****************************************************************************/
3382 /* */
3383 /* Function Name : ih264d_get_display_frame */
3384 /* */
3385 /* Description : */
3386 /* Inputs :iv_obj_t decoder handle */
3387 /* :pv_api_ip pointer to input structure */
3388 /* :pv_api_op pointer to output structure */
3389 /* Outputs : */
3390 /* Returns : void */
3391 /* */
3392 /* Issues : none */
3393 /* */
3394 /* Revision History: */
3395 /* */
3396 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3397 /* 22 10 2008 100356 Draft */
3398 /* */
3399 /*****************************************************************************/
ih264d_get_display_frame(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3400 WORD32 ih264d_get_display_frame(iv_obj_t *dec_hdl,
3401 void *pv_api_ip,
3402 void *pv_api_op)
3403 {
3404
3405 UNUSED(dec_hdl);
3406 UNUSED(pv_api_ip);
3407 UNUSED(pv_api_op);
3408 // This function is no longer needed, output is returned in the process()
3409 return IV_FAIL;
3410 }
3411
3412 /*****************************************************************************/
3413 /* */
3414 /* Function Name : ih264d_set_display_frame */
3415 /* */
3416 /* Description : */
3417 /* */
3418 /* Inputs :iv_obj_t decoder handle */
3419 /* :pv_api_ip pointer to input structure */
3420 /* :pv_api_op pointer to output structure */
3421 /* Outputs : */
3422 /* Returns : void */
3423 /* */
3424 /* Issues : none */
3425 /* */
3426 /* Revision History: */
3427 /* */
3428 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3429 /* 22 10 2008 100356 Draft */
3430 /* */
3431 /*****************************************************************************/
ih264d_set_display_frame(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3432 WORD32 ih264d_set_display_frame(iv_obj_t *dec_hdl,
3433 void *pv_api_ip,
3434 void *pv_api_op)
3435 {
3436
3437 ivd_set_display_frame_ip_t *dec_disp_ip;
3438 ivd_set_display_frame_op_t *dec_disp_op;
3439
3440 UWORD32 i, num_mvbank_req;
3441 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3442
3443 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip;
3444 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op;
3445 dec_disp_op->u4_error_code = 0;
3446 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3447 {
3448 UWORD32 level, width_mbs, height_mbs;
3449
3450 level = ps_dec->u4_level_at_init;
3451 width_mbs = ps_dec->u2_frm_wd_in_mbs;
3452 height_mbs = ps_dec->u2_frm_ht_in_mbs;
3453
3454 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1)
3455 && (ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames != 64))
3456 {
3457 num_mvbank_req = ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 2;
3458 }
3459 else
3460 {
3461 /*if VUI is not present assume maximum possible refrence frames for the level,
3462 * as max reorder frames*/
3463 num_mvbank_req = ih264d_get_dpb_size_new(level, width_mbs,
3464 height_mbs);
3465 }
3466
3467 num_mvbank_req += ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
3468 }
3469 else
3470 {
3471 UWORD32 num_bufs_app, num_bufs_level;
3472 UWORD32 num_ref_frames, num_reorder_frames, luma_width;
3473 UWORD32 luma_height, level;
3474
3475 num_ref_frames = ps_dec->u4_num_ref_frames_at_init;
3476 num_reorder_frames = ps_dec->u4_num_reorder_frames_at_init;
3477 level = ps_dec->u4_level_at_init;
3478 luma_width = ps_dec->u4_width_at_init;
3479 luma_height = ps_dec->u4_height_at_init;
3480
3481 num_bufs_app = num_ref_frames + num_reorder_frames + 1;
3482
3483 if(num_bufs_app <= 1)
3484 num_bufs_app = 2;
3485
3486 num_bufs_level = ih264d_get_dpb_size_new(level, (luma_width >> 4),
3487 (luma_height >> 4));
3488
3489 num_bufs_level = num_bufs_level * 2 + 1;
3490
3491 num_mvbank_req = MIN(num_bufs_level, num_bufs_app);
3492
3493 num_mvbank_req += ps_dec->u4_num_extra_disp_bufs_at_init;
3494
3495 }
3496
3497 ps_dec->u4_num_disp_bufs = 0;
3498 if(ps_dec->u4_share_disp_buf)
3499 {
3500 UWORD32 u4_num_bufs = dec_disp_ip->num_disp_bufs;
3501 if(u4_num_bufs > MAX_DISP_BUFS_NEW)
3502 u4_num_bufs = MAX_DISP_BUFS_NEW;
3503
3504 u4_num_bufs = MIN(u4_num_bufs, MAX_DISP_BUFS_NEW);
3505 u4_num_bufs = MIN(u4_num_bufs, num_mvbank_req);
3506
3507 ps_dec->u4_num_disp_bufs = u4_num_bufs;
3508 for(i = 0; i < u4_num_bufs; i++)
3509 {
3510 ps_dec->disp_bufs[i].u4_num_bufs =
3511 dec_disp_ip->s_disp_buffer[i].u4_num_bufs;
3512
3513 ps_dec->disp_bufs[i].buf[0] =
3514 dec_disp_ip->s_disp_buffer[i].pu1_bufs[0];
3515 ps_dec->disp_bufs[i].buf[1] =
3516 dec_disp_ip->s_disp_buffer[i].pu1_bufs[1];
3517 ps_dec->disp_bufs[i].buf[2] =
3518 dec_disp_ip->s_disp_buffer[i].pu1_bufs[2];
3519
3520 ps_dec->disp_bufs[i].u4_bufsize[0] =
3521 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0];
3522 ps_dec->disp_bufs[i].u4_bufsize[1] =
3523 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1];
3524 ps_dec->disp_bufs[i].u4_bufsize[2] =
3525 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2];
3526
3527 }
3528 }
3529 return IV_SUCCESS;
3530
3531 }
3532
3533 /*****************************************************************************/
3534 /* */
3535 /* Function Name : ih264d_set_flush_mode */
3536 /* */
3537 /* Description : */
3538 /* */
3539 /* Inputs :iv_obj_t decoder handle */
3540 /* :pv_api_ip pointer to input structure */
3541 /* :pv_api_op pointer to output structure */
3542 /* Globals : <Does it use any global variables?> */
3543 /* Outputs : */
3544 /* Returns : void */
3545 /* */
3546 /* Issues : none */
3547 /* */
3548 /* Revision History: */
3549 /* */
3550 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3551 /* 22 10 2008 100356 Draft */
3552 /* */
3553 /*****************************************************************************/
ih264d_set_flush_mode(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3554 WORD32 ih264d_set_flush_mode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3555 {
3556
3557 dec_struct_t * ps_dec;
3558 ivd_ctl_flush_op_t *ps_ctl_op = (ivd_ctl_flush_op_t*)pv_api_op;
3559 ps_ctl_op->u4_error_code = 0;
3560
3561 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3562 UNUSED(pv_api_ip);
3563 /* ! */
3564 /* Signal flush frame control call */
3565 ps_dec->u1_flushfrm = 1;
3566
3567 if( ps_dec->u1_init_dec_flag == 1)
3568 {
3569
3570 ih264d_release_pics_in_dpb((void *)ps_dec,
3571 ps_dec->u1_pic_bufs);
3572 ih264d_release_display_bufs(ps_dec);
3573 }
3574
3575 ps_ctl_op->u4_error_code =
3576 ((ivd_ctl_flush_op_t*)ps_dec->pv_dec_out)->u4_error_code; //verify the value
3577
3578 return IV_SUCCESS;
3579
3580 }
3581
3582 /*****************************************************************************/
3583 /* */
3584 /* Function Name : ih264d_get_status */
3585 /* */
3586 /* Description : */
3587 /* */
3588 /* Inputs :iv_obj_t decoder handle */
3589 /* :pv_api_ip pointer to input structure */
3590 /* :pv_api_op pointer to output structure */
3591 /* Globals : <Does it use any global variables?> */
3592 /* Outputs : */
3593 /* Returns : void */
3594 /* */
3595 /* Issues : none */
3596 /* */
3597 /* Revision History: */
3598 /* */
3599 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3600 /* 22 10 2008 100356 Draft */
3601 /* */
3602 /*****************************************************************************/
3603
ih264d_get_status(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3604 WORD32 ih264d_get_status(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3605 {
3606
3607 UWORD32 i;
3608 dec_struct_t * ps_dec;
3609 UWORD32 pic_wd, pic_ht;
3610 ivd_ctl_getstatus_op_t *ps_ctl_op = (ivd_ctl_getstatus_op_t*)pv_api_op;
3611 UNUSED(pv_api_ip);
3612 ps_ctl_op->u4_error_code = 0;
3613
3614 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3615
3616 pic_wd = ps_dec->u4_width_at_init;
3617 pic_ht = ps_dec->u4_height_at_init;
3618
3619 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3620 {
3621 ps_ctl_op->u4_pic_ht = ps_dec->u2_disp_height;
3622 ps_ctl_op->u4_pic_wd = ps_dec->u2_disp_width;
3623
3624 if(0 == ps_dec->u4_share_disp_buf)
3625 {
3626 pic_wd = ps_dec->u2_disp_width;
3627 pic_ht = ps_dec->u2_disp_height;
3628
3629 }
3630 else
3631 {
3632 pic_wd = ps_dec->u2_frm_wd_y;
3633 pic_ht = ps_dec->u2_frm_ht_y;
3634 }
3635 }
3636 else
3637 {
3638 ps_ctl_op->u4_pic_ht = pic_wd;
3639 ps_ctl_op->u4_pic_wd = pic_ht;
3640
3641 if(1 == ps_dec->u4_share_disp_buf)
3642 {
3643 pic_wd += (PAD_LEN_Y_H << 1);
3644 pic_ht += (PAD_LEN_Y_V << 2);
3645
3646 }
3647
3648 }
3649
3650 if(ps_dec->u4_app_disp_width > pic_wd)
3651 pic_wd = ps_dec->u4_app_disp_width;
3652 if(0 == ps_dec->u4_share_disp_buf)
3653 ps_ctl_op->u4_num_disp_bufs = 1;
3654 else
3655 {
3656 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3657 {
3658 UWORD32 level, width_mbs, height_mbs;
3659
3660 level = ps_dec->u4_level_at_init;
3661 width_mbs = ps_dec->u2_frm_wd_in_mbs;
3662 height_mbs = ps_dec->u2_frm_ht_in_mbs;
3663
3664 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1)
3665 && (ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames
3666 != 64))
3667 {
3668 ps_ctl_op->u4_num_disp_bufs =
3669 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 2;
3670 }
3671 else
3672 {
3673 /*if VUI is not present assume maximum possible refrence frames for the level,
3674 * as max reorder frames*/
3675 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new(
3676 level, width_mbs, height_mbs);
3677 }
3678
3679 ps_ctl_op->u4_num_disp_bufs +=
3680 ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
3681 }
3682 else
3683 {
3684 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new(
3685 ps_dec->u4_level_at_init,
3686 (ps_dec->u4_width_at_init >> 4),
3687 (ps_dec->u4_height_at_init >> 4));
3688
3689 ps_ctl_op->u4_num_disp_bufs +=
3690 ps_ctl_op->u4_num_disp_bufs;
3691
3692 ps_ctl_op->u4_num_disp_bufs =
3693 MIN(ps_ctl_op->u4_num_disp_bufs,
3694 (ps_dec->u4_num_ref_frames_at_init
3695 + ps_dec->u4_num_reorder_frames_at_init));
3696
3697 }
3698
3699 ps_ctl_op->u4_num_disp_bufs = MAX(
3700 ps_ctl_op->u4_num_disp_bufs, 6);
3701 ps_ctl_op->u4_num_disp_bufs = MIN(
3702 ps_ctl_op->u4_num_disp_bufs, 32);
3703 }
3704
3705 ps_ctl_op->u4_error_code = ps_dec->i4_error_code;
3706
3707 ps_ctl_op->u4_frame_rate = 0; //make it proper
3708 ps_ctl_op->u4_bit_rate = 0; //make it proper
3709 ps_ctl_op->e_content_type = ps_dec->i4_content_type;
3710 ps_ctl_op->e_output_chroma_format = ps_dec->u1_chroma_format;
3711 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
3712
3713 if(ps_dec->u1_chroma_format == IV_YUV_420P)
3714 {
3715 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420;
3716 }
3717 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
3718 {
3719 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
3720 }
3721 else if(ps_dec->u1_chroma_format == IV_RGB_565)
3722 {
3723 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
3724 }
3725 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3726 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3727 {
3728 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
3729 }
3730
3731 else
3732 {
3733 //Invalid chroma format; Error code may be updated, verify in testing if needed
3734 ps_ctl_op->u4_error_code = ERROR_FEATURE_UNAVAIL;
3735 return IV_FAIL;
3736 }
3737
3738 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
3739 {
3740 ps_ctl_op->u4_min_in_buf_size[i] = MIN_IN_BUF_SIZE;
3741 }
3742
3743 /*!*/
3744 if(ps_dec->u1_chroma_format == IV_YUV_420P)
3745 {
3746 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
3747 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
3748 >> 2;
3749 ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht)
3750 >> 2;
3751 }
3752 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
3753 {
3754 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
3755 * 2;
3756 ps_ctl_op->u4_min_out_buf_size[1] =
3757 ps_ctl_op->u4_min_out_buf_size[2] = 0;
3758 }
3759 else if(ps_dec->u1_chroma_format == IV_RGB_565)
3760 {
3761 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
3762 * 2;
3763 ps_ctl_op->u4_min_out_buf_size[1] =
3764 ps_ctl_op->u4_min_out_buf_size[2] = 0;
3765 }
3766 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3767 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3768 {
3769 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
3770 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
3771 >> 1;
3772 ps_ctl_op->u4_min_out_buf_size[2] = 0;
3773 }
3774
3775 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
3776 return IV_SUCCESS;
3777 }
3778
3779 /*****************************************************************************/
3780 /* */
3781 /* Function Name : ih264d_get_buf_info */
3782 /* */
3783 /* Description : */
3784 /* */
3785 /* Inputs :iv_obj_t decoder handle */
3786 /* :pv_api_ip pointer to input structure */
3787 /* :pv_api_op pointer to output structure */
3788 /* Globals : <Does it use any global variables?> */
3789 /* Outputs : */
3790 /* Returns : void */
3791 /* */
3792 /* Issues : none */
3793 /* */
3794 /* Revision History: */
3795 /* */
3796 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3797 /* 22 10 2008 100356 Draft */
3798 /* */
3799 /*****************************************************************************/
ih264d_get_buf_info(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3800 WORD32 ih264d_get_buf_info(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3801 {
3802
3803 dec_struct_t * ps_dec;
3804 UWORD8 i = 0; // Default for 420P format
3805 UWORD16 pic_wd, pic_ht;
3806 ivd_ctl_getbufinfo_op_t *ps_ctl_op =
3807 (ivd_ctl_getbufinfo_op_t*)pv_api_op;
3808 UNUSED(pv_api_ip);
3809 ps_ctl_op->u4_error_code = 0;
3810
3811 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3812
3813 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
3814 if(ps_dec->u1_chroma_format == IV_YUV_420P)
3815 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420;
3816 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
3817 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
3818 else if(ps_dec->u1_chroma_format == IV_RGB_565)
3819 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
3820 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3821 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3822 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
3823
3824 else
3825 {
3826 //Invalid chroma format; Error code may be updated, verify in testing if needed
3827 return IV_FAIL;
3828 }
3829
3830 ps_ctl_op->u4_num_disp_bufs = 1;
3831
3832 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
3833 {
3834 ps_ctl_op->u4_min_in_buf_size[i] = MIN_IN_BUF_SIZE;
3835 }
3836
3837 pic_wd = ps_dec->u4_width_at_init;
3838 pic_ht = ps_dec->u4_height_at_init;
3839
3840 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3841 {
3842
3843 if(0 == ps_dec->u4_share_disp_buf)
3844 {
3845 pic_wd = ps_dec->u2_disp_width;
3846 pic_ht = ps_dec->u2_disp_height;
3847
3848 }
3849 else
3850 {
3851 pic_wd = ps_dec->u2_frm_wd_y;
3852 pic_ht = ps_dec->u2_frm_ht_y;
3853 }
3854
3855 }
3856 else
3857 {
3858 if(1 == ps_dec->u4_share_disp_buf)
3859 {
3860 pic_wd += (PAD_LEN_Y_H << 1);
3861 pic_ht += (PAD_LEN_Y_V << 2);
3862
3863 }
3864 }
3865
3866 if((WORD32)ps_dec->u4_app_disp_width > pic_wd)
3867 pic_wd = ps_dec->u4_app_disp_width;
3868
3869 if(0 == ps_dec->u4_share_disp_buf)
3870 ps_ctl_op->u4_num_disp_bufs = 1;
3871 else
3872 {
3873 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3874 {
3875 UWORD32 level, width_mbs, height_mbs;
3876
3877 level = ps_dec->u4_level_at_init;
3878 width_mbs = ps_dec->u2_frm_wd_in_mbs;
3879 height_mbs = ps_dec->u2_frm_ht_in_mbs;
3880
3881 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1)
3882 && (ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames
3883 != 64))
3884 {
3885 ps_ctl_op->u4_num_disp_bufs =
3886 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 2;
3887 }
3888 else
3889 {
3890 /*if VUI is not present assume maximum possible refrence frames for the level,
3891 * as max reorder frames*/
3892 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new(
3893 level, width_mbs, height_mbs);
3894 }
3895
3896 ps_ctl_op->u4_num_disp_bufs +=
3897 ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
3898
3899 }
3900 else
3901 {
3902 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new(
3903 ps_dec->u4_level_at_init,
3904 (ps_dec->u4_width_at_init >> 4),
3905 (ps_dec->u4_height_at_init >> 4));
3906
3907 ps_ctl_op->u4_num_disp_bufs +=
3908 ps_ctl_op->u4_num_disp_bufs;
3909
3910 ps_ctl_op->u4_num_disp_bufs =
3911 MIN(ps_ctl_op->u4_num_disp_bufs,
3912 (ps_dec->u4_num_ref_frames_at_init
3913 + ps_dec->u4_num_reorder_frames_at_init));
3914
3915 }
3916
3917 ps_ctl_op->u4_num_disp_bufs = MAX(
3918 ps_ctl_op->u4_num_disp_bufs, 6);
3919 ps_ctl_op->u4_num_disp_bufs = MIN(
3920 ps_ctl_op->u4_num_disp_bufs, 32);
3921 }
3922
3923 /*!*/
3924 if(ps_dec->u1_chroma_format == IV_YUV_420P)
3925 {
3926 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
3927 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
3928 >> 2;
3929 ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht)
3930 >> 2;
3931 }
3932 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
3933 {
3934 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
3935 * 2;
3936 ps_ctl_op->u4_min_out_buf_size[1] =
3937 ps_ctl_op->u4_min_out_buf_size[2] = 0;
3938 }
3939 else if(ps_dec->u1_chroma_format == IV_RGB_565)
3940 {
3941 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
3942 * 2;
3943 ps_ctl_op->u4_min_out_buf_size[1] =
3944 ps_ctl_op->u4_min_out_buf_size[2] = 0;
3945 }
3946 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3947 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3948 {
3949 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
3950 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
3951 >> 1;
3952 ps_ctl_op->u4_min_out_buf_size[2] = 0;
3953 }
3954 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
3955
3956 return IV_SUCCESS;
3957 }
3958
3959 /*****************************************************************************/
3960 /* */
3961 /* Function Name : ih264d_set_params */
3962 /* */
3963 /* Description : */
3964 /* */
3965 /* Inputs :iv_obj_t decoder handle */
3966 /* :pv_api_ip pointer to input structure */
3967 /* :pv_api_op pointer to output structure */
3968 /* Outputs : */
3969 /* Returns : void */
3970 /* */
3971 /* Issues : none */
3972 /* */
3973 /* Revision History: */
3974 /* */
3975 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3976 /* 22 10 2008 100356 Draft */
3977 /* */
3978 /*****************************************************************************/
ih264d_set_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3979 WORD32 ih264d_set_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3980 {
3981
3982 dec_struct_t * ps_dec;
3983 WORD32 ret = IV_SUCCESS;
3984
3985 ivd_ctl_set_config_ip_t *ps_ctl_ip =
3986 (ivd_ctl_set_config_ip_t *)pv_api_ip;
3987 ivd_ctl_set_config_op_t *ps_ctl_op =
3988 (ivd_ctl_set_config_op_t *)pv_api_op;
3989
3990 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3991
3992 ps_dec->u4_skip_frm_mask = 0;
3993
3994 ps_ctl_op->u4_error_code = 0;
3995
3996 ps_dec->i4_app_skip_mode = ps_ctl_ip->e_frm_skip_mode;
3997
3998 /*Is it really supported test it when you so the corner testing using test app*/
3999
4000 if(ps_ctl_ip->e_frm_skip_mode != IVD_SKIP_NONE)
4001 {
4002
4003 if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_P)
4004 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT;
4005 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_B)
4006 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT;
4007 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_PB)
4008 {
4009 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT;
4010 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT;
4011 }
4012 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_I)
4013 ps_dec->u4_skip_frm_mask |= 1 << I_SLC_BIT;
4014 else
4015 {
4016 //dynamic parameter not supported
4017 //Put an appropriate error code to return the error..
4018 //when you do the error code tests and after that remove this comment
4019 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
4020 ret = IV_FAIL;
4021 }
4022 }
4023
4024 if((0 != ps_dec->u4_app_disp_width)
4025 && (ps_ctl_ip->u4_disp_wd
4026 != ps_dec->u4_app_disp_width))
4027 {
4028 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
4029 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID;
4030 ret = IV_FAIL;
4031 }
4032 else
4033 {
4034 if((ps_ctl_ip->u4_disp_wd >= ps_dec->u2_pic_wd)/* && (ps_ctl_ip->u4_disp_wd <= ps_dec->u4_width_at_init) */)
4035 {
4036 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd;
4037 }
4038 else if((0 == ps_dec->i4_header_decoded) /*&& (ps_ctl_ip->u4_disp_wd <= ps_dec->u4_width_at_init)*/)
4039 {
4040 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd;
4041 }
4042 else if(ps_ctl_ip->u4_disp_wd == 0)
4043 {
4044 ps_dec->u4_app_disp_width = 0;
4045 }
4046 else
4047 {
4048 /*
4049 * Set the display width to zero. This will ensure that the wrong value we had stored (0xFFFFFFFF)
4050 * does not propogate.
4051 */
4052 ps_dec->u4_app_disp_width = 0;
4053 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
4054 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID;
4055 ret = IV_FAIL;
4056 }
4057 }
4058 if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_FRAME)
4059 ps_dec->i4_decode_header = 0;
4060 else if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_HEADER)
4061 ps_dec->i4_decode_header = 1;
4062 else
4063 {
4064 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
4065 ps_dec->i4_decode_header = 1;
4066 ret = IV_FAIL;
4067 }
4068
4069 return ret;
4070
4071 }
4072
4073 /*****************************************************************************/
4074 /* */
4075 /* Function Name : ih264d_set_default_params */
4076 /* */
4077 /* Description : */
4078 /* */
4079 /* Inputs :iv_obj_t decoder handle */
4080 /* :pv_api_ip pointer to input structure */
4081 /* :pv_api_op pointer to output structure */
4082 /* Outputs : */
4083 /* Returns : void */
4084 /* */
4085 /* Issues : none */
4086 /* */
4087 /* Revision History: */
4088 /* */
4089 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
4090 /* 08 08 2011 100421 Copied from set_params */
4091 /* */
4092 /*****************************************************************************/
ih264d_set_default_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)4093 WORD32 ih264d_set_default_params(iv_obj_t *dec_hdl,
4094 void *pv_api_ip,
4095 void *pv_api_op)
4096 {
4097
4098 dec_struct_t * ps_dec;
4099 WORD32 ret = IV_SUCCESS;
4100
4101 ivd_ctl_set_config_op_t *ps_ctl_op =
4102 (ivd_ctl_set_config_op_t *)pv_api_op;
4103 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
4104 UNUSED(pv_api_ip);
4105
4106
4107 {
4108 ps_dec->u4_app_disp_width = 0;
4109 ps_dec->u4_skip_frm_mask = 0;
4110 ps_dec->i4_decode_header = 1;
4111
4112 ps_ctl_op->u4_error_code = 0;
4113 }
4114
4115
4116 return ret;
4117 }
4118
4119 /*****************************************************************************/
4120 /* */
4121 /* Function Name : ih264d_reset */
4122 /* */
4123 /* Description : */
4124 /* */
4125 /* Inputs :iv_obj_t decoder handle */
4126 /* :pv_api_ip pointer to input structure */
4127 /* :pv_api_op pointer to output structure */
4128 /* Globals : <Does it use any global variables?> */
4129 /* Outputs : */
4130 /* Returns : void */
4131 /* */
4132 /* Issues : none */
4133 /* */
4134 /* Revision History: */
4135 /* */
4136 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
4137 /* 22 10 2008 100356 Draft */
4138 /* */
4139 /*****************************************************************************/
ih264d_reset(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)4140 WORD32 ih264d_reset(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4141 {
4142 dec_struct_t * ps_dec;
4143 ivd_ctl_reset_op_t *ps_ctl_op = (ivd_ctl_reset_op_t *)pv_api_op;
4144 UNUSED(pv_api_ip);
4145 ps_ctl_op->u4_error_code = 0;
4146
4147 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
4148 //CHECK
4149 if(ps_dec != NULL)
4150 {
4151
4152 ih264d_init_decoder(ps_dec);
4153
4154 /*
4155 memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t));
4156 memset(ps_dec->u4_disp_buf_mapping, 0, (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
4157 memset(ps_dec->u4_disp_buf_to_be_freed, 0, (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
4158 */
4159 }
4160 else
4161 {
4162 H264_DEC_DEBUG_PRINT(
4163 "\nReset called without Initializing the decoder\n");
4164 ps_ctl_op->u4_error_code = ERROR_INIT_NOT_DONE;
4165 }
4166
4167 return IV_SUCCESS;
4168 }
4169
4170 /*****************************************************************************/
4171 /* */
4172 /* Function Name : ih264d_ctl */
4173 /* */
4174 /* Description : */
4175 /* */
4176 /* Inputs :iv_obj_t decoder handle */
4177 /* :pv_api_ip pointer to input structure */
4178 /* :pv_api_op pointer to output structure */
4179 /* Outputs : */
4180 /* Returns : void */
4181 /* */
4182 /* Issues : none */
4183 /* */
4184 /* Revision History: */
4185 /* */
4186 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
4187 /* 22 10 2008 100356 Draft */
4188 /* */
4189 /*****************************************************************************/
ih264d_ctl(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)4190 WORD32 ih264d_ctl(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4191 {
4192 ivd_ctl_set_config_ip_t *ps_ctl_ip;
4193 ivd_ctl_set_config_op_t *ps_ctl_op;
4194 WORD32 ret = IV_SUCCESS;
4195 UWORD32 subcommand;
4196 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4197
4198 if(ps_dec->init_done != 1)
4199 {
4200 //Return proper Error Code
4201 return IV_FAIL;
4202 }
4203 ps_ctl_ip = (ivd_ctl_set_config_ip_t*)pv_api_ip;
4204 ps_ctl_op = (ivd_ctl_set_config_op_t*)pv_api_op;
4205 ps_ctl_op->u4_error_code = 0;
4206 subcommand = ps_ctl_ip->e_sub_cmd;
4207
4208 switch(subcommand)
4209 {
4210 case IVD_CMD_CTL_GETPARAMS:
4211 ret = ih264d_get_status(dec_hdl, (void *)pv_api_ip,
4212 (void *)pv_api_op);
4213 break;
4214 case IVD_CMD_CTL_SETPARAMS:
4215 ret = ih264d_set_params(dec_hdl, (void *)pv_api_ip,
4216 (void *)pv_api_op);
4217 break;
4218 case IVD_CMD_CTL_RESET:
4219 ret = ih264d_reset(dec_hdl, (void *)pv_api_ip, (void *)pv_api_op);
4220 break;
4221 case IVD_CMD_CTL_SETDEFAULT:
4222 ret = ih264d_set_default_params(dec_hdl, (void *)pv_api_ip,
4223 (void *)pv_api_op);
4224 break;
4225 case IVD_CMD_CTL_FLUSH:
4226 ret = ih264d_set_flush_mode(dec_hdl, (void *)pv_api_ip,
4227 (void *)pv_api_op);
4228 break;
4229 case IVD_CMD_CTL_GETBUFINFO:
4230 ret = ih264d_get_buf_info(dec_hdl, (void *)pv_api_ip,
4231 (void *)pv_api_op);
4232 break;
4233 case IVD_CMD_CTL_GETVERSION:
4234 ret = ih264d_get_version(dec_hdl, (void *)pv_api_ip,
4235 (void *)pv_api_op);
4236 break;
4237 case IH264D_CMD_CTL_DEGRADE:
4238 ret = ih264d_set_degrade(dec_hdl, (void *)pv_api_ip,
4239 (void *)pv_api_op);
4240 break;
4241
4242 case IH264D_CMD_CTL_SET_NUM_CORES:
4243 ret = ih264d_set_num_cores(dec_hdl, (void *)pv_api_ip,
4244 (void *)pv_api_op);
4245 break;
4246 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS:
4247 ret = ih264d_get_frame_dimensions(dec_hdl, (void *)pv_api_ip,
4248 (void *)pv_api_op);
4249 break;
4250 case IH264D_CMD_CTL_SET_PROCESSOR:
4251 ret = ih264d_set_processor(dec_hdl, (void *)pv_api_ip,
4252 (void *)pv_api_op);
4253 break;
4254 default:
4255 H264_DEC_DEBUG_PRINT("\ndo nothing\n")
4256 ;
4257 break;
4258 }
4259
4260 return ret;
4261 }
4262 /*****************************************************************************/
4263 /* */
4264 /* Function Name : ih264d_rel_display_frame */
4265 /* */
4266 /* Description : */
4267 /* */
4268 /* Inputs :iv_obj_t decoder handle */
4269 /* :pv_api_ip pointer to input structure */
4270 /* :pv_api_op pointer to output structure */
4271 /* Outputs : */
4272 /* Returns : void */
4273 /* */
4274 /* Issues : none */
4275 /* */
4276 /* Revision History: */
4277 /* */
4278 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
4279 /* 22 10 2008 100356 Draft */
4280 /* */
4281 /*****************************************************************************/
ih264d_rel_display_frame(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)4282 WORD32 ih264d_rel_display_frame(iv_obj_t *dec_hdl,
4283 void *pv_api_ip,
4284 void *pv_api_op)
4285 {
4286
4287 ivd_rel_display_frame_ip_t *ps_rel_ip;
4288 ivd_rel_display_frame_op_t *ps_rel_op;
4289 UWORD32 buf_released = 0;
4290
4291 UWORD32 u4_ts = -1;
4292 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4293
4294 ps_rel_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip;
4295 ps_rel_op = (ivd_rel_display_frame_op_t *)pv_api_op;
4296 ps_rel_op->u4_error_code = 0;
4297 u4_ts = ps_rel_ip->u4_disp_buf_id;
4298
4299 if(0 == ps_dec->u4_share_disp_buf)
4300 {
4301 ps_dec->u4_disp_buf_mapping[u4_ts] = 0;
4302 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 0;
4303 return IV_SUCCESS;
4304 }
4305
4306 if(ps_dec->pv_pic_buf_mgr != NULL)
4307 {
4308 if(1 == ps_dec->u4_disp_buf_mapping[u4_ts])
4309 {
4310 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
4311 ps_rel_ip->u4_disp_buf_id,
4312 BUF_MGR_IO);
4313 ps_dec->u4_disp_buf_mapping[u4_ts] = 0;
4314 buf_released = 1;
4315 }
4316 }
4317
4318 if((1 == ps_dec->u4_share_disp_buf) && (0 == buf_released))
4319 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 1;
4320
4321 return IV_SUCCESS;
4322 }
4323
4324 /**
4325 *******************************************************************************
4326 *
4327 * @brief
4328 * Sets degrade params
4329 *
4330 * @par Description:
4331 * Sets degrade params.
4332 * Refer to ih264d_ctl_degrade_ip_t definition for details
4333 *
4334 * @param[in] ps_codec_obj
4335 * Pointer to codec object at API level
4336 *
4337 * @param[in] pv_api_ip
4338 * Pointer to input argument structure
4339 *
4340 * @param[out] pv_api_op
4341 * Pointer to output argument structure
4342 *
4343 * @returns Status
4344 *
4345 * @remarks
4346 *
4347 *
4348 *******************************************************************************
4349 */
4350
ih264d_set_degrade(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)4351 WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj,
4352 void *pv_api_ip,
4353 void *pv_api_op)
4354 {
4355 ih264d_ctl_degrade_ip_t *ps_ip;
4356 ih264d_ctl_degrade_op_t *ps_op;
4357 dec_struct_t *ps_codec = (dec_struct_t *)ps_codec_obj->pv_codec_handle;
4358
4359 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip;
4360 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op;
4361
4362 ps_codec->i4_degrade_type = ps_ip->i4_degrade_type;
4363 ps_codec->i4_nondegrade_interval = ps_ip->i4_nondegrade_interval;
4364 ps_codec->i4_degrade_pics = ps_ip->i4_degrade_pics;
4365
4366 ps_op->u4_error_code = 0;
4367 ps_codec->i4_degrade_pic_cnt = 0;
4368
4369 return IV_SUCCESS;
4370 }
4371
ih264d_get_frame_dimensions(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)4372 WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl,
4373 void *pv_api_ip,
4374 void *pv_api_op)
4375 {
4376 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip;
4377 ih264d_ctl_get_frame_dimensions_op_t *ps_op;
4378 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4379 UWORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset;
4380
4381 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
4382
4383 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op;
4384 UNUSED(ps_ip);
4385 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
4386 {
4387 disp_wd = ps_dec->u2_disp_width;
4388 disp_ht = ps_dec->u2_disp_height;
4389
4390 if(0 == ps_dec->u4_share_disp_buf)
4391 {
4392 buffer_wd = disp_wd;
4393 buffer_ht = disp_ht;
4394 }
4395 else
4396 {
4397 buffer_wd = ps_dec->u2_frm_wd_y;
4398 buffer_ht = ps_dec->u2_frm_ht_y;
4399 }
4400 }
4401 else
4402 {
4403 disp_wd = ps_dec->u4_width_at_init;
4404 disp_ht = ps_dec->u4_height_at_init;
4405
4406 if(0 == ps_dec->u4_share_disp_buf)
4407 {
4408 buffer_wd = disp_wd;
4409 buffer_ht = disp_ht;
4410 }
4411 else
4412 {
4413 buffer_wd = ALIGN16(disp_wd) + (PAD_LEN_Y_H << 1);
4414 buffer_ht = ALIGN16(disp_ht) + (PAD_LEN_Y_V << 2);
4415 }
4416 }
4417 if(ps_dec->u4_app_disp_width > buffer_wd)
4418 buffer_wd = ps_dec->u4_app_disp_width;
4419
4420 if(0 == ps_dec->u4_share_disp_buf)
4421 {
4422 x_offset = 0;
4423 y_offset = 0;
4424 }
4425 else
4426 {
4427 y_offset = (PAD_LEN_Y_V << 1);
4428 x_offset = PAD_LEN_Y_H;
4429
4430 if((NULL != ps_dec->ps_sps) && (1 == (ps_dec->ps_sps->u1_is_valid))
4431 && (0 != ps_dec->u2_crop_offset_y))
4432 {
4433 y_offset += ps_dec->u2_crop_offset_y / ps_dec->u2_frm_wd_y;
4434 x_offset += ps_dec->u2_crop_offset_y % ps_dec->u2_frm_wd_y;
4435 }
4436 }
4437
4438 ps_op->u4_disp_wd[0] = disp_wd;
4439 ps_op->u4_disp_ht[0] = disp_ht;
4440 ps_op->u4_buffer_wd[0] = buffer_wd;
4441 ps_op->u4_buffer_ht[0] = buffer_ht;
4442 ps_op->u4_x_offset[0] = x_offset;
4443 ps_op->u4_y_offset[0] = y_offset;
4444
4445 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1)
4446 >> 1);
4447 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1)
4448 >> 1);
4449 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0]
4450 >> 1);
4451 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0]
4452 >> 1);
4453 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] =
4454 (ps_op->u4_x_offset[0] >> 1);
4455 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] =
4456 (ps_op->u4_y_offset[0] >> 1);
4457
4458 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
4459 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
4460 {
4461 ps_op->u4_disp_wd[2] = 0;
4462 ps_op->u4_disp_ht[2] = 0;
4463 ps_op->u4_buffer_wd[2] = 0;
4464 ps_op->u4_buffer_ht[2] = 0;
4465 ps_op->u4_x_offset[2] = 0;
4466 ps_op->u4_y_offset[2] = 0;
4467
4468 ps_op->u4_disp_wd[1] <<= 1;
4469 ps_op->u4_buffer_wd[1] <<= 1;
4470 ps_op->u4_x_offset[1] <<= 1;
4471 }
4472
4473 return IV_SUCCESS;
4474
4475 }
4476
ih264d_set_num_cores(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)4477 WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4478 {
4479 ih264d_ctl_set_num_cores_ip_t *ps_ip;
4480 ih264d_ctl_set_num_cores_op_t *ps_op;
4481 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4482
4483 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip;
4484 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op;
4485 ps_op->u4_error_code = 0;
4486 ps_dec->u4_num_cores = ps_ip->u4_num_cores;
4487 if(ps_dec->u4_num_cores == 1)
4488 {
4489 ps_dec->u1_separate_parse = 0;
4490 ps_dec->pi4_ctxt_save_register_dec = ps_dec->pi4_ctxt_save_register;
4491 }
4492 else
4493 {
4494 ps_dec->u1_separate_parse = 1;
4495 }
4496
4497 /*using only upto three threads currently*/
4498 if(ps_dec->u4_num_cores > 3)
4499 ps_dec->u4_num_cores = 3;
4500
4501 return IV_SUCCESS;
4502 }
4503
ih264d_fill_output_struct_from_context(dec_struct_t * ps_dec,ivd_video_decode_op_t * ps_dec_op)4504 void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec,
4505 ivd_video_decode_op_t *ps_dec_op)
4506 {
4507 if((ps_dec_op->u4_error_code & 0xff)
4508 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
4509 {
4510 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
4511 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
4512 }
4513 ps_dec_op->e_pic_type = ps_dec->i4_frametype;
4514
4515 ps_dec_op->u4_new_seq = 0;
4516 ps_dec_op->u4_output_present = ps_dec->u4_output_present;
4517 ps_dec_op->u4_progressive_frame_flag =
4518 ps_dec->s_disp_op.u4_progressive_frame_flag;
4519
4520 ps_dec_op->u4_is_ref_flag = 1;
4521 if(ps_dec_op->u4_frame_decoded_flag)
4522 {
4523 if(ps_dec->ps_cur_slice->u1_nal_ref_idc == 0)
4524 ps_dec_op->u4_is_ref_flag = 0;
4525 }
4526
4527 ps_dec_op->e_output_format = ps_dec->s_disp_op.e_output_format;
4528 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf;
4529 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type;
4530 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts;
4531 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
4532 }
4533
4534 /*****************************************************************************/
4535 /* */
4536 /* Function Name : ih264d_api_function */
4537 /* */
4538 /* Description : */
4539 /* */
4540 /* Inputs :iv_obj_t decoder handle */
4541 /* :pv_api_ip pointer to input structure */
4542 /* :pv_api_op pointer to output structure */
4543 /* Outputs : */
4544 /* Returns : void */
4545 /* */
4546 /* Issues : none */
4547 /* */
4548 /* Revision History: */
4549 /* */
4550 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
4551 /* 22 10 2008 100356 Draft */
4552 /* */
4553 /*****************************************************************************/
ih264d_api_function(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)4554 IV_API_CALL_STATUS_T ih264d_api_function(iv_obj_t *dec_hdl,
4555 void *pv_api_ip,
4556 void *pv_api_op)
4557 {
4558 UWORD32 command;
4559 UWORD32 *pu2_ptr_cmd;
4560 UWORD32 u4_api_ret;
4561 IV_API_CALL_STATUS_T e_status;
4562 e_status = api_check_struct_sanity(dec_hdl, pv_api_ip, pv_api_op);
4563
4564 if(e_status != IV_SUCCESS)
4565 {
4566 UWORD32 *ptr_err;
4567
4568 ptr_err = (UWORD32 *)pv_api_op;
4569 UNUSED(ptr_err);
4570 H264_DEC_DEBUG_PRINT("error code = %d\n", *(ptr_err + 1));
4571 return IV_FAIL;
4572 }
4573
4574 pu2_ptr_cmd = (UWORD32 *)pv_api_ip;
4575 pu2_ptr_cmd++;
4576
4577 command = *pu2_ptr_cmd;
4578 // H264_DEC_DEBUG_PRINT("inside lib = %d\n",command);
4579 switch(command)
4580 {
4581
4582 case IV_CMD_GET_NUM_MEM_REC:
4583 u4_api_ret = ih264d_get_num_rec((void *)pv_api_ip,
4584 (void *)pv_api_op);
4585
4586 break;
4587 case IV_CMD_FILL_NUM_MEM_REC:
4588
4589 u4_api_ret = ih264d_fill_num_mem_rec((void *)pv_api_ip,
4590 (void *)pv_api_op);
4591 break;
4592 case IV_CMD_INIT:
4593 u4_api_ret = ih264d_init(dec_hdl, (void *)pv_api_ip,
4594 (void *)pv_api_op);
4595 break;
4596
4597 case IVD_CMD_VIDEO_DECODE:
4598 u4_api_ret = ih264d_video_decode(dec_hdl, (void *)pv_api_ip,
4599 (void *)pv_api_op);
4600 break;
4601
4602 case IVD_CMD_GET_DISPLAY_FRAME:
4603 u4_api_ret = ih264d_get_display_frame(dec_hdl, (void *)pv_api_ip,
4604 (void *)pv_api_op);
4605
4606 break;
4607
4608 case IVD_CMD_SET_DISPLAY_FRAME:
4609 u4_api_ret = ih264d_set_display_frame(dec_hdl, (void *)pv_api_ip,
4610 (void *)pv_api_op);
4611
4612 break;
4613
4614 case IVD_CMD_REL_DISPLAY_FRAME:
4615 u4_api_ret = ih264d_rel_display_frame(dec_hdl, (void *)pv_api_ip,
4616 (void *)pv_api_op);
4617 break;
4618
4619 case IV_CMD_RETRIEVE_MEMREC:
4620 u4_api_ret = ih264d_clr(dec_hdl, (void *)pv_api_ip,
4621 (void *)pv_api_op);
4622 break;
4623
4624 case IVD_CMD_VIDEO_CTL:
4625 u4_api_ret = ih264d_ctl(dec_hdl, (void *)pv_api_ip,
4626 (void *)pv_api_op);
4627 break;
4628 default:
4629 u4_api_ret = IV_FAIL;
4630 break;
4631 }
4632
4633 return u4_api_ret;
4634 }
4635