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2 Copyright (C) 2013 Xiph.Org Foundation and contributors.
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4 modification, are permitted provided that the following conditions
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6 - Redistributions of source code must retain the above copyright notice,
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8 - Redistributions in binary form must reproduce the above copyright
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15 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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18 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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26 ***********************************************************************/
27
28 #ifndef SILK_MACROS_ARMv4_H
29 #define SILK_MACROS_ARMv4_H
30
31 /* (a32 * (opus_int32)((opus_int16)(b32))) >> 16 output have to be 32bit int */
32 #undef silk_SMULWB
silk_SMULWB_armv4(opus_int32 a,opus_int16 b)33 static OPUS_INLINE opus_int32 silk_SMULWB_armv4(opus_int32 a, opus_int16 b)
34 {
35 unsigned rd_lo;
36 int rd_hi;
37 __asm__(
38 "#silk_SMULWB\n\t"
39 "smull %0, %1, %2, %3\n\t"
40 : "=&r"(rd_lo), "=&r"(rd_hi)
41 : "%r"(a), "r"(b<<16)
42 );
43 return rd_hi;
44 }
45 #define silk_SMULWB(a, b) (silk_SMULWB_armv4(a, b))
46
47 /* a32 + (b32 * (opus_int32)((opus_int16)(c32))) >> 16 output have to be 32bit int */
48 #undef silk_SMLAWB
49 #define silk_SMLAWB(a, b, c) ((a) + silk_SMULWB(b, c))
50
51 /* (a32 * (b32 >> 16)) >> 16 */
52 #undef silk_SMULWT
silk_SMULWT_armv4(opus_int32 a,opus_int32 b)53 static OPUS_INLINE opus_int32 silk_SMULWT_armv4(opus_int32 a, opus_int32 b)
54 {
55 unsigned rd_lo;
56 int rd_hi;
57 __asm__(
58 "#silk_SMULWT\n\t"
59 "smull %0, %1, %2, %3\n\t"
60 : "=&r"(rd_lo), "=&r"(rd_hi)
61 : "%r"(a), "r"(b&~0xFFFF)
62 );
63 return rd_hi;
64 }
65 #define silk_SMULWT(a, b) (silk_SMULWT_armv4(a, b))
66
67 /* a32 + (b32 * (c32 >> 16)) >> 16 */
68 #undef silk_SMLAWT
69 #define silk_SMLAWT(a, b, c) ((a) + silk_SMULWT(b, c))
70
71 /* (a32 * b32) >> 16 */
72 #undef silk_SMULWW
silk_SMULWW_armv4(opus_int32 a,opus_int32 b)73 static OPUS_INLINE opus_int32 silk_SMULWW_armv4(opus_int32 a, opus_int32 b)
74 {
75 unsigned rd_lo;
76 int rd_hi;
77 __asm__(
78 "#silk_SMULWW\n\t"
79 "smull %0, %1, %2, %3\n\t"
80 : "=&r"(rd_lo), "=&r"(rd_hi)
81 : "%r"(a), "r"(b)
82 );
83 return (rd_hi<<16)+(rd_lo>>16);
84 }
85 #define silk_SMULWW(a, b) (silk_SMULWW_armv4(a, b))
86
87 #undef silk_SMLAWW
silk_SMLAWW_armv4(opus_int32 a,opus_int32 b,opus_int32 c)88 static OPUS_INLINE opus_int32 silk_SMLAWW_armv4(opus_int32 a, opus_int32 b,
89 opus_int32 c)
90 {
91 unsigned rd_lo;
92 int rd_hi;
93 __asm__(
94 "#silk_SMLAWW\n\t"
95 "smull %0, %1, %2, %3\n\t"
96 : "=&r"(rd_lo), "=&r"(rd_hi)
97 : "%r"(b), "r"(c)
98 );
99 return a+(rd_hi<<16)+(rd_lo>>16);
100 }
101 #define silk_SMLAWW(a, b, c) (silk_SMLAWW_armv4(a, b, c))
102
103 #endif /* SILK_MACROS_ARMv4_H */
104