1# Copyright (c) 2014, Google Inc.
2#
3# Permission to use, copy, modify, and/or distribute this software for any
4# purpose with or without fee is hereby granted, provided that the above
5# copyright notice and this permission notice appear in all copies.
6#
7# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
8# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
9# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
10# SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
12# OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
13# CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
14
15# This file contains a pre-compiled version of chacha_vec.c for ARM. This is
16# needed to support switching on NEON code at runtime. If the whole of OpenSSL
17# were to be compiled with the needed flags to build chacha_vec.c, then it
18# wouldn't be possible to run on non-NEON systems.
19#
20# This file was generated by chacha_vec_arm_generate.go using the following
21# compiler command:
22#
23#     /opt/gcc-linaro-4.9-2014.11-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-gcc -O3 -mcpu=cortex-a8 -mfpu=neon -fpic -DASM_GEN -I ../../include -S chacha_vec.c -o -
24
25#if !defined(OPENSSL_NO_ASM)
26
27	.syntax unified
28	.cpu cortex-a8
29	.eabi_attribute 27, 3
30
31# EABI attribute 28 sets whether VFP register arguments were used to build this
32# file. If object files are inconsistent on this point, the linker will refuse
33# to link them. Thus we report whatever the compiler expects since we don't use
34# VFP arguments.
35
36#if defined(__ARM_PCS_VFP)
37	.eabi_attribute 28, 1
38#else
39	.eabi_attribute 28, 0
40#endif
41
42	.fpu neon
43	.eabi_attribute 20, 1
44	.eabi_attribute 21, 1
45	.eabi_attribute 23, 3
46	.eabi_attribute 24, 1
47	.eabi_attribute 25, 1
48	.eabi_attribute 26, 2
49	.eabi_attribute 30, 2
50	.eabi_attribute 34, 1
51	.eabi_attribute 18, 4
52	.thumb
53	.file	"chacha_vec.c"
54	.text
55	.align	2
56	.global	CRYPTO_chacha_20_neon
57	.hidden	CRYPTO_chacha_20_neon
58	.thumb
59	.thumb_func
60	.type	CRYPTO_chacha_20_neon, %function
61CRYPTO_chacha_20_neon:
62	@ args = 8, pretend = 0, frame = 152
63	@ frame_needed = 1, uses_anonymous_args = 0
64	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
65	mov	r8, r3
66	vpush.64	{d8, d9, d10, d11, d12, d13, d14, d15}
67	mov	r9, r2
68	ldr	r4, .L91+16
69	mov	fp, r0
70	mov	r10, r1
71	mov	lr, r8
72.LPIC16:
73	add	r4, pc
74	sub	sp, sp, #156
75	add	r7, sp, #0
76	sub	sp, sp, #112
77	add	r6, r7, #144
78	str	r0, [r7, #88]
79	str	r1, [r7, #12]
80	str	r2, [r7, #8]
81	ldmia	r4, {r0, r1, r2, r3}
82	add	r4, sp, #15
83	bic	r4, r4, #15
84	ldr	ip, [r7, #256]
85	str	r4, [r7, #84]
86	mov	r5, r4
87	adds	r4, r4, #64
88	adds	r5, r5, #80
89	str	r8, [r7, #68]
90	stmia	r4, {r0, r1, r2, r3}
91	movw	r4, #43691
92	ldr	r0, [ip]	@ unaligned
93	movt	r4, 43690
94	ldr	r1, [ip, #4]	@ unaligned
95	ldr	r3, [r7, #84]
96	ldr	r2, [r8, #8]	@ unaligned
97	mov	r8, #0
98	stmia	r6!, {r0, r1}
99	mov	r6, r5
100	ldr	r1, [lr, #4]	@ unaligned
101	ldr	r0, [lr]	@ unaligned
102	vldr	d24, [r3, #64]
103	vldr	d25, [r3, #72]
104	ldr	r3, [lr, #12]	@ unaligned
105	str	r5, [r7, #80]
106	stmia	r5!, {r0, r1, r2, r3}
107	ldr	r0, [lr, #16]!	@ unaligned
108	ldr	r2, [r7, #84]
109	umull	r4, r5, r9, r4
110	vldr	d26, [r2, #80]
111	vldr	d27, [r2, #88]
112	ldr	r1, [lr, #4]	@ unaligned
113	ldr	r2, [lr, #8]	@ unaligned
114	ldr	r3, [lr, #12]	@ unaligned
115	ldr	r4, [r7, #260]
116	stmia	r6!, {r0, r1, r2, r3}
117	ldr	r3, [ip]
118	ldr	r1, [r7, #84]
119	ldr	r2, [ip, #4]
120	str	r3, [r7, #64]
121	vldr	d28, [r1, #80]
122	vldr	d29, [r1, #88]
123	str	r3, [r7, #136]
124	lsrs	r3, r5, #7
125	str	r4, [r7, #128]
126	str	r2, [r7, #140]
127	str	r8, [r7, #132]
128	str	r2, [r7, #60]
129	vldr	d22, [r7, #128]
130	vldr	d23, [r7, #136]
131	beq	.L26
132	lsls	r2, r3, #8
133	ldr	r5, [r1, #64]
134	sub	r3, r2, r3, lsl #6
135	ldr	r2, [r1, #68]
136	vldr	d0, .L91
137	vldr	d1, .L91+8
138	adds	r4, r4, #2
139	str	r5, [r7, #56]
140	str	r2, [r7, #52]
141	ldr	r5, [r1, #72]
142	ldr	r2, [r1, #76]
143	str	r3, [r7, #4]
144	str	r5, [r7, #48]
145	str	r2, [r7, #44]
146	mov	r2, fp
147	str	r4, [r7, #72]
148	adds	r3, r2, r3
149	str	r10, [r7, #76]
150	str	r3, [r7, #16]
151.L4:
152	ldr	r5, [r7, #68]
153	add	r8, r7, #44
154	ldr	r4, [r7, #72]
155	vadd.i32	q3, q11, q0
156	ldmia	r8, {r8, r9, r10, fp}
157	vmov	q8, q14  @ v4si
158	ldr	r2, [r5, #4]
159	vmov	q1, q13  @ v4si
160	ldr	r3, [r5]
161	vmov	q9, q12  @ v4si
162	ldr	lr, [r5, #20]
163	vmov	q2, q11  @ v4si
164	mov	r0, r2
165	ldr	r2, [r5, #8]
166	str	r3, [r7, #108]
167	mov	r3, r5
168	ldr	ip, [r5, #16]
169	vmov	q15, q14  @ v4si
170	mov	r1, r2
171	ldr	r2, [r5, #12]
172	ldr	r5, [r5, #24]
173	vmov	q5, q13  @ v4si
174	ldr	r6, [r3, #28]
175	vmov	q10, q12  @ v4si
176	ldr	r3, [r7, #64]
177	str	r5, [r7, #116]
178	movs	r5, #10
179	str	r6, [r7, #120]
180	str	r4, [r7, #112]
181	ldr	r6, [r7, #60]
182	str	r8, [r7, #96]
183	mov	r8, r10
184	ldr	r4, [r7, #108]
185	mov	r10, r9
186	ldr	r9, [r7, #116]
187	str	lr, [r7, #104]
188	mov	lr, r3
189	str	r5, [r7, #92]
190	movs	r5, #0
191	str	r6, [r7, #124]
192	str	r5, [r7, #100]
193	b	.L92
194.L93:
195	.align	3
196.L91:
197	.word	1
198	.word	0
199	.word	0
200	.word	0
201	.word	.LANCHOR0-(.LPIC16+4)
202.L92:
203.L3:
204	vadd.i32	q9, q9, q1
205	add	r3, r8, r0
206	vadd.i32	q10, q10, q5
207	add	r5, fp, r4
208	veor	q3, q3, q9
209	mov	r6, r3
210	veor	q2, q2, q10
211	ldr	r3, [r7, #96]
212	str	r5, [r7, #116]
213	add	r10, r10, r1
214	vrev32.16	q3, q3
215	eor	lr, lr, r10
216	vadd.i32	q8, q8, q3
217	vrev32.16	q2, q2
218	vadd.i32	q15, q15, q2
219	mov	fp, r3
220	ldr	r3, [r7, #112]
221	veor	q4, q8, q1
222	str	r6, [r7, #112]
223	veor	q6, q15, q5
224	eors	r3, r3, r5
225	mov	r5, r6
226	ldr	r6, [r7, #100]
227	vshl.i32	q1, q4, #12
228	vshl.i32	q5, q6, #12
229	add	fp, fp, r2
230	eors	r6, r6, r5
231	ror	r3, r3, #16
232	vsri.32	q1, q4, #20
233	ror	lr, lr, #16
234	mov	r5, r6
235	ldr	r6, [r7, #124]
236	vsri.32	q5, q6, #20
237	str	r3, [r7, #124]
238	eor	r6, r6, fp
239	ror	r5, r5, #16
240	vadd.i32	q9, q9, q1
241	add	r9, r9, lr
242	ror	r3, r6, #16
243	ldr	r6, [r7, #124]
244	vadd.i32	q10, q10, q5
245	str	r3, [r7, #108]
246	veor	q4, q9, q3
247	add	ip, ip, r6
248	ldr	r6, [r7, #104]
249	veor	q6, q10, q2
250	eor	r4, ip, r4
251	eor	r1, r9, r1
252	vshl.i32	q3, q4, #8
253	mov	r8, r6
254	ldr	r6, [r7, #120]
255	vshl.i32	q2, q6, #8
256	ror	r4, r4, #20
257	add	r6, r6, r3
258	vsri.32	q3, q4, #24
259	str	r6, [r7, #104]
260	eors	r2, r2, r6
261	ldr	r6, [r7, #116]
262	vsri.32	q2, q6, #24
263	add	r8, r8, r5
264	ror	r2, r2, #20
265	adds	r6, r4, r6
266	vadd.i32	q4, q8, q3
267	eor	r0, r8, r0
268	vadd.i32	q15, q15, q2
269	mov	r3, r6
270	ldr	r6, [r7, #112]
271	veor	q6, q4, q1
272	ror	r0, r0, #20
273	str	r3, [r7, #112]
274	veor	q5, q15, q5
275	adds	r6, r0, r6
276	str	r6, [r7, #120]
277	mov	r6, r3
278	ldr	r3, [r7, #124]
279	vshl.i32	q8, q6, #7
280	add	fp, fp, r2
281	eors	r3, r3, r6
282	ldr	r6, [r7, #120]
283	vshl.i32	q1, q5, #7
284	ror	r1, r1, #20
285	eors	r5, r5, r6
286	vsri.32	q8, q6, #25
287	ldr	r6, [r7, #108]
288	ror	r3, r3, #24
289	ror	r5, r5, #24
290	vsri.32	q1, q5, #25
291	str	r5, [r7, #116]
292	eor	r6, fp, r6
293	ldr	r5, [r7, #116]
294	add	r10, r10, r1
295	add	ip, r3, ip
296	vext.32	q8, q8, q8, #1
297	str	ip, [r7, #124]
298	add	ip, r5, r8
299	ldr	r5, [r7, #104]
300	eor	lr, r10, lr
301	ror	r6, r6, #24
302	vext.32	q1, q1, q1, #1
303	add	r8, r6, r5
304	vadd.i32	q9, q9, q8
305	ldr	r5, [r7, #124]
306	vext.32	q3, q3, q3, #3
307	vadd.i32	q10, q10, q1
308	ror	lr, lr, #24
309	eor	r0, ip, r0
310	vext.32	q2, q2, q2, #3
311	add	r9, r9, lr
312	eors	r4, r4, r5
313	veor	q3, q9, q3
314	ldr	r5, [r7, #112]
315	eor	r1, r9, r1
316	ror	r0, r0, #25
317	veor	q2, q10, q2
318	adds	r5, r0, r5
319	vext.32	q4, q4, q4, #2
320	str	r5, [r7, #112]
321	ldr	r5, [r7, #120]
322	ror	r1, r1, #25
323	vrev32.16	q3, q3
324	eor	r2, r8, r2
325	vext.32	q15, q15, q15, #2
326	adds	r5, r1, r5
327	vadd.i32	q4, q4, q3
328	ror	r4, r4, #25
329	vrev32.16	q2, q2
330	str	r5, [r7, #100]
331	vadd.i32	q15, q15, q2
332	eors	r3, r3, r5
333	ldr	r5, [r7, #112]
334	add	fp, fp, r4
335	veor	q8, q4, q8
336	ror	r2, r2, #25
337	veor	q1, q15, q1
338	eor	lr, fp, lr
339	eors	r6, r6, r5
340	ror	r3, r3, #16
341	ldr	r5, [r7, #116]
342	add	r10, r10, r2
343	str	r3, [r7, #120]
344	ror	lr, lr, #16
345	ldr	r3, [r7, #120]
346	eor	r5, r10, r5
347	vshl.i32	q5, q8, #12
348	add	ip, lr, ip
349	vshl.i32	q6, q1, #12
350	str	ip, [r7, #104]
351	add	ip, r3, r8
352	str	ip, [r7, #116]
353	ldr	r3, [r7, #124]
354	ror	r5, r5, #16
355	vsri.32	q5, q8, #20
356	ror	r6, r6, #16
357	add	ip, r5, r3
358	ldr	r3, [r7, #104]
359	vsri.32	q6, q1, #20
360	add	r9, r9, r6
361	eor	r2, ip, r2
362	eors	r4, r4, r3
363	ldr	r3, [r7, #116]
364	eor	r0, r9, r0
365	vadd.i32	q9, q9, q5
366	ror	r4, r4, #20
367	eors	r1, r1, r3
368	vadd.i32	q10, q10, q6
369	ror	r3, r2, #20
370	str	r3, [r7, #108]
371	ldr	r3, [r7, #112]
372	veor	q3, q9, q3
373	ror	r0, r0, #20
374	add	r8, r4, fp
375	veor	q2, q10, q2
376	add	fp, r0, r3
377	ldr	r3, [r7, #100]
378	ror	r1, r1, #20
379	mov	r2, r8
380	vshl.i32	q8, q3, #8
381	str	r8, [r7, #96]
382	add	r8, r1, r3
383	ldr	r3, [r7, #108]
384	vmov	q1, q6  @ v4si
385	vshl.i32	q6, q2, #8
386	eor	r6, fp, r6
387	add	r10, r10, r3
388	ldr	r3, [r7, #120]
389	vsri.32	q8, q3, #24
390	eor	lr, r2, lr
391	eor	r3, r8, r3
392	ror	r2, r6, #24
393	vsri.32	q6, q2, #24
394	eor	r5, r10, r5
395	str	r2, [r7, #124]
396	ror	r2, r3, #24
397	ldr	r3, [r7, #104]
398	vmov	q3, q8  @ v4si
399	vadd.i32	q15, q15, q6
400	ror	lr, lr, #24
401	vadd.i32	q8, q4, q8
402	ror	r6, r5, #24
403	add	r5, lr, r3
404	ldr	r3, [r7, #124]
405	veor	q4, q8, q5
406	add	ip, ip, r6
407	vmov	q2, q6  @ v4si
408	add	r9, r9, r3
409	veor	q6, q15, q1
410	ldr	r3, [r7, #116]
411	vshl.i32	q1, q4, #7
412	str	r2, [r7, #112]
413	add	r3, r3, r2
414	str	r3, [r7, #120]
415	vshl.i32	q5, q6, #7
416	eors	r1, r1, r3
417	ldr	r3, [r7, #108]
418	vsri.32	q1, q4, #25
419	eors	r4, r4, r5
420	eor	r0, r9, r0
421	eor	r2, ip, r3
422	vsri.32	q5, q6, #25
423	ldr	r3, [r7, #92]
424	ror	r4, r4, #25
425	str	r6, [r7, #100]
426	ror	r0, r0, #25
427	subs	r3, r3, #1
428	str	r5, [r7, #104]
429	ror	r1, r1, #25
430	ror	r2, r2, #25
431	vext.32	q15, q15, q15, #2
432	str	r3, [r7, #92]
433	vext.32	q2, q2, q2, #1
434	vext.32	q8, q8, q8, #2
435	vext.32	q3, q3, q3, #1
436	vext.32	q5, q5, q5, #3
437	vext.32	q1, q1, q1, #3
438	bne	.L3
439	ldr	r3, [r7, #80]
440	vadd.i32	q4, q12, q10
441	str	r9, [r7, #116]
442	mov	r9, r10
443	mov	r10, r8
444	ldr	r8, [r7, #96]
445	str	lr, [r7, #96]
446	mov	lr, r5
447	ldr	r5, [r7, #56]
448	vadd.i32	q5, q13, q5
449	ldr	r6, [r7, #76]
450	vadd.i32	q15, q14, q15
451	add	fp, fp, r5
452	ldr	r5, [r7, #52]
453	str	r4, [r7, #108]
454	vadd.i32	q7, q14, q8
455	ldr	r4, [r7, #112]
456	add	r5, r10, r5
457	str	r3, [r7, #112]
458	vadd.i32	q2, q11, q2
459	ldr	r3, [r6, #12]	@ unaligned
460	vadd.i32	q6, q12, q9
461	str	r0, [r7, #92]
462	vadd.i32	q1, q13, q1
463	ldr	r0, [r6]	@ unaligned
464	vadd.i32	q11, q11, q0
465	str	r1, [r7, #40]
466	str	r2, [r7, #36]
467	vadd.i32	q3, q11, q3
468	ldr	r1, [r6, #4]	@ unaligned
469	vadd.i32	q11, q11, q0
470	ldr	r2, [r6, #8]	@ unaligned
471	str	r5, [r7, #104]
472	vadd.i32	q11, q11, q0
473	ldr	r5, [r7, #112]
474	ldr	r10, [r7, #80]
475	stmia	r5!, {r0, r1, r2, r3}
476	mov	r5, r10
477	ldr	r0, [r7, #84]
478	ldr	r2, [r7, #48]
479	ldr	r3, [r7, #72]
480	vldr	d20, [r0, #80]
481	vldr	d21, [r0, #88]
482	add	r9, r9, r2
483	veor	q10, q10, q4
484	ldr	r2, [r7, #44]
485	adds	r1, r4, r3
486	str	r1, [r7, #28]
487	add	r2, r8, r2
488	str	r2, [r7, #32]
489	vstr	d20, [r0, #80]
490	vstr	d21, [r0, #88]
491	ldmia	r5!, {r0, r1, r2, r3}
492	ldr	r4, [r7, #96]
493	ldr	r5, [r7, #64]
494	add	r4, r4, r5
495	ldr	r5, [r7, #124]
496	str	r4, [r7, #96]
497	ldr	r4, [r7, #60]
498	add	r5, r5, r4
499	ldr	r4, [r7, #88]
500	str	r5, [r7, #24]
501	mov	r5, r10
502	str	r0, [r4]	@ unaligned
503	mov	r0, r4
504	str	r1, [r4, #4]	@ unaligned
505	mov	r8, r0
506	str	r2, [r0, #8]	@ unaligned
507	mov	r4, r10
508	str	r3, [r0, #12]	@ unaligned
509	ldr	r0, [r6, #16]!	@ unaligned
510	ldr	r1, [r6, #4]	@ unaligned
511	ldr	r2, [r6, #8]	@ unaligned
512	ldr	r3, [r6, #12]	@ unaligned
513	ldr	r6, [r7, #76]
514	stmia	r5!, {r0, r1, r2, r3}
515	mov	r5, r10
516	ldr	r3, [r7, #84]
517	vldr	d20, [r3, #80]
518	vldr	d21, [r3, #88]
519	veor	q10, q10, q5
520	vstr	d20, [r3, #80]
521	vstr	d21, [r3, #88]
522	ldmia	r4!, {r0, r1, r2, r3}
523	mov	r4, r8
524	str	r0, [r8, #16]	@ unaligned
525	str	r1, [r8, #20]	@ unaligned
526	str	r2, [r8, #24]	@ unaligned
527	str	r3, [r8, #28]	@ unaligned
528	mov	r8, r4
529	ldr	r0, [r6, #32]!	@ unaligned
530	str	r10, [r7, #124]
531	ldr	r1, [r6, #4]	@ unaligned
532	ldr	r2, [r6, #8]	@ unaligned
533	ldr	r3, [r6, #12]	@ unaligned
534	ldr	r6, [r7, #76]
535	stmia	r5!, {r0, r1, r2, r3}
536	mov	r5, r10
537	ldr	r2, [r7, #84]
538	vldr	d16, [r2, #80]
539	vldr	d17, [r2, #88]
540	veor	q15, q8, q15
541	vstr	d30, [r2, #80]
542	vstr	d31, [r2, #88]
543	ldmia	r10!, {r0, r1, r2, r3}
544	str	r0, [r4, #32]	@ unaligned
545	str	r1, [r4, #36]	@ unaligned
546	str	r2, [r4, #40]	@ unaligned
547	str	r3, [r4, #44]	@ unaligned
548	ldr	r0, [r6, #48]!	@ unaligned
549	ldr	r1, [r6, #4]	@ unaligned
550	ldr	r2, [r6, #8]	@ unaligned
551	ldr	r3, [r6, #12]	@ unaligned
552	ldr	r6, [r7, #76]
553	stmia	r5!, {r0, r1, r2, r3}
554	ldr	r1, [r7, #84]
555	vldr	d18, [r1, #80]
556	vldr	d19, [r1, #88]
557	veor	q9, q9, q2
558	vstr	d18, [r1, #80]
559	vstr	d19, [r1, #88]
560	ldr	r3, [r7, #112]
561	ldr	r5, [r7, #80]
562	mov	r10, r3
563	ldmia	r10!, {r0, r1, r2, r3}
564	str	r0, [r4, #48]	@ unaligned
565	str	r1, [r4, #52]	@ unaligned
566	str	r2, [r4, #56]	@ unaligned
567	str	r3, [r4, #60]	@ unaligned
568	ldr	r0, [r6, #64]!	@ unaligned
569	ldr	r1, [r6, #4]	@ unaligned
570	ldr	r2, [r6, #8]	@ unaligned
571	ldr	r3, [r6, #12]	@ unaligned
572	ldr	r6, [r7, #76]
573	stmia	r5!, {r0, r1, r2, r3}
574	ldr	r1, [r7, #84]
575	ldr	r3, [r7, #112]
576	ldr	r5, [r7, #80]
577	vldr	d18, [r1, #80]
578	vldr	d19, [r1, #88]
579	veor	q9, q9, q6
580	mov	r10, r3
581	str	r5, [r7, #20]
582	vstr	d18, [r1, #80]
583	vstr	d19, [r1, #88]
584	ldmia	r10!, {r0, r1, r2, r3}
585	str	r1, [r4, #68]	@ unaligned
586	str	r2, [r4, #72]	@ unaligned
587	str	r3, [r4, #76]	@ unaligned
588	str	r0, [r4, #64]	@ unaligned
589	ldr	r0, [r6, #80]!	@ unaligned
590	ldr	r1, [r6, #4]	@ unaligned
591	ldr	r2, [r6, #8]	@ unaligned
592	ldr	r3, [r6, #12]	@ unaligned
593	ldr	r6, [r7, #76]
594	stmia	r5!, {r0, r1, r2, r3}
595	ldr	r1, [r7, #84]
596	ldr	r3, [r7, #20]
597	ldr	r5, [r7, #80]
598	vldr	d18, [r1, #80]
599	vldr	d19, [r1, #88]
600	veor	q1, q9, q1
601	mov	r10, r3
602	vstr	d2, [r1, #80]
603	vstr	d3, [r1, #88]
604	ldmia	r10!, {r0, r1, r2, r3}
605	mov	r10, r5
606	str	r0, [r4, #80]	@ unaligned
607	str	r1, [r4, #84]	@ unaligned
608	str	r2, [r4, #88]	@ unaligned
609	str	r3, [r4, #92]	@ unaligned
610	ldr	r0, [r6, #96]!	@ unaligned
611	ldr	r1, [r6, #4]	@ unaligned
612	ldr	r2, [r6, #8]	@ unaligned
613	ldr	r3, [r6, #12]	@ unaligned
614	ldr	r6, [r7, #76]
615	stmia	r5!, {r0, r1, r2, r3}
616	mov	r5, r10
617	ldr	r3, [r7, #84]
618	vldr	d16, [r3, #80]
619	vldr	d17, [r3, #88]
620	veor	q8, q8, q7
621	vstr	d16, [r3, #80]
622	vstr	d17, [r3, #88]
623	ldmia	r10!, {r0, r1, r2, r3}
624	str	r0, [r4, #96]	@ unaligned
625	str	r1, [r4, #100]	@ unaligned
626	str	r2, [r4, #104]	@ unaligned
627	str	r3, [r4, #108]	@ unaligned
628	ldr	r0, [r6, #112]!	@ unaligned
629	ldr	r1, [r6, #4]	@ unaligned
630	ldr	r2, [r6, #8]	@ unaligned
631	ldr	r3, [r6, #12]	@ unaligned
632	mov	r6, r5
633	stmia	r6!, {r0, r1, r2, r3}
634	ldr	r3, [r7, #84]
635	vldr	d16, [r3, #80]
636	vldr	d17, [r3, #88]
637	veor	q8, q8, q3
638	vstr	d16, [r3, #80]
639	vstr	d17, [r3, #88]
640	ldmia	r5!, {r0, r1, r2, r3}
641	str	r1, [r4, #116]	@ unaligned
642	ldr	r1, [r7, #76]
643	str	r0, [r4, #112]	@ unaligned
644	str	r2, [r4, #120]	@ unaligned
645	str	r3, [r4, #124]	@ unaligned
646	ldr	r3, [r1, #128]
647	ldr	r2, [r7, #104]
648	eor	r3, fp, r3
649	str	r3, [r4, #128]
650	ldr	r3, [r1, #132]
651	eors	r2, r2, r3
652	str	r2, [r8, #132]
653	ldr	r3, [r1, #136]
654	ldr	r5, [r7, #68]
655	ldr	r6, [r7, #32]
656	eor	r3, r9, r3
657	str	r3, [r4, #136]
658	ldr	r3, [r1, #140]
659	ldr	r0, [r7, #92]
660	eors	r3, r3, r6
661	ldr	r6, [r7, #108]
662	str	r3, [r4, #140]
663	ldr	r3, [r5]
664	ldr	r2, [r1, #144]
665	add	r6, r6, r3
666	eors	r2, r2, r6
667	str	r2, [r4, #144]
668	ldr	r2, [r5, #4]
669	ldr	r3, [r1, #148]
670	add	r0, r0, r2
671	ldr	r6, [r7, #36]
672	eors	r3, r3, r0
673	ldr	r0, [r7, #40]
674	str	r3, [r4, #148]
675	ldr	r2, [r5, #8]
676	ldr	r3, [r1, #152]
677	add	r0, r0, r2
678	eors	r3, r3, r0
679	str	r3, [r4, #152]
680	ldr	r2, [r5, #12]
681	mov	r0, r4
682	ldr	r3, [r1, #156]
683	mov	r4, r1
684	add	r6, r6, r2
685	mov	r1, r0
686	eors	r3, r3, r6
687	str	r3, [r0, #156]
688	ldr	r2, [r5, #16]
689	ldr	r3, [r4, #160]
690	add	ip, ip, r2
691	eor	r3, ip, r3
692	str	r3, [r1, #160]
693	ldr	r2, [r5, #20]
694	ldr	r3, [r4, #164]
695	add	lr, lr, r2
696	ldr	r2, [r7, #116]
697	eor	r3, lr, r3
698	str	r3, [r1, #164]
699	ldr	r6, [r5, #24]
700	mov	lr, r4
701	ldr	r3, [r4, #168]
702	add	r2, r2, r6
703	mov	r6, r4
704	eors	r3, r3, r2
705	str	r3, [r1, #168]
706	ldr	r5, [r5, #28]
707	mov	r2, r1
708	ldr	r3, [r4, #172]
709	ldr	r0, [r7, #120]
710	add	r0, r0, r5
711	ldr	r5, [r7, #24]
712	eors	r3, r3, r0
713	str	r3, [r1, #172]
714	ldr	r3, [r7, #72]
715	ldr	r4, [r4, #176]
716	ldr	r1, [r7, #28]
717	eors	r4, r4, r1
718	adds	r1, r3, #3
719	str	r4, [r2, #176]
720	ldr	r3, [r7, #100]
721	ldr	r0, [lr, #180]
722	str	r1, [r7, #72]
723	eors	r3, r3, r0
724	mov	r0, r3
725	mov	r3, r2
726	str	r0, [r2, #180]
727	adds	r3, r3, #192
728	ldr	r1, [lr, #184]
729	ldr	r2, [r7, #96]
730	eors	r1, r1, r2
731	str	r1, [r3, #-8]
732	ldr	r2, [lr, #188]
733	mov	r1, r6
734	adds	r1, r1, #192
735	str	r1, [r7, #76]
736	eors	r2, r2, r5
737	str	r2, [r3, #-4]
738	ldr	r2, [r7, #16]
739	str	r3, [r7, #88]
740	cmp	r2, r3
741	bne	.L4
742	ldr	r3, [r7, #12]
743	ldr	r2, [r7, #4]
744	add	r3, r3, r2
745	str	r3, [r7, #12]
746.L2:
747	ldr	r1, [r7, #8]
748	movw	r2, #43691
749	movt	r2, 43690
750	umull	r2, r3, r1, r2
751	lsr	fp, r3, #7
752	lsl	r3, fp, #8
753	sub	fp, r3, fp, lsl #6
754	rsb	fp, fp, r1
755	lsrs	fp, fp, #6
756	beq	.L6
757	ldr	r5, [r7, #12]
758	ldr	r4, [r7, #16]
759	ldr	r6, [r7, #84]
760	ldr	lr, [r7, #80]
761	vldr	d30, .L94
762	vldr	d31, .L94+8
763	str	fp, [r7, #120]
764	str	fp, [r7, #124]
765.L8:
766	vmov	q2, q11  @ v4si
767	movs	r3, #10
768	vmov	q8, q14  @ v4si
769	vmov	q9, q13  @ v4si
770	vmov	q10, q12  @ v4si
771.L7:
772	vadd.i32	q10, q10, q9
773	subs	r3, r3, #1
774	veor	q3, q2, q10
775	vrev32.16	q3, q3
776	vadd.i32	q8, q8, q3
777	veor	q9, q8, q9
778	vshl.i32	q2, q9, #12
779	vsri.32	q2, q9, #20
780	vadd.i32	q10, q10, q2
781	veor	q3, q10, q3
782	vshl.i32	q9, q3, #8
783	vsri.32	q9, q3, #24
784	vadd.i32	q8, q8, q9
785	vext.32	q9, q9, q9, #3
786	veor	q2, q8, q2
787	vext.32	q8, q8, q8, #2
788	vshl.i32	q3, q2, #7
789	vsri.32	q3, q2, #25
790	vext.32	q3, q3, q3, #1
791	vadd.i32	q10, q10, q3
792	veor	q9, q10, q9
793	vrev32.16	q9, q9
794	vadd.i32	q8, q8, q9
795	veor	q3, q8, q3
796	vshl.i32	q2, q3, #12
797	vsri.32	q2, q3, #20
798	vadd.i32	q10, q10, q2
799	vmov	q3, q2  @ v4si
800	veor	q9, q10, q9
801	vshl.i32	q2, q9, #8
802	vsri.32	q2, q9, #24
803	vadd.i32	q8, q8, q2
804	vext.32	q2, q2, q2, #1
805	veor	q3, q8, q3
806	vext.32	q8, q8, q8, #2
807	vshl.i32	q9, q3, #7
808	vsri.32	q9, q3, #25
809	vext.32	q9, q9, q9, #3
810	bne	.L7
811	ldr	r0, [r5]	@ unaligned
812	vadd.i32	q1, q12, q10
813	ldr	r1, [r5, #4]	@ unaligned
814	mov	ip, lr
815	ldr	r2, [r5, #8]	@ unaligned
816	mov	r9, lr
817	ldr	r3, [r5, #12]	@ unaligned
818	mov	r10, r5
819	vadd.i32	q9, q13, q9
820	mov	r8, lr
821	vadd.i32	q8, q14, q8
822	stmia	ip!, {r0, r1, r2, r3}
823	mov	ip, lr
824	vldr	d20, [r6, #80]
825	vldr	d21, [r6, #88]
826	vadd.i32	q3, q11, q2
827	veor	q10, q10, q1
828	vadd.i32	q11, q11, q15
829	vstr	d20, [r6, #80]
830	vstr	d21, [r6, #88]
831	ldmia	r9!, {r0, r1, r2, r3}
832	mov	r9, r5
833	str	r0, [r4]	@ unaligned
834	str	r1, [r4, #4]	@ unaligned
835	str	r2, [r4, #8]	@ unaligned
836	str	r3, [r4, #12]	@ unaligned
837	ldr	r0, [r10, #16]!	@ unaligned
838	ldr	r1, [r10, #4]	@ unaligned
839	ldr	r2, [r10, #8]	@ unaligned
840	ldr	r3, [r10, #12]	@ unaligned
841	add	r10, r4, #48
842	adds	r4, r4, #64
843	stmia	r8!, {r0, r1, r2, r3}
844	mov	r8, lr
845	vldr	d20, [r6, #80]
846	vldr	d21, [r6, #88]
847	veor	q10, q10, q9
848	vstr	d20, [r6, #80]
849	vstr	d21, [r6, #88]
850	ldmia	ip!, {r0, r1, r2, r3}
851	mov	ip, lr
852	str	r0, [r4, #-48]	@ unaligned
853	str	r1, [r4, #-44]	@ unaligned
854	str	r2, [r4, #-40]	@ unaligned
855	str	r3, [r4, #-36]	@ unaligned
856	ldr	r0, [r9, #32]!	@ unaligned
857	ldr	r1, [r9, #4]	@ unaligned
858	ldr	r2, [r9, #8]	@ unaligned
859	ldr	r3, [r9, #12]	@ unaligned
860	mov	r9, r5
861	adds	r5, r5, #64
862	stmia	r8!, {r0, r1, r2, r3}
863	mov	r8, lr
864	vldr	d18, [r6, #80]
865	vldr	d19, [r6, #88]
866	veor	q9, q9, q8
867	vstr	d18, [r6, #80]
868	vstr	d19, [r6, #88]
869	ldmia	ip!, {r0, r1, r2, r3}
870	mov	ip, lr
871	str	r0, [r4, #-32]	@ unaligned
872	str	r1, [r4, #-28]	@ unaligned
873	str	r2, [r4, #-24]	@ unaligned
874	str	r3, [r4, #-20]	@ unaligned
875	ldr	r0, [r9, #48]!	@ unaligned
876	ldr	r1, [r9, #4]	@ unaligned
877	ldr	r2, [r9, #8]	@ unaligned
878	ldr	r3, [r9, #12]	@ unaligned
879	stmia	r8!, {r0, r1, r2, r3}
880	vldr	d16, [r6, #80]
881	vldr	d17, [r6, #88]
882	veor	q8, q8, q3
883	vstr	d16, [r6, #80]
884	vstr	d17, [r6, #88]
885	ldmia	ip!, {r0, r1, r2, r3}
886	str	r0, [r4, #-16]	@ unaligned
887	str	r1, [r4, #-12]	@ unaligned
888	str	r3, [r10, #12]	@ unaligned
889	ldr	r3, [r7, #124]
890	str	r2, [r10, #8]	@ unaligned
891	cmp	r3, #1
892	beq	.L87
893	movs	r3, #1
894	str	r3, [r7, #124]
895	b	.L8
896.L95:
897	.align	3
898.L94:
899	.word	1
900	.word	0
901	.word	0
902	.word	0
903.L87:
904	ldr	fp, [r7, #120]
905	ldr	r3, [r7, #12]
906	lsl	fp, fp, #6
907	add	r3, r3, fp
908	str	r3, [r7, #12]
909	ldr	r3, [r7, #16]
910	add	r3, r3, fp
911	str	r3, [r7, #16]
912.L6:
913	ldr	r3, [r7, #8]
914	ands	r9, r3, #63
915	beq	.L1
916	vmov	q3, q11  @ v4si
917	movs	r3, #10
918	vmov	q8, q14  @ v4si
919	mov	r5, r9
920	vmov	q15, q13  @ v4si
921	vmov	q10, q12  @ v4si
922.L10:
923	vadd.i32	q10, q10, q15
924	subs	r3, r3, #1
925	veor	q9, q3, q10
926	vrev32.16	q9, q9
927	vadd.i32	q8, q8, q9
928	veor	q15, q8, q15
929	vshl.i32	q3, q15, #12
930	vsri.32	q3, q15, #20
931	vadd.i32	q10, q10, q3
932	veor	q15, q10, q9
933	vshl.i32	q9, q15, #8
934	vsri.32	q9, q15, #24
935	vadd.i32	q8, q8, q9
936	vext.32	q9, q9, q9, #3
937	veor	q3, q8, q3
938	vext.32	q8, q8, q8, #2
939	vshl.i32	q15, q3, #7
940	vsri.32	q15, q3, #25
941	vext.32	q15, q15, q15, #1
942	vadd.i32	q10, q10, q15
943	veor	q9, q10, q9
944	vrev32.16	q9, q9
945	vadd.i32	q8, q8, q9
946	veor	q15, q8, q15
947	vshl.i32	q3, q15, #12
948	vsri.32	q3, q15, #20
949	vadd.i32	q10, q10, q3
950	vmov	q15, q3  @ v4si
951	veor	q9, q10, q9
952	vshl.i32	q3, q9, #8
953	vsri.32	q3, q9, #24
954	vadd.i32	q8, q8, q3
955	vext.32	q3, q3, q3, #1
956	veor	q9, q8, q15
957	vext.32	q8, q8, q8, #2
958	vshl.i32	q15, q9, #7
959	vsri.32	q15, q9, #25
960	vext.32	q15, q15, q15, #3
961	bne	.L10
962	cmp	r5, #15
963	mov	r9, r5
964	bhi	.L88
965	vadd.i32	q12, q12, q10
966	ldr	r3, [r7, #84]
967	vst1.64	{d24-d25}, [r3:128]
968.L14:
969	ldr	r3, [r7, #8]
970	and	r2, r3, #48
971	cmp	r9, r2
972	bls	.L1
973	ldr	r6, [r7, #16]
974	add	r3, r2, #16
975	ldr	r1, [r7, #12]
976	rsb	ip, r2, r9
977	adds	r0, r1, r2
978	mov	r4, r6
979	add	r1, r1, r3
980	add	r4, r4, r2
981	add	r3, r3, r6
982	cmp	r0, r3
983	it	cc
984	cmpcc	r4, r1
985	ite	cs
986	movcs	r3, #1
987	movcc	r3, #0
988	cmp	ip, #18
989	ite	ls
990	movls	r3, #0
991	andhi	r3, r3, #1
992	cmp	r3, #0
993	beq	.L16
994	and	r1, r0, #7
995	mov	r3, r2
996	negs	r1, r1
997	and	r1, r1, #15
998	cmp	r1, ip
999	it	cs
1000	movcs	r1, ip
1001	cmp	r1, #0
1002	beq	.L17
1003	ldr	r5, [r7, #84]
1004	cmp	r1, #1
1005	ldrb	r0, [r0]	@ zero_extendqisi2
1006	add	r3, r2, #1
1007	ldrb	lr, [r5, r2]	@ zero_extendqisi2
1008	mov	r6, r5
1009	eor	r0, lr, r0
1010	strb	r0, [r4]
1011	beq	.L17
1012	ldr	r0, [r7, #12]
1013	cmp	r1, #2
1014	ldrb	r4, [r5, r3]	@ zero_extendqisi2
1015	ldr	r5, [r7, #16]
1016	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1017	eor	r0, r0, r4
1018	strb	r0, [r5, r3]
1019	add	r3, r2, #2
1020	beq	.L17
1021	ldr	r0, [r7, #12]
1022	cmp	r1, #3
1023	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1024	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1025	eor	r0, r0, r4
1026	strb	r0, [r5, r3]
1027	add	r3, r2, #3
1028	beq	.L17
1029	ldr	r0, [r7, #12]
1030	cmp	r1, #4
1031	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1032	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1033	eor	r0, r0, r4
1034	strb	r0, [r5, r3]
1035	add	r3, r2, #4
1036	beq	.L17
1037	ldr	r0, [r7, #12]
1038	cmp	r1, #5
1039	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1040	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1041	eor	r0, r0, r4
1042	strb	r0, [r5, r3]
1043	add	r3, r2, #5
1044	beq	.L17
1045	ldr	r0, [r7, #12]
1046	cmp	r1, #6
1047	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1048	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1049	eor	r0, r0, r4
1050	strb	r0, [r5, r3]
1051	add	r3, r2, #6
1052	beq	.L17
1053	ldr	r0, [r7, #12]
1054	cmp	r1, #7
1055	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1056	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1057	eor	r0, r0, r4
1058	strb	r0, [r5, r3]
1059	add	r3, r2, #7
1060	beq	.L17
1061	ldr	r0, [r7, #12]
1062	cmp	r1, #8
1063	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1064	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1065	eor	r0, r0, r4
1066	strb	r0, [r5, r3]
1067	add	r3, r2, #8
1068	beq	.L17
1069	ldr	r0, [r7, #12]
1070	cmp	r1, #9
1071	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1072	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1073	eor	r0, r0, r4
1074	strb	r0, [r5, r3]
1075	add	r3, r2, #9
1076	beq	.L17
1077	ldr	r0, [r7, #12]
1078	cmp	r1, #10
1079	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1080	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1081	eor	r0, r0, r4
1082	strb	r0, [r5, r3]
1083	add	r3, r2, #10
1084	beq	.L17
1085	ldr	r0, [r7, #12]
1086	cmp	r1, #11
1087	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1088	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1089	eor	r0, r0, r4
1090	strb	r0, [r5, r3]
1091	add	r3, r2, #11
1092	beq	.L17
1093	ldr	r0, [r7, #12]
1094	cmp	r1, #12
1095	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1096	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1097	eor	r0, r0, r4
1098	strb	r0, [r5, r3]
1099	add	r3, r2, #12
1100	beq	.L17
1101	ldr	r0, [r7, #12]
1102	cmp	r1, #13
1103	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1104	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1105	eor	r0, r0, r4
1106	strb	r0, [r5, r3]
1107	add	r3, r2, #13
1108	beq	.L17
1109	ldr	r0, [r7, #12]
1110	cmp	r1, #15
1111	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1112	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1113	eor	r0, r0, r4
1114	strb	r0, [r5, r3]
1115	add	r3, r2, #14
1116	bne	.L17
1117	ldr	r0, [r7, #12]
1118	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1119	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1120	eors	r0, r0, r4
1121	strb	r0, [r5, r3]
1122	add	r3, r2, #15
1123.L17:
1124	rsb	r4, r1, ip
1125	add	r0, ip, #-1
1126	sub	r6, r4, #16
1127	subs	r0, r0, r1
1128	cmp	r0, #14
1129	lsr	r6, r6, #4
1130	add	r6, r6, #1
1131	lsl	lr, r6, #4
1132	bls	.L19
1133	add	r2, r2, r1
1134	ldr	r1, [r7, #12]
1135	ldr	r5, [r7, #16]
1136	cmp	r6, #1
1137	add	r0, r1, r2
1138	ldr	r1, [r7, #84]
1139	add	r1, r1, r2
1140	vld1.64	{d18-d19}, [r0:64]
1141	add	r2, r2, r5
1142	vld1.8	{q8}, [r1]
1143	veor	q8, q8, q9
1144	vst1.8	{q8}, [r2]
1145	beq	.L20
1146	add	r8, r1, #16
1147	add	ip, r2, #16
1148	vldr	d18, [r0, #16]
1149	vldr	d19, [r0, #24]
1150	cmp	r6, #2
1151	vld1.8	{q8}, [r8]
1152	veor	q8, q8, q9
1153	vst1.8	{q8}, [ip]
1154	beq	.L20
1155	add	r8, r1, #32
1156	add	ip, r2, #32
1157	vldr	d18, [r0, #32]
1158	vldr	d19, [r0, #40]
1159	cmp	r6, #3
1160	vld1.8	{q8}, [r8]
1161	veor	q8, q8, q9
1162	vst1.8	{q8}, [ip]
1163	beq	.L20
1164	adds	r1, r1, #48
1165	adds	r2, r2, #48
1166	vldr	d18, [r0, #48]
1167	vldr	d19, [r0, #56]
1168	vld1.8	{q8}, [r1]
1169	veor	q8, q8, q9
1170	vst1.8	{q8}, [r2]
1171.L20:
1172	cmp	lr, r4
1173	add	r3, r3, lr
1174	beq	.L1
1175.L19:
1176	ldr	r4, [r7, #84]
1177	adds	r2, r3, #1
1178	ldr	r1, [r7, #12]
1179	cmp	r2, r9
1180	ldr	r5, [r7, #16]
1181	ldrb	r0, [r4, r3]	@ zero_extendqisi2
1182	ldrb	r1, [r1, r3]	@ zero_extendqisi2
1183	eor	r1, r1, r0
1184	strb	r1, [r5, r3]
1185	bcs	.L1
1186	ldr	r0, [r7, #12]
1187	adds	r1, r3, #2
1188	mov	r6, r4
1189	cmp	r9, r1
1190	ldrb	r4, [r4, r2]	@ zero_extendqisi2
1191	ldrb	r0, [r0, r2]	@ zero_extendqisi2
1192	eor	r0, r0, r4
1193	strb	r0, [r5, r2]
1194	bls	.L1
1195	ldr	r0, [r7, #12]
1196	adds	r2, r3, #3
1197	ldrb	r4, [r6, r1]	@ zero_extendqisi2
1198	cmp	r9, r2
1199	ldrb	r0, [r0, r1]	@ zero_extendqisi2
1200	eor	r0, r0, r4
1201	strb	r0, [r5, r1]
1202	bls	.L1
1203	ldr	r0, [r7, #12]
1204	adds	r1, r3, #4
1205	ldrb	r4, [r6, r2]	@ zero_extendqisi2
1206	cmp	r9, r1
1207	ldrb	r0, [r0, r2]	@ zero_extendqisi2
1208	eor	r0, r0, r4
1209	strb	r0, [r5, r2]
1210	bls	.L1
1211	ldr	r0, [r7, #12]
1212	adds	r2, r3, #5
1213	ldrb	r4, [r6, r1]	@ zero_extendqisi2
1214	cmp	r9, r2
1215	ldrb	r0, [r0, r1]	@ zero_extendqisi2
1216	eor	r0, r0, r4
1217	strb	r0, [r5, r1]
1218	bls	.L1
1219	ldr	r0, [r7, #12]
1220	adds	r1, r3, #6
1221	ldrb	r4, [r6, r2]	@ zero_extendqisi2
1222	cmp	r9, r1
1223	ldrb	r0, [r0, r2]	@ zero_extendqisi2
1224	eor	r0, r0, r4
1225	strb	r0, [r5, r2]
1226	bls	.L1
1227	ldr	r0, [r7, #12]
1228	adds	r2, r3, #7
1229	ldrb	r4, [r6, r1]	@ zero_extendqisi2
1230	cmp	r9, r2
1231	ldrb	r0, [r0, r1]	@ zero_extendqisi2
1232	eor	r0, r0, r4
1233	strb	r0, [r5, r1]
1234	bls	.L1
1235	ldr	r0, [r7, #12]
1236	add	r1, r3, #8
1237	ldrb	r4, [r6, r2]	@ zero_extendqisi2
1238	cmp	r9, r1
1239	ldrb	r0, [r0, r2]	@ zero_extendqisi2
1240	eor	r0, r0, r4
1241	strb	r0, [r5, r2]
1242	bls	.L1
1243	ldr	r0, [r7, #12]
1244	add	r2, r3, #9
1245	ldrb	r4, [r6, r1]	@ zero_extendqisi2
1246	cmp	r9, r2
1247	ldrb	r0, [r0, r1]	@ zero_extendqisi2
1248	eor	r0, r0, r4
1249	strb	r0, [r5, r1]
1250	bls	.L1
1251	ldr	r0, [r7, #12]
1252	add	r1, r3, #10
1253	ldrb	r4, [r6, r2]	@ zero_extendqisi2
1254	cmp	r9, r1
1255	ldrb	r0, [r0, r2]	@ zero_extendqisi2
1256	eor	r0, r0, r4
1257	strb	r0, [r5, r2]
1258	bls	.L1
1259	ldr	r0, [r7, #12]
1260	add	r2, r3, #11
1261	ldrb	r4, [r6, r1]	@ zero_extendqisi2
1262	cmp	r9, r2
1263	ldrb	r0, [r0, r1]	@ zero_extendqisi2
1264	eor	r0, r0, r4
1265	strb	r0, [r5, r1]
1266	bls	.L1
1267	ldr	r0, [r7, #12]
1268	add	r1, r3, #12
1269	ldrb	r4, [r6, r2]	@ zero_extendqisi2
1270	cmp	r9, r1
1271	ldrb	r0, [r0, r2]	@ zero_extendqisi2
1272	eor	r0, r0, r4
1273	strb	r0, [r5, r2]
1274	bls	.L1
1275	ldr	r0, [r7, #12]
1276	add	r2, r3, #13
1277	ldrb	r4, [r6, r1]	@ zero_extendqisi2
1278	cmp	r9, r2
1279	ldrb	r0, [r0, r1]	@ zero_extendqisi2
1280	eor	r0, r0, r4
1281	strb	r0, [r5, r1]
1282	bls	.L1
1283	ldr	r1, [r7, #12]
1284	adds	r3, r3, #14
1285	ldrb	r0, [r6, r2]	@ zero_extendqisi2
1286	cmp	r9, r3
1287	ldrb	r1, [r1, r2]	@ zero_extendqisi2
1288	eor	r1, r1, r0
1289	strb	r1, [r5, r2]
1290	bls	.L1
1291	ldr	r2, [r7, #84]
1292	ldrb	r1, [r2, r3]	@ zero_extendqisi2
1293	ldr	r2, [r7, #12]
1294	ldrb	r2, [r2, r3]	@ zero_extendqisi2
1295	eors	r2, r2, r1
1296	ldr	r1, [r7, #16]
1297	strb	r2, [r1, r3]
1298.L1:
1299	adds	r7, r7, #156
1300	mov	sp, r7
1301	@ sp needed
1302	vldm	sp!, {d8-d15}
1303	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
1304.L88:
1305	ldr	r5, [r7, #12]
1306	vadd.i32	q12, q12, q10
1307	ldr	r4, [r7, #80]
1308	cmp	r9, #31
1309	ldr	r0, [r5]	@ unaligned
1310	ldr	r1, [r5, #4]	@ unaligned
1311	mov	r6, r4
1312	ldr	r2, [r5, #8]	@ unaligned
1313	ldr	r3, [r5, #12]	@ unaligned
1314	stmia	r6!, {r0, r1, r2, r3}
1315	ldr	r2, [r7, #84]
1316	ldr	r6, [r7, #16]
1317	vldr	d18, [r2, #80]
1318	vldr	d19, [r2, #88]
1319	veor	q9, q9, q12
1320	vstr	d18, [r2, #80]
1321	vstr	d19, [r2, #88]
1322	ldmia	r4!, {r0, r1, r2, r3}
1323	str	r1, [r6, #4]	@ unaligned
1324	mov	r1, r6
1325	str	r0, [r6]	@ unaligned
1326	str	r2, [r6, #8]	@ unaligned
1327	str	r3, [r6, #12]	@ unaligned
1328	bhi	.L89
1329	vadd.i32	q13, q13, q15
1330	ldr	r3, [r7, #84]
1331	vstr	d26, [r3, #16]
1332	vstr	d27, [r3, #24]
1333	b	.L14
1334.L16:
1335	subs	r3, r2, #1
1336	ldr	r2, [r7, #12]
1337	add	r2, r2, r9
1338	mov	r5, r2
1339	ldr	r2, [r7, #84]
1340	add	r2, r2, r3
1341	mov	r3, r2
1342.L24:
1343	ldrb	r1, [r0], #1	@ zero_extendqisi2
1344	ldrb	r2, [r3, #1]!	@ zero_extendqisi2
1345	cmp	r0, r5
1346	eor	r2, r2, r1
1347	strb	r2, [r4], #1
1348	bne	.L24
1349	adds	r7, r7, #156
1350	mov	sp, r7
1351	@ sp needed
1352	vldm	sp!, {d8-d15}
1353	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
1354.L26:
1355	str	fp, [r7, #16]
1356	b	.L2
1357.L89:
1358	mov	r3, r5
1359	ldr	r4, [r7, #80]
1360	ldr	r0, [r3, #16]!	@ unaligned
1361	add	lr, r1, #16
1362	mov	r5, r1
1363	vadd.i32	q13, q13, q15
1364	mov	r6, r4
1365	cmp	r9, #47
1366	ldr	r1, [r3, #4]	@ unaligned
1367	ldr	r2, [r3, #8]	@ unaligned
1368	ldr	r3, [r3, #12]	@ unaligned
1369	stmia	r6!, {r0, r1, r2, r3}
1370	ldr	r2, [r7, #84]
1371	vldr	d18, [r2, #80]
1372	vldr	d19, [r2, #88]
1373	veor	q13, q9, q13
1374	vstr	d26, [r2, #80]
1375	vstr	d27, [r2, #88]
1376	ldmia	r4!, {r0, r1, r2, r3}
1377	str	r0, [r5, #16]	@ unaligned
1378	str	r1, [lr, #4]	@ unaligned
1379	str	r2, [lr, #8]	@ unaligned
1380	str	r3, [lr, #12]	@ unaligned
1381	bhi	.L90
1382	vadd.i32	q8, q14, q8
1383	ldr	r3, [r7, #84]
1384	vstr	d16, [r3, #32]
1385	vstr	d17, [r3, #40]
1386	b	.L14
1387.L90:
1388	ldr	r3, [r7, #12]
1389	add	lr, r5, #32
1390	ldr	r4, [r7, #80]
1391	vadd.i32	q8, q14, q8
1392	ldr	r5, [r7, #84]
1393	vadd.i32	q11, q11, q3
1394	ldr	r0, [r3, #32]!	@ unaligned
1395	mov	r6, r4
1396	vstr	d22, [r5, #48]
1397	vstr	d23, [r5, #56]
1398	ldr	r1, [r3, #4]	@ unaligned
1399	ldr	r2, [r3, #8]	@ unaligned
1400	ldr	r3, [r3, #12]	@ unaligned
1401	stmia	r4!, {r0, r1, r2, r3}
1402	vldr	d18, [r5, #80]
1403	vldr	d19, [r5, #88]
1404	veor	q9, q9, q8
1405	ldr	r4, [r7, #16]
1406	vstr	d18, [r5, #80]
1407	vstr	d19, [r5, #88]
1408	ldmia	r6!, {r0, r1, r2, r3}
1409	str	r0, [r4, #32]	@ unaligned
1410	str	r1, [lr, #4]	@ unaligned
1411	str	r2, [lr, #8]	@ unaligned
1412	str	r3, [lr, #12]	@ unaligned
1413	b	.L14
1414	.size	CRYPTO_chacha_20_neon, .-CRYPTO_chacha_20_neon
1415	.section	.rodata
1416	.align	2
1417.LANCHOR0 = . + 0
1418.LC0:
1419	.word	1634760805
1420	.word	857760878
1421	.word	2036477234
1422	.word	1797285236
1423	.ident	"GCC: (Linaro GCC 2014.11) 4.9.3 20141031 (prerelease)"
1424	.section	.note.GNU-stack,"",%progbits
1425
1426#endif  /* !OPENSSL_NO_ASM */
1427