1 // Copyright 2015, ARM Limited
2 // All rights reserved.
3 //
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are met:
6 //
7 // * Redistributions of source code must retain the above copyright notice,
8 // this list of conditions and the following disclaimer.
9 // * Redistributions in binary form must reproduce the above copyright notice,
10 // this list of conditions and the following disclaimer in the documentation
11 // and/or other materials provided with the distribution.
12 // * Neither the name of ARM Limited nor the names of its contributors may be
13 // used to endorse or promote products derived from this software without
14 // specific prior written permission.
15 //
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 #include "vixl/utils.h"
28 #include "vixl/a64/cpu-a64.h"
29
30 namespace vixl {
31
32 // Initialise to smallest possible cache size.
33 unsigned CPU::dcache_line_size_ = 1;
34 unsigned CPU::icache_line_size_ = 1;
35
36
37 // Currently computes I and D cache line size.
SetUp()38 void CPU::SetUp() {
39 uint32_t cache_type_register = GetCacheType();
40
41 // The cache type register holds information about the caches, including I
42 // D caches line size.
43 static const int kDCacheLineSizeShift = 16;
44 static const int kICacheLineSizeShift = 0;
45 static const uint32_t kDCacheLineSizeMask = 0xf << kDCacheLineSizeShift;
46 static const uint32_t kICacheLineSizeMask = 0xf << kICacheLineSizeShift;
47
48 // The cache type register holds the size of the I and D caches in words as
49 // a power of two.
50 uint32_t dcache_line_size_power_of_two =
51 (cache_type_register & kDCacheLineSizeMask) >> kDCacheLineSizeShift;
52 uint32_t icache_line_size_power_of_two =
53 (cache_type_register & kICacheLineSizeMask) >> kICacheLineSizeShift;
54
55 dcache_line_size_ = 4 << dcache_line_size_power_of_two;
56 icache_line_size_ = 4 << icache_line_size_power_of_two;
57 }
58
59
GetCacheType()60 uint32_t CPU::GetCacheType() {
61 #ifdef __aarch64__
62 uint64_t cache_type_register;
63 // Copy the content of the cache type register to a core register.
64 __asm__ __volatile__ ("mrs %[ctr], ctr_el0" // NOLINT
65 : [ctr] "=r" (cache_type_register));
66 VIXL_ASSERT(is_uint32(cache_type_register));
67 return cache_type_register;
68 #else
69 // This will lead to a cache with 1 byte long lines, which is fine since
70 // neither EnsureIAndDCacheCoherency nor the simulator will need this
71 // information.
72 return 0;
73 #endif
74 }
75
76
EnsureIAndDCacheCoherency(void * address,size_t length)77 void CPU::EnsureIAndDCacheCoherency(void *address, size_t length) {
78 #ifdef __aarch64__
79 // Implement the cache synchronisation for all targets where AArch64 is the
80 // host, even if we're building the simulator for an AAarch64 host. This
81 // allows for cases where the user wants to simulate code as well as run it
82 // natively.
83
84 if (length == 0) {
85 return;
86 }
87
88 // The code below assumes user space cache operations are allowed.
89
90 // Work out the line sizes for each cache, and use them to determine the
91 // start addresses.
92 uintptr_t start = reinterpret_cast<uintptr_t>(address);
93 uintptr_t dsize = static_cast<uintptr_t>(dcache_line_size_);
94 uintptr_t isize = static_cast<uintptr_t>(icache_line_size_);
95 uintptr_t dline = start & ~(dsize - 1);
96 uintptr_t iline = start & ~(isize - 1);
97
98 // Cache line sizes are always a power of 2.
99 VIXL_ASSERT(IsPowerOf2(dsize));
100 VIXL_ASSERT(IsPowerOf2(isize));
101 uintptr_t end = start + length;
102
103 do {
104 __asm__ __volatile__ (
105 // Clean each line of the D cache containing the target data.
106 //
107 // dc : Data Cache maintenance
108 // c : Clean
109 // va : by (Virtual) Address
110 // u : to the point of Unification
111 // The point of unification for a processor is the point by which the
112 // instruction and data caches are guaranteed to see the same copy of a
113 // memory location. See ARM DDI 0406B page B2-12 for more information.
114 " dc cvau, %[dline]\n"
115 :
116 : [dline] "r" (dline)
117 // This code does not write to memory, but the "memory" dependency
118 // prevents GCC from reordering the code.
119 : "memory");
120 dline += dsize;
121 } while (dline < end);
122
123 __asm__ __volatile__ (
124 // Make sure that the data cache operations (above) complete before the
125 // instruction cache operations (below).
126 //
127 // dsb : Data Synchronisation Barrier
128 // ish : Inner SHareable domain
129 //
130 // The point of unification for an Inner Shareable shareability domain is
131 // the point by which the instruction and data caches of all the processors
132 // in that Inner Shareable shareability domain are guaranteed to see the
133 // same copy of a memory location. See ARM DDI 0406B page B2-12 for more
134 // information.
135 " dsb ish\n"
136 : : : "memory");
137
138 do {
139 __asm__ __volatile__ (
140 // Invalidate each line of the I cache containing the target data.
141 //
142 // ic : Instruction Cache maintenance
143 // i : Invalidate
144 // va : by Address
145 // u : to the point of Unification
146 " ic ivau, %[iline]\n"
147 :
148 : [iline] "r" (iline)
149 : "memory");
150 iline += isize;
151 } while (iline < end);
152
153 __asm__ __volatile__ (
154 // Make sure that the instruction cache operations (above) take effect
155 // before the isb (below).
156 " dsb ish\n"
157
158 // Ensure that any instructions already in the pipeline are discarded and
159 // reloaded from the new data.
160 // isb : Instruction Synchronisation Barrier
161 " isb\n"
162 : : : "memory");
163 #else
164 // If the host isn't AArch64, we must be using the simulator, so this function
165 // doesn't have to do anything.
166 USE(address);
167 USE(length);
168 #endif
169 }
170
171 } // namespace vixl
172