Searched refs:AT (Results 1 – 7 of 7) sorted by relevance
| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 835 Auipc(AT, offset >> 16); in B()
836 Jic(AT, offset); in B()
843 Auipc(AT, prev >> 16); in B()
844 Jic(AT, prev); in B()
938 LoadConst32(AT, offset); in LoadFromOffset()
939 Daddu(AT, AT, base); in LoadFromOffset()
940 base = AT; in LoadFromOffset()
972 LoadConst32(AT, offset); in LoadFpuFromOffset()
973 Daddu(AT, AT, base); in LoadFpuFromOffset()
974 base = AT; in LoadFpuFromOffset()
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| D | assembler_mips64.h | 197 void Addiu32(GpuRegister rt, GpuRegister rs, int32_t value, GpuRegister rtmp = AT);
198 void Daddiu64(GpuRegister rt, GpuRegister rs, int64_t value, GpuRegister rtmp = AT); // MIPS64
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| /art/runtime/arch/mips/ |
| D | registers_mips.h | 31 AT = 1, // Assembler temporary. enumerator
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| /art/runtime/arch/mips64/ |
| D | registers_mips64.h | 31 AT = 1, // Assembler temporary. enumerator
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| /art/compiler/jni/quick/mips/ |
| D | calling_convention_mips.cc | 146 return MipsManagedRegister::FromCoreRegister(AT); in ReturnScratchRegister()
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| /art/compiler/jni/quick/mips64/ |
| D | calling_convention_mips64.cc | 147 return Mips64ManagedRegister::FromGpuRegister(AT); in ReturnScratchRegister()
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| /art/compiler/optimizing/ |
| D | code_generator_mips64.cc | 641 GpuRegister gpr = AT; in MoveLocation()
748 __ Dmfc1(AT, r1); in SwapLocations()
750 __ Dmtc1(AT, r2); in SwapLocations()
860 GpuRegister card = AT; in MarkGCCard()
884 blocked_core_registers_[AT] = true; in SetupBlockedRegisters()
973 __ LoadConst32(AT, mirror::Class::kStatusInitialized); in GenerateClassInitializationCheck()
974 __ Bltc(TMP, AT, slow_path->GetEntryLabel()); in GenerateClassInitializationCheck()
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