| /art/compiler/dex/quick/x86/ |
| D | fp_x86.cc | 172 AnnotateDalvikRegAccess(fild64, (src_v_reg_offset + LOWORD_OFFSET) >> 2, in GenLongToFP()
179 AnnotateDalvikRegAccess(fstp, displacement >> 2, false /* is_load */, is_double); in GenLongToFP()
408 AnnotateDalvikRegAccess(fld_2, (src2_v_reg_offset + LOWORD_OFFSET) >> 2, in GenRemFP()
413 AnnotateDalvikRegAccess(fld_1, (src1_v_reg_offset + LOWORD_OFFSET) >> 2, in GenRemFP()
441 AnnotateDalvikRegAccess(fst, displacement >> 2, false /* is_load */, is_double /* is64bit */); in GenRemFP()
654 AnnotateDalvikRegAccess(lir, displacement >> 2, false /*is_load */, false /* is_64bit */); in GenInlinedAbsFloat()
655 AnnotateDalvikRegAccess(lir, displacement >> 2, true /* is_load */, false /* is_64bit*/); in GenInlinedAbsFloat()
718 …AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, true /* is_load */, true /* is_6… in GenInlinedAbsDouble()
719 …AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, false /*is_load */, true /* is_6… in GenInlinedAbsDouble()
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| D | utility_x86.cc | 393 AnnotateDalvikRegAccess(l, offset >> 2, true /* is_load */, false /* is_64bit */); in OpRegMem()
420 AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is64Bit /* is_64bit */); in OpMemReg()
421 AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, is64Bit /* is_64bit */); in OpMemReg()
446 AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is64Bit /* is_64bit */); in OpRegMem()
717 AnnotateDalvikRegAccess(load, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2, in LoadBaseIndexedDisp()
720 AnnotateDalvikRegAccess(load2, (displacement + HIWORD_OFFSET) >> 2, in LoadBaseIndexedDisp()
882 AnnotateDalvikRegAccess(store, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2, in StoreBaseIndexedDisp()
885 AnnotateDalvikRegAccess(store2, (displacement + HIWORD_OFFSET) >> 2, in StoreBaseIndexedDisp()
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| D | int_x86.cc | 1189 AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false); in GenInlinedCas()
1196 AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false); in GenInlinedCas()
1655 AnnotateDalvikRegAccess(m, displacement >> 2, true /* is_load */, true /* is_64bit */); in GenImulMemImm()
1796 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, in GenMulLongConst()
1880 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, in GenMulLong()
1902 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, in GenMulLong()
1913 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, in GenMulLong()
1935 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, in GenMulLong()
1982 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, in GenLongRegOrMemOp()
1987 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, in GenLongRegOrMemOp()
[all …]
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| D | target_x86.cc | 910 AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2, in GenConstWide()
913 AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2, in GenConstWide()
1366 AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false); in GenInlinedIndexOf()
2232 AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, is_wide /* is_64bit */); in GenReduceVector()
2596 AnnotateDalvikRegAccess(ld1, current_src_offset >> 2, true, true); in GenDalvikArgsBulkCopy()
2597 AnnotateDalvikRegAccess(ld2, (current_src_offset + (bytes_to_move >> 1)) >> 2, true, in GenDalvikArgsBulkCopy()
2607 AnnotateDalvikRegAccess(st1, current_dest_offset >> 2, false, true); in GenDalvikArgsBulkCopy()
2608 AnnotateDalvikRegAccess(st2, (current_dest_offset + (bytes_to_move >> 1)) >> 2, false, in GenDalvikArgsBulkCopy()
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| /art/compiler/dex/quick/mips/ |
| D | utility_mips.cc | 772 AnnotateDalvikRegAccess(load, displacement >> 2, true /* is_load */, r_dest.Is64Bit()); in LoadBaseDispBody()
825 AnnotateDalvikRegAccess(load, (displacement + (is64bit ? LOWORD_OFFSET : 0)) >> 2, in LoadBaseDispBody()
828 AnnotateDalvikRegAccess(load2, (displacement + HIWORD_OFFSET) >> 2, in LoadBaseDispBody()
943 AnnotateDalvikRegAccess(store, displacement >> 2, false /* is_load */, r_src.Is64Bit()); in StoreBaseDispBody()
993 AnnotateDalvikRegAccess(store, (displacement + (is64bit ? LOWORD_OFFSET : 0)) >> 2, in StoreBaseDispBody()
996 AnnotateDalvikRegAccess(store2, (displacement + HIWORD_OFFSET) >> 2, in StoreBaseDispBody()
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| /art/compiler/dex/quick/arm64/ |
| D | utility_arm64.cc | 1267 AnnotateDalvikRegAccess(load, displacement >> 2, true /* is_load */, r_dest.Is64Bit()); in LoadBaseDispBody()
1357 AnnotateDalvikRegAccess(store, displacement >> 2, false /* is_load */, r_src.Is64Bit()); in StoreBaseDispBody()
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| /art/compiler/dex/quick/arm/ |
| D | utility_arm.cc | 1025 AnnotateDalvikRegAccess(load, displacement >> 2, true /* is_load */, r_dest.Is64Bit()); in LoadBaseDispBody()
1167 AnnotateDalvikRegAccess(store, displacement >> 2, false /* is_load */, r_src.Is64Bit()); in StoreBaseDispBody()
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| /art/compiler/dex/quick/ |
| D | codegen_util.cc | 181 void Mir2Lir::AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, in AnnotateDalvikRegAccess() function in art::Mir2Lir
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| D | mir_to_lir.h | 645 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit);
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