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Searched refs:Condition (Results 1 – 25 of 25) sorted by relevance

/art/compiler/utils/arm/
Dassembler_arm32.h42 void and_(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
44 void eor(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
46 void sub(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
47 void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
49 void rsb(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
50 void rsbs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
52 void add(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
54 void adds(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
56 void adc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
58 void sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
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Dassembler_thumb2.h64 void and_(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
66 void eor(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
68 void sub(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
69 void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
71 void rsb(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
72 void rsbs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
74 void add(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
76 void adds(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
78 void adc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
80 void sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
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Dassembler_arm.h351 virtual void and_(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
353 virtual void eor(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
355 virtual void sub(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
356 virtual void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
358 virtual void rsb(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
359 virtual void rsbs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
361 virtual void add(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
363 virtual void adds(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
365 virtual void adc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
367 virtual void sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
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Dassembler_arm32.cc60 Condition cond) { in and_()
66 Condition cond) { in eor()
72 Condition cond) { in sub()
77 Condition cond) { in rsb()
82 Condition cond) { in rsbs()
88 Condition cond) { in add()
94 Condition cond) { in adds()
100 Condition cond) { in subs()
106 Condition cond) { in adc()
112 Condition cond) { in sbc()
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Dassembler_thumb2.cc55 Condition cond) { in and_()
61 Condition cond) { in eor()
67 Condition cond) { in sub()
73 Condition cond) { in rsb()
79 Condition cond) { in rsbs()
85 Condition cond) { in add()
91 Condition cond) { in adds()
97 Condition cond) { in subs()
103 Condition cond) { in adc()
109 Condition cond) { in sbc()
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Dassembler_arm32_test.cc45 uint32_t, arm::ShifterOperand, arm::Condition> {
103 conditions_.push_back(arm::Condition::EQ); in SetUpHelpers()
104 conditions_.push_back(arm::Condition::NE); in SetUpHelpers()
105 conditions_.push_back(arm::Condition::CS); in SetUpHelpers()
106 conditions_.push_back(arm::Condition::CC); in SetUpHelpers()
107 conditions_.push_back(arm::Condition::MI); in SetUpHelpers()
108 conditions_.push_back(arm::Condition::PL); in SetUpHelpers()
109 conditions_.push_back(arm::Condition::VS); in SetUpHelpers()
110 conditions_.push_back(arm::Condition::VC); in SetUpHelpers()
111 conditions_.push_back(arm::Condition::HI); in SetUpHelpers()
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Dconstants_arm.h101 enum Condition { // private marker to avoid generate-operator-out.py from processing. enum
121 std::ostream& operator<<(std::ostream& os, const Condition& rhs);
265 Condition ConditionField() const { in ConditionField()
266 return static_cast<Condition>(Bits(kConditionShift, kConditionBits)); in ConditionField()
Dassembler_arm.cc67 std::ostream& operator<<(std::ostream& os, const Condition& rhs) { in operator <<()
/art/compiler/utils/x86/
Dconstants_x86.h78 enum Condition { enum
Dassembler_x86.h254 void cmovl(Condition condition, Register dst, Register src);
256 void setb(Condition condition, Register dst);
461 void j(Condition condition, Label* label);
Dassembler_x86.cc270 void X86Assembler::cmovl(Condition condition, Register dst, Register src) { in cmovl()
278 void X86Assembler::setb(Condition condition, Register dst) { in setb()
1454 void X86Assembler::j(Condition condition, Label* label) { in j()
/art/compiler/utils/arm64/
Dassembler_arm64.h222 void LoadImmediate(XRegister dest, int32_t value, vixl::Condition cond = vixl::al);
229 void AddConstant(XRegister rd, int32_t value, vixl::Condition cond = vixl::al);
230 void AddConstant(XRegister rd, XRegister rn, int32_t value, vixl::Condition cond = vixl::al);
Dassembler_arm64.cc75 void Arm64Assembler::AddConstant(XRegister rd, int32_t value, Condition cond) { in AddConstant()
80 Condition cond) { in AddConstant()
200 Condition cond) { in LoadImmediate()
/art/compiler/utils/x86_64/
Dconstants_x86_64.h87 enum Condition { enum
Dassembler_x86_64.h336 void cmov(Condition c, CpuRegister dst, CpuRegister src); // This is the 64b version.
337 void cmov(Condition c, CpuRegister dst, CpuRegister src, bool is64bit);
586 void j(Condition condition, Label* label);
600 void setcc(Condition condition, CpuRegister dst);
Dassembler_x86_64.cc198 void X86_64Assembler::cmov(Condition c, CpuRegister dst, CpuRegister src) { in cmov()
202 void X86_64Assembler::cmov(Condition c, CpuRegister dst, CpuRegister src, bool is64bit) { in cmov()
1931 void X86_64Assembler::j(Condition condition, Label* label) { in j()
2042 void X86_64Assembler::setcc(Condition condition, CpuRegister dst) { in setcc()
Dassembler_x86_64_test.cc1078 assembler->setcc(static_cast<x86_64::Condition>(i), *reg); in setcc_test_fn()
/art/compiler/optimizing/
Dintrinsics_x86.cc514 __ j(Condition::kParityEven, &nan); in GenMinMaxFP()
516 __ j(is_min ? Condition::kAbove : Condition::kBelow, &op2_label); in GenMinMaxFP()
517 __ j(is_min ? Condition::kBelow : Condition::kAbove, &done); in GenMinMaxFP()
640 Condition cond = is_min ? Condition::kGreaterEqual : Condition::kLess; in GenMinMax()
654 Condition cond = is_min ? Condition::kGreater : Condition::kLess; in GenMinMax()
Dintrinsics_arm.cc319 __ it((is_min) ? Condition::LT : Condition::GT, kItElse); in GenMinMax()
320 __ mov(out, ShifterOperand(op1), is_min ? Condition::LT : Condition::GT); in GenMinMax()
321 __ mov(out, ShifterOperand(op2), is_min ? Condition::GE : Condition::LE); in GenMinMax()
Dintrinsics_x86_64.cc430 __ j(Condition::kParityEven, &nan); in GenMinMaxFP()
432 __ j(is_min ? Condition::kAbove : Condition::kBelow, &op2_label); in GenMinMaxFP()
433 __ j(is_min ? Condition::kBelow : Condition::kAbove, &done); in GenMinMaxFP()
544 __ cmov(is_min ? Condition::kGreater : Condition::kLess, out, op2, is_long); in GenMinMax()
Dnodes.h817 M(Condition, BinaryOperation) \
822 M(Equal, Condition) \
826 M(GreaterThan, Condition) \
827 M(GreaterThanOrEqual, Condition) \
836 M(LessThan, Condition) \
837 M(LessThanOrEqual, Condition) \
851 M(NotEqual, Condition) \
1950 DECLARE_INSTRUCTION(Condition);
Dcode_generator_arm64.cc70 inline Condition ARM64Condition(IfCondition cond) { in ARM64Condition()
1587 Condition cond = ARM64Condition(instruction->GetCondition()); in VisitCondition()
1764 Condition arm64_cond = ARM64Condition(condition->GetCondition()); in GenerateTestAndBranch()
Dcode_generator_arm.cc321 inline Condition ARMCondition(IfCondition cond) { in ARMCondition()
335 inline Condition ARMOppositeCondition(IfCondition cond) { in ARMOppositeCondition()
Dcode_generator_x86.cc328 inline Condition X86Condition(IfCondition cond) { in X86Condition()
Dcode_generator_x86_64.cc348 inline Condition X86_64Condition(IfCondition cond) { in X86_64Condition()