| /art/compiler/dex/quick/arm64/ |
| D | utility_arm64.cc | 96 const A64EncodingMap *encoder = &EncodingMap[opcode]; in GetLoadStoreSize()
616 if (EncodingMap[opcode].flags & IS_BINARY_OP) { in OpRegRegShift()
619 } else if (EncodingMap[opcode].flags & IS_TERTIARY_OP) { in OpRegRegShift()
620 A64EncodingKind kind = EncodingMap[opcode].field_loc[2].kind; in OpRegRegShift()
652 if (EncodingMap[opcode].flags & IS_TERTIARY_OP) { in OpRegRegExtend()
653 A64EncodingKind kind = EncodingMap[opcode].field_loc[2].kind; in OpRegRegExtend()
753 if (EncodingMap[opcode].flags & IS_QUAD_OP) { in OpRegRegRegShift()
757 DCHECK(EncodingMap[opcode].flags & IS_TERTIARY_OP); in OpRegRegRegShift()
927 if (EncodingMap[alt_opcode].flags & IS_QUAD_OP) in OpRegRegImm64()
1001 if (EncodingMap[opcode].flags & IS_QUAD_OP) in OpRegImm64()
[all …]
|
| D | assemble_arm64.cc | 111 const A64EncodingMap Arm64Mir2Lir::EncodingMap[kA64Last] = { member in art::Arm64Mir2Lir
700 const A64EncodingMap *encoder = &EncodingMap[opcode]; in EncodeLIRs()
980 lir->flags.fixup = EncodingMap[kA64Tst2rl].fixup; in AssembleLIR()
981 lir->flags.size = EncodingMap[kA64Tst2rl].size; in AssembleLIR()
991 new_lir->flags.fixup = EncodingMap[kA64B2ct].fixup; in AssembleLIR()
992 new_lir->flags.size = EncodingMap[kA64B2ct].size; in AssembleLIR()
1036 uint64_t prev_insn_flags = EncodingMap[UNWIDE(prev_insn->opcode)].flags; in AssembleLIR()
1043 new_lir->flags.size = EncodingMap[kA64Nop0].size; in AssembleLIR()
1104 return EncodingMap[opcode].size; in GetInsnSize()
1117 lir->flags.size = EncodingMap[opcode].size; in LinkFixupInsns()
[all …]
|
| D | target_arm64.cc | 612 DCHECK_EQ(UNWIDE(Arm64Mir2Lir::EncodingMap[i].opcode), i) in Arm64Mir2Lir()
613 << "Encoding order for " << Arm64Mir2Lir::EncodingMap[i].name in Arm64Mir2Lir()
615 << static_cast<int>(Arm64Mir2Lir::EncodingMap[i].opcode); in Arm64Mir2Lir()
801 return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].flags; in GetTargetInstFlags()
806 return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].name; in GetTargetInstName()
811 return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].fmt; in GetTargetInstFmt()
|
| D | codegen_arm64.h | 406 static const A64EncodingMap EncodingMap[kA64Last]; variable
|
| /art/compiler/dex/quick/arm/ |
| D | assemble_arm.cc | 82 const ArmEncodingMap ArmMir2Lir::EncodingMap[kArmLast] = { member in art::ArmMir2Lir
1101 const ArmEncodingMap *encoder = &EncodingMap[lir->opcode]; in EncodeLIRs()
1327 new_adr->flags.size = EncodingMap[kThumb2Adr].size; in AssembleLIR()
1342 lir->flags.size = EncodingMap[lir->opcode].size; in AssembleLIR()
1392 lir->flags.size = EncodingMap[lir->opcode].size; in AssembleLIR()
1398 new_inst->flags.size = EncodingMap[new_inst->opcode].size; in AssembleLIR()
1423 lir->flags.size = EncodingMap[lir->opcode].size; in AssembleLIR()
1459 lir->flags.size = EncodingMap[lir->opcode].size; in AssembleLIR()
1521 new_mov16L->flags.size = EncodingMap[new_mov16L->opcode].size; in AssembleLIR()
1533 new_mov16H->flags.size = EncodingMap[new_mov16H->opcode].size; in AssembleLIR()
[all …]
|
| D | target_arm.cc | 584 DCHECK_EQ(ArmMir2Lir::EncodingMap[i].opcode, i) in ArmMir2Lir()
585 << "Encoding order for " << ArmMir2Lir::EncodingMap[i].name in ArmMir2Lir()
587 << static_cast<int>(ArmMir2Lir::EncodingMap[i].opcode); in ArmMir2Lir()
817 return ArmMir2Lir::EncodingMap[opcode].flags; in GetTargetInstFlags()
822 return ArmMir2Lir::EncodingMap[opcode].name; in GetTargetInstName()
827 return ArmMir2Lir::EncodingMap[opcode].fmt; in GetTargetInstFmt()
|
| D | utility_arm.cc | 402 if (EncodingMap[opcode].flags & IS_BINARY_OP) { in OpRegRegShift()
404 } else if (EncodingMap[opcode].flags & IS_TERTIARY_OP) { in OpRegRegShift()
405 if (EncodingMap[opcode].field_loc[2].kind == kFmtShift) { in OpRegRegShift()
410 } else if (EncodingMap[opcode].flags & IS_QUAD_OP) { in OpRegRegShift()
501 if (EncodingMap[opcode].flags & IS_QUAD_OP) { in OpRegRegRegShift()
504 DCHECK(EncodingMap[opcode].flags & IS_TERTIARY_OP); in OpRegRegRegShift()
646 if (EncodingMap[alt_opcode].flags & IS_QUAD_OP) in OpRegRegImm()
|
| D | codegen_arm.h | 228 static const ArmEncodingMap EncodingMap[kArmLast]; variable
|
| /art/compiler/dex/quick/mips/ |
| D | target_mips.cc | 908 DCHECK_EQ(MipsMir2Lir::EncodingMap[i].opcode, i) in MipsMir2Lir()
909 << "Encoding order for " << MipsMir2Lir::EncodingMap[i].name in MipsMir2Lir()
911 << static_cast<int>(MipsMir2Lir::EncodingMap[i].opcode); in MipsMir2Lir()
922 return MipsMir2Lir::EncodingMap[opcode].flags; in GetTargetInstFlags()
927 return MipsMir2Lir::EncodingMap[opcode].name; in GetTargetInstName()
932 return MipsMir2Lir::EncodingMap[opcode].fmt; in GetTargetInstFmt()
|
| D | assemble_mips.cc | 87 const MipsEncodingMap MipsMir2Lir::EncodingMap[kMipsLast] = { member in art::MipsMir2Lir
791 const MipsEncodingMap *encoder = &EncodingMap[lir->opcode]; in AssembleInstructions()
844 const MipsEncodingMap *encoder2 = &EncodingMap[kMipsNop]; in AssembleInstructions()
857 return EncodingMap[lir->opcode].size; in GetInsnSize()
|
| D | codegen_mips.h | 226 static const MipsEncodingMap EncodingMap[kMipsLast]; variable
|
| D | mips_lir.h | 712 extern MipsEncodingMap EncodingMap[kMipsLast];
|
| /art/compiler/dex/quick/x86/ |
| D | target_x86.cc | 851 DCHECK_EQ(X86Mir2Lir::EncodingMap[i].opcode, i) in X86Mir2Lir()
852 << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name in X86Mir2Lir()
854 << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode); in X86Mir2Lir()
885 return X86Mir2Lir::EncodingMap[opcode].flags; in GetTargetInstFlags()
890 return X86Mir2Lir::EncodingMap[opcode].name; in GetTargetInstName()
895 return X86Mir2Lir::EncodingMap[opcode].fmt; in GetTargetInstFmt()
|
| D | assemble_x86.cc | 31 const X86EncodingMap X86Mir2Lir::EncodingMap[kX86Last] = { member in art::X86Mir2Lir
555 os << X86Mir2Lir::EncodingMap[rhs].name; in operator <<()
711 const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode]; in GetInsnSize()
1770 …EQ(lir->opcode, kX86Lea64RM) << "Unknown instruction: " << X86Mir2Lir::EncodingMap[lir->opcode].na… in AssembleInstructions()
1792 const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode]; in AssembleInstructions()
1944 << "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name; in AssembleInstructions()
|
| D | x86_lir.h | 733 extern X86EncodingMap EncodingMap[kX86Last];
|
| D | codegen_x86.h | 973 static const X86EncodingMap EncodingMap[kX86Last]; variable
|
| D | utility_x86.cc | 52 DCHECK_NE((EncodingMap[opcode].flags & IS_BINARY_OP), 0ULL); in OpFpRegCopy()
|