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Searched refs:IS_TERTIARY_OP (Results 1 – 8 of 8) sorted by relevance

/art/compiler/dex/quick/mips/
Dassemble_mips.cc95 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
99 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
103 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
107 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
155 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
159 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
163 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
167 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
171 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
175 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
[all …]
/art/compiler/dex/quick/arm/
Dassemble_arm.cc94 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES,
104 IS_TERTIARY_OP | REG_DEF0_USE12 | SETS_CCODES,
120 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | REG_USE_PC | NEEDS_FIXUP,
124 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | REG_USE_SP,
138 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES,
223 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD_OFF4,
227 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
231 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | REG_USE_PC
235 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | REG_USE_SP
239 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD_OFF,
[all …]
Dutility_arm.cc404 } else if (EncodingMap[opcode].flags & IS_TERTIARY_OP) { in OpRegRegShift()
504 DCHECK(EncodingMap[opcode].flags & IS_TERTIARY_OP); in OpRegRegRegShift()
1260 size_t offset = (check_flags & IS_TERTIARY_OP) ? lir->operands[2] : 0; in GetInstructionOffset()
/art/compiler/dex/quick/arm64/
Dassemble_arm64.cc114 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | USES_CCODES,
132 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | NEEDS_FIXUP,
140 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
148 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
152 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
191 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | SETS_CCODES,
195 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | SETS_CCODES,
199 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE0 | SETS_CCODES,
203 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | SETS_CCODES,
207 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | SETS_CCODES,
[all …]
Dutility_arm64.cc106 DCHECK(check_flags & IS_TERTIARY_OP); in GetInstructionOffset()
619 } else if (EncodingMap[opcode].flags & IS_TERTIARY_OP) { in OpRegRegShift()
652 if (EncodingMap[opcode].flags & IS_TERTIARY_OP) { in OpRegRegExtend()
757 DCHECK(EncodingMap[opcode].flags & IS_TERTIARY_OP); in OpRegRegRegShift()
1097 DCHECK_NE(EncodingMap[UNWIDE(opcode)].flags & IS_TERTIARY_OP, 0U); in LoadBaseIndexed()
1175 DCHECK_NE(EncodingMap[UNWIDE(opcode)].flags & IS_TERTIARY_OP, 0U); in StoreBaseIndexed()
/art/compiler/dex/quick/x86/
Dassemble_x86.cc43 { kX86 ## opname ## 8MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES …
47 { kX86 ## opname ## 8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES …
51 { kX86 ## opname ## 8MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES …
55 { kX86 ## opname ## 16MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODE…
59 { kX86 ## opname ## 16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODE…
63 { kX86 ## opname ## 16MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODE…
67 { kX86 ## opname ## 16MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODE…
71 { kX86 ## opname ## 32MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODE…
75 { kX86 ## opname ## 32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODE…
79 { kX86 ## opname ## 32MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODE…
[all …]
/art/compiler/dex/quick/
Dmir_to_lir-inl.h112 DCHECK(IsPseudoLirOp(opcode) || (GetTargetInstFlags(opcode) & IS_TERTIARY_OP)) in NewLIR3()
Dmir_to_lir.h54 #define IS_TERTIARY_OP (1ULL << kIsTertiaryOp) macro