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Searched refs:LOWORD_OFFSET (Results 1 – 7 of 7) sorted by relevance

/art/compiler/dex/quick/x86/
Dutility_x86.cc702 load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), displacement + LOWORD_OFFSET); in LoadBaseIndexedDisp()
708 load2 = NewLIR3(opcode, r_dest.GetLowReg(), r_base.GetReg(), displacement + LOWORD_OFFSET); in LoadBaseIndexedDisp()
710 load = NewLIR3(opcode, r_dest.GetLowReg(), r_base.GetReg(), displacement + LOWORD_OFFSET); in LoadBaseIndexedDisp()
717 AnnotateDalvikRegAccess(load, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2, in LoadBaseIndexedDisp()
727 displacement + LOWORD_OFFSET); in LoadBaseIndexedDisp()
737 displacement + LOWORD_OFFSET); in LoadBaseIndexedDisp()
744 displacement + LOWORD_OFFSET); in LoadBaseIndexedDisp()
751 displacement + LOWORD_OFFSET); in LoadBaseIndexedDisp()
758 displacement + LOWORD_OFFSET); in LoadBaseIndexedDisp()
874 store = NewLIR3(opcode, r_base.GetReg(), displacement + LOWORD_OFFSET, r_src.GetReg()); in StoreBaseIndexedDisp()
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Dfp_x86.cc171 src_v_reg_offset + LOWORD_OFFSET); in GenLongToFP()
172 AnnotateDalvikRegAccess(fild64, (src_v_reg_offset + LOWORD_OFFSET) >> 2, in GenLongToFP()
177 int displacement = is_double ? dest_v_reg_offset + LOWORD_OFFSET : dest_v_reg_offset; in GenLongToFP()
407 src2_v_reg_offset + LOWORD_OFFSET); in GenRemFP()
408 AnnotateDalvikRegAccess(fld_2, (src2_v_reg_offset + LOWORD_OFFSET) >> 2, in GenRemFP()
412 src1_v_reg_offset + LOWORD_OFFSET); in GenRemFP()
413 AnnotateDalvikRegAccess(fld_1, (src1_v_reg_offset + LOWORD_OFFSET) >> 2, in GenRemFP()
438 int displacement = dest_v_reg_offset + LOWORD_OFFSET; in GenRemFP()
Dint_x86.cc1782 GenImulMemImm(rs_r0, rl_src1.s_reg_low, displacement + LOWORD_OFFSET, val_hi); in GenMulLongConst()
1795 LIR *m = NewLIR2(kX86Mul32DaM, rs_rX86_SP_32.GetReg(), displacement + LOWORD_OFFSET); in GenMulLongConst()
1796 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, in GenMulLongConst()
1879 displacement + LOWORD_OFFSET); in GenMulLong()
1880 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, in GenMulLong()
1901 displacement + LOWORD_OFFSET); in GenMulLong()
1902 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, in GenMulLong()
1912 displacement + LOWORD_OFFSET); in GenMulLong()
1913 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, in GenMulLong()
1925 LoadBaseDisp(rs_rSP, SRegOffset(rl_src2.s_reg_low) + LOWORD_OFFSET, rs_r0, k32, in GenMulLong()
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Dx86_lir.h707 #define LOWORD_OFFSET 0 macro
Dtarget_x86.cc909 LIR * store = NewLIR3(kX86Mov32MI, r_base, displacement + LOWORD_OFFSET, val_lo); in GenConstWide()
910 AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2, in GenConstWide()
/art/compiler/dex/quick/mips/
Dutility_mips.cc783 load = res = NewLIR3(opcode, r_dest.GetLowReg(), displacement + LOWORD_OFFSET, in LoadBaseDispBody()
791 load = res = NewLIR3(kMipsFlwc1, r_dest.GetReg(), displacement + LOWORD_OFFSET, in LoadBaseDispBody()
810 load = NewLIR3(opcode, r_dest.GetLowReg(), LOWORD_OFFSET, r_tmp.GetReg()); in LoadBaseDispBody()
815 load = res = NewLIR3(kMipsFlwc1, r_dest.GetReg(), LOWORD_OFFSET, r_tmp.GetReg()); in LoadBaseDispBody()
825 AnnotateDalvikRegAccess(load, (displacement + (is64bit ? LOWORD_OFFSET : 0)) >> 2, in LoadBaseDispBody()
842 LIR* load = Load32Disp(reg, LOWORD_OFFSET, rs_rZERO); in ForceImplicitNullCheck()
954 store = res = NewLIR3(opcode, r_src.GetLowReg(), displacement + LOWORD_OFFSET, in StoreBaseDispBody()
961 store = res = NewLIR3(kMipsFswc1, r_src.GetReg(), displacement + LOWORD_OFFSET, in StoreBaseDispBody()
976 store = NewLIR3(opcode, r_src.GetLowReg(), LOWORD_OFFSET, r_scratch.GetReg()); in StoreBaseDispBody()
982 store = NewLIR3(kMipsFswc1, r_src.GetReg(), LOWORD_OFFSET, r_scratch.GetReg()); in StoreBaseDispBody()
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Dmips_lir.h104 #define LOWORD_OFFSET 0 macro