| /art/compiler/optimizing/ |
| D | code_generator_arm.cc | 182 __ LoadImmediate(calling_convention.GetRegisterAt(0), cls_->GetTypeIndex()); in EmitNativeCode() local
228 __ LoadImmediate(calling_convention.GetRegisterAt(0), instruction_->GetStringIndex()); in EmitNativeCode() local
814 __ LoadImmediate(location.AsRegister<Register>(), value); in Move() local
817 __ LoadImmediate(IP, value); in Move() local
824 __ LoadImmediate(location.AsRegisterPairLow<Register>(), Low32Bits(value)); in Move() local
825 __ LoadImmediate(location.AsRegisterPairHigh<Register>(), High32Bits(value)); in Move() local
828 __ LoadImmediate(IP, Low32Bits(value)); in Move() local
830 __ LoadImmediate(IP, High32Bits(value)); in Move() local
976 __ LoadImmediate(temp, value); in GenerateTestAndBranch() local
1055 __ LoadImmediate(temp, value); in VisitCondition() local
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| D | intrinsics_arm.cc | 880 __ LoadImmediate(tmp_reg, std::numeric_limits<uint16_t>::max()); in GenerateVisitStringIndexOf() local
890 __ LoadImmediate(tmp_reg, 0); in GenerateVisitStringIndexOf() local
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| /art/compiler/utils/arm64/ |
| D | assembler_arm64.cc | 160 LoadImmediate(scratch.AsXRegister(), imm); in StoreImmediateToFrame()
169 LoadImmediate(scratch.AsXRegister(), imm); in StoreImmediateToThread64()
199 void Arm64Assembler::LoadImmediate(XRegister dest, int32_t value, in LoadImmediate() function in art::arm64::Arm64Assembler
566 LoadImmediate(out_reg.AsXRegister(), 0, eq); in CreateHandleScopeEntry()
602 LoadImmediate(out_reg.AsXRegister(), 0, eq); in LoadReferenceFromHandleScope()
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| D | assembler_arm64.h | 222 void LoadImmediate(XRegister dest, int32_t value, vixl::Condition cond = vixl::al);
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| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 454 void MipsAssembler::LoadImmediate(Register rt, int32_t value) { in LoadImmediate() function in art::mips::MipsAssembler
650 LoadImmediate(scratch.AsCoreRegister(), imm); in StoreImmediateToFrame()
658 LoadImmediate(scratch.AsCoreRegister(), imm); in StoreImmediateToThread32()
864 LoadImmediate(out_reg.AsCoreRegister(), 0); in CreateHandleScopeEntry()
905 LoadImmediate(out_reg.AsCoreRegister(), 0); in LoadReferenceFromHandleScope()
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| D | assembler_mips.h | 137 void LoadImmediate(Register rt, int32_t value);
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| /art/compiler/utils/arm/ |
| D | assembler_arm.cc | 560 LoadImmediate(scratch.AsCoreRegister(), imm); in StoreImmediateToFrame()
568 LoadImmediate(scratch.AsCoreRegister(), imm); in StoreImmediateToThread32()
747 LoadImmediate(out_reg.AsCoreRegister(), 0, EQ); in CreateHandleScopeEntry()
786 LoadImmediate(out_reg.AsCoreRegister(), 0, EQ); // TODO: why EQ? in LoadReferenceFromHandleScope()
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| D | assembler_arm32.cc | 1417 void Arm32Assembler::LoadImmediate(Register rd, int32_t value, Condition cond) { in LoadImmediate() function in art::arm::Arm32Assembler
1442 LoadImmediate(IP, offset, cond); in LoadFromOffset()
1482 LoadImmediate(IP, offset, cond); in LoadSFromOffset()
1500 LoadImmediate(IP, offset, cond); in LoadDFromOffset()
1520 LoadImmediate(IP, offset, cond); in StoreToOffset()
1554 LoadImmediate(IP, offset, cond); in StoreSToOffset()
1572 LoadImmediate(IP, offset, cond); in StoreDToOffset()
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| D | assembler_thumb2.cc | 2523 void Thumb2Assembler::LoadImmediate(Register rd, int32_t value, Condition cond) { in LoadImmediate() function in art::arm::Thumb2Assembler
2548 LoadImmediate(IP, offset, cond); in LoadFromOffset()
2588 LoadImmediate(IP, offset, cond); in LoadSFromOffset()
2606 LoadImmediate(IP, offset, cond); in LoadDFromOffset()
2642 LoadImmediate(tmp_reg, offset, cond); in StoreToOffset()
2680 LoadImmediate(IP, offset, cond); in StoreSToOffset()
2698 LoadImmediate(IP, offset, cond); in StoreDToOffset()
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| D | assembler_arm.h | 540 virtual void LoadImmediate(Register rd, int32_t value, Condition cond = AL) = 0;
551 LoadImmediate(IP, int_value, cond);
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| D | assembler_arm32.h | 248 void LoadImmediate(Register rd, int32_t value, Condition cond = AL) OVERRIDE;
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| D | assembler_thumb2.h | 287 void LoadImmediate(Register rd, int32_t value, Condition cond = AL) OVERRIDE;
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