Searched refs:OpDecAndBranch (Results 1 – 10 of 10) sorted by relevance
| /art/compiler/dex/quick/mips/ |
| D | codegen_mips.h | 199 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
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| D | int_mips.cc | 460 LIR* MipsMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { in OpDecAndBranch() function in art::MipsMir2Lir
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| /art/compiler/dex/quick/arm/ |
| D | codegen_arm.h | 201 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
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| D | int_arm.cc | 1182 LIR* ArmMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { in OpDecAndBranch() function in art::ArmMir2Lir
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| /art/compiler/dex/quick/arm64/ |
| D | codegen_arm64.h | 205 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE;
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| D | int_arm64.cc | 1025 LIR* Arm64Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { in OpDecAndBranch() function in art::Arm64Mir2Lir
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| /art/compiler/dex/quick/x86/ |
| D | codegen_x86.h | 298 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE;
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| D | int_x86.cc | 1593 LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { in OpDecAndBranch() function in art::X86Mir2Lir
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| /art/compiler/dex/quick/ |
| D | mir_to_lir.h | 1410 virtual LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) = 0;
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| D | gen_common.cc | 620 OpDecAndBranch(kCondGe, r_idx, loop_head_target); in GenFilledNewArray()
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