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Searched refs:OpKind (Results 1 – 15 of 15) sorted by relevance

/art/compiler/dex/quick/arm64/
Dcodegen_arm64.h209 LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE;
211 LIR* OpReg(OpKind op, RegStorage r_dest_src) OVERRIDE;
214 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) OVERRIDE;
215 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) OVERRIDE;
218 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE;
219 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) OVERRIDE;
220 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) OVERRIDE;
265 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE;
367 void GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
369 LIR* OpRegImm64(OpKind op, RegStorage r_dest_src1, int64_t value);
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Dutility_arm64.cc552 LIR* Arm64Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { in OpReg()
564 LIR* Arm64Mir2Lir::OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift) { in OpRegRegShift()
630 LIR* Arm64Mir2Lir::OpRegRegExtend(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, in OpRegRegExtend()
664 LIR* Arm64Mir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) { in OpRegReg()
689 LIR* Arm64Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { in OpCondRegReg()
695 LIR* Arm64Mir2Lir::OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, in OpRegRegRegShift()
763 LIR* Arm64Mir2Lir::OpRegRegRegExtend(OpKind op, RegStorage r_dest, RegStorage r_src1, in OpRegRegRegExtend()
801 LIR* Arm64Mir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) { in OpRegRegReg()
805 LIR* Arm64Mir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) { in OpRegRegImm()
809 LIR* Arm64Mir2Lir::OpRegRegImm64(OpKind op, RegStorage r_dest, RegStorage r_src1, int64_t value) { in OpRegRegImm64()
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Dint_arm64.cc73 OpKind op = kOpBkpt; in GenShiftOpLong()
1105 void Arm64Mir2Lir::GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1, in GenLongOp()
1345 OpKind op = kOpBkpt; in GenShiftImmOpLong()
1377 OpKind op = kOpBkpt; in GenArithImmOpLong()
/art/compiler/dex/quick/arm/
Dcodegen_arm.h206 LIR* OpMem(OpKind op, RegStorage r_base, int disp);
208 LIR* OpReg(OpKind op, RegStorage r_dest_src);
211 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value);
212 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2);
215 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
216 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
217 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
225 LIR* OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2,
227 LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift);
272 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE;
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Dutility_arm.cc270 LIR* ArmMir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { in OpReg()
285 LIR* ArmMir2Lir::OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, in OpRegRegShift()
418 LIR* ArmMir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) { in OpRegReg()
434 LIR* ArmMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { in OpCondRegReg()
440 LIR* ArmMir2Lir::OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, in OpRegRegRegShift()
509 LIR* ArmMir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) { in OpRegRegReg()
513 LIR* ArmMir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) { in OpRegRegImm()
656 LIR* ArmMir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) { in OpRegImm()
1246 LIR* ArmMir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) { in OpMem()
1252 LIR* ArmMir2Lir::InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) { in InvokeTrampoline()
/art/compiler/dex/quick/mips/
Dcodegen_mips.h203 LIR* OpMem(OpKind op, RegStorage r_base, int disp);
205 LIR* OpReg(OpKind op, RegStorage r_dest_src);
208 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value);
209 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2);
212 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
213 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
214 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
239 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE;
276 void GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
Dutility_mips.cc280 LIR* MipsMir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { in OpReg()
295 LIR* MipsMir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) { in OpRegImm()
304 LIR* MipsMir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) { in OpRegRegReg()
346 LIR* MipsMir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) { in OpRegRegImm()
466 LIR* MipsMir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) { in OpRegReg()
536 LIR* MipsMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { in OpCondRegReg()
1034 LIR* MipsMir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) { in OpMem()
1046 LIR* MipsMir2Lir::InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) { in InvokeTrampoline()
Dint_mips.cc600 void MipsMir2Lir::GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1, in GenLongOp()
834 OpKind op = kOpBkpt; in GenShiftOpLong()
866 OpKind op = kOpBkpt; in GenShiftImmOpLong()
/art/compiler/dex/quick/x86/
Dcodegen_x86.h302 LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE;
304 LIR* OpReg(OpKind op, RegStorage r_dest_src) OVERRIDE;
307 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) OVERRIDE;
308 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) OVERRIDE;
311 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE;
312 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) OVERRIDE;
313 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) OVERRIDE;
388 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE;
838 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset);
839 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegLocation value);
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Dutility_x86.cc126 LIR* X86Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { in OpReg()
139 LIR* X86Mir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) { in OpRegImm()
201 LIR* X86Mir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) { in OpRegReg()
362 LIR* X86Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { in OpCondRegReg()
370 LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) { in OpRegMem()
398 LIR* X86Mir2Lir::OpMemReg(OpKind op, RegLocation rl_dest, int r_value) { in OpMemReg()
426 LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegLocation rl_value) { in OpRegMem()
451 LIR* X86Mir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, in OpRegRegReg()
504 LIR* X86Mir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src, int value) { in OpRegRegImm()
530 LIR* X86Mir2Lir::OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) { in OpThreadMem()
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Dint_x86.cc2406 void X86Mir2Lir::OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset) { in OpRegThreadMem()
2419 void X86Mir2Lir::OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset) { in OpRegThreadMem()
2556 OpKind op = static_cast<OpKind>(0); /* Make gcc happy */ in GenShiftImmOpLong()
3080 OpKind op = kOpBkpt; in GenArithOpInt()
3426 OpKind op = kOpBkpt; in GenShiftOpLong()
/art/compiler/dex/
Dcompiler_enums.h394 enum OpKind { enum
433 std::ostream& operator<<(std::ostream& os, const OpKind& rhs);
/art/compiler/dex/quick/
Dmir_to_lir.h841 void GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest,
1414 virtual LIR* OpMem(OpKind op, RegStorage r_base, int disp) = 0;
1416 virtual LIR* OpReg(OpKind op, RegStorage r_dest_src) = 0;
1419 virtual LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) = 0;
1420 virtual LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) = 0;
1453 virtual LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) = 0;
1455 virtual LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) = 0;
1456 virtual LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1,
1475 virtual LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) = 0;
Dgen_common.cc464 OpKind op = kOpInvalid; in GenIntNarrowing()
1444 void Mir2Lir::GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, in GenLong3Addr()
1519 OpKind op = kOpBkpt; in GenArithOpInt()
1805 OpKind op = static_cast<OpKind>(0); /* Make gcc happy */ in GenArithOpIntLit()
1958 OpKind first_op = kOpBkpt; in GenArithOpLong()
1959 OpKind second_op = kOpBkpt; in GenArithOpLong()
Dgen_invoke.cc1199 OpKind op = (size == k32) ? kOpRev : kOpRevsh; in GenInlinedReverseBytes()