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Searched refs:OpSize (Results 1 – 25 of 25) sorted by relevance

/art/compiler/dex/quick/mips/
Dcodegen_mips.h83 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size,
86 OpSize size) OVERRIDE;
90 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size,
93 OpSize size) OVERRIDE;
139 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
146 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
148 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
164 bool GenInlinedPeek(CallInfo* info, OpSize size);
165 bool GenInlinedPoke(CallInfo* info, OpSize size);
221 LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size);
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Dutility_mips.cc570 int scale, OpSize size) { in LoadBaseIndexed()
644 int scale, OpSize size) { in StoreBaseIndexed()
691 OpSize size) { in LoadBaseDispBody()
851 LIR* MipsMir2Lir::LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, in LoadBaseDisp()
876 OpSize size) { in StoreBaseDispBody()
1004 LIR* MipsMir2Lir::StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size, in StoreBaseDisp()
Dint_mips.cc366 bool MipsMir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { in GenInlinedPeek()
389 bool MipsMir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { in GenInlinedPoke()
667 void MipsMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, in GenArrayGet()
749 void MipsMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, in GenArrayPut()
Dtarget_mips.cc888 RegisterClass MipsMir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) { in RegClassForFieldLoadStore()
/art/compiler/dex/quick/arm/
Dcodegen_arm.h72 OpSize size, VolatileKind is_volatile) OVERRIDE;
74 OpSize size) OVERRIDE;
78 OpSize size, VolatileKind is_volatile) OVERRIDE;
80 OpSize size) OVERRIDE;
140 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
147 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
149 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
165 bool GenInlinedPeek(CallInfo* info, OpSize size);
166 bool GenInlinedPoke(CallInfo* info, OpSize size);
223 LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size);
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Dutility_arm.cc749 int scale, OpSize size) { in LoadBaseIndexed()
815 int scale, OpSize size) { in StoreBaseIndexed()
911 OpSize size) { in LoadBaseDispBody()
1031 OpSize size, VolatileKind is_volatile) { in LoadBaseDisp()
1061 OpSize size) { in StoreBaseDispBody()
1173 OpSize size, VolatileKind is_volatile) { in StoreBaseDisp()
Dint_arm.cc785 bool ArmMir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { in GenInlinedPeek()
810 bool ArmMir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { in GenInlinedPoke()
1375 void ArmMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, in GenArrayGet()
1461 void ArmMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, in GenArrayPut()
Dtarget_arm.cc565 RegisterClass ArmMir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) { in RegClassForFieldLoadStore()
/art/compiler/dex/quick/arm64/
Dcodegen_arm64.h68 OpSize size, VolatileKind is_volatile) OVERRIDE;
70 OpSize size) OVERRIDE;
73 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size,
76 OpSize size) OVERRIDE;
128 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
135 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
137 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
148 bool GenInlinedReverseBits(CallInfo* info, OpSize size) OVERRIDE;
159 bool GenInlinedPeek(CallInfo* info, OpSize size) OVERRIDE;
160 bool GenInlinedPoke(CallInfo* info, OpSize size) OVERRIDE;
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Dutility_arm64.cc1025 int scale, OpSize size) { in LoadBaseIndexed()
1110 int scale, OpSize size) { in StoreBaseIndexed()
1192 OpSize size) { in LoadBaseDispBody()
1273 OpSize size, VolatileKind is_volatile) { in LoadBaseDisp()
1288 OpSize size) { in StoreBaseDispBody()
1363 OpSize size, VolatileKind is_volatile) { in StoreBaseDisp()
Dint_arm64.cc708 bool Arm64Mir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { in GenInlinedPeek()
724 bool Arm64Mir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { in GenInlinedPoke()
1185 void Arm64Mir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, in GenArrayGet()
1259 void Arm64Mir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, in GenArrayPut()
1783 bool Arm64Mir2Lir::GenInlinedReverseBits(CallInfo* info, OpSize size) { in GenInlinedReverseBits()
Dtarget_arm64.cc596 RegisterClass Arm64Mir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) { in RegClassForFieldLoadStore()
/art/compiler/dex/quick/x86/
Dcodegen_x86.h93 OpSize size, VolatileKind is_volatile) OVERRIDE;
95 OpSize size) OVERRIDE;
100 OpSize size, VolatileKind is_volatile) OVERRIDE;
102 OpSize size) OVERRIDE;
172 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
175 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
177 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
191 bool GenInlinedReverseBits(CallInfo* info, OpSize size) OVERRIDE;
195 bool GenInlinedPeek(CallInfo* info, OpSize size) OVERRIDE;
196 bool GenInlinedPoke(CallInfo* info, OpSize size) OVERRIDE;
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Dtarget_x86.cc743 OpSize size = cu_->target64 ? k64 : k32; in SpillCoreRegs()
763 OpSize size = cu_->target64 ? k64 : k32; in UnSpillCoreRegs()
814 RegisterClass X86Mir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) { in RegClassForFieldLoadStore()
1707 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenMultiplyVector()
1741 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenAddVector()
1776 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenSubtractVector()
1855 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenShiftLeftVector()
1884 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenSignedShiftRightVector()
1912 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenUnsignedShiftRightVector()
1985 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenAddReduceVector()
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Dutility_x86.cc644 int displacement, RegStorage r_dest, OpSize size) { in LoadBaseIndexedDisp()
772 int scale, OpSize size) { in LoadBaseIndexed()
777 OpSize size, VolatileKind is_volatile) { in LoadBaseDisp()
792 int displacement, RegStorage r_src, OpSize size, in StoreBaseIndexedDisp()
906 int scale, OpSize size) { in StoreBaseIndexed()
910 LIR* X86Mir2Lir::StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size, in StoreBaseDisp()
1001 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in AnalyzeMIR()
Dint_x86.cc1031 bool X86Mir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { in GenInlinedPeek()
1057 bool X86Mir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { in GenInlinedPoke()
1303 bool X86Mir2Lir::GenInlinedReverseBits(CallInfo* info, OpSize size) { in GenInlinedReverseBits()
2445 void X86Mir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, in GenArrayGet()
2494 void X86Mir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, in GenArrayPut()
/art/compiler/dex/quick/
Dmir_to_lir.h568 RegisterClass RegClassBySize(OpSize size) { in RegClassBySize()
824 void GenSput(MIR* mir, RegLocation rl_src, OpSize size);
827 void GenSget(MIR* mir, RegLocation rl_dest, OpSize size, Primitive::Type type);
828 void GenIGet(MIR* mir, int opt_flags, OpSize size, Primitive::Type type,
830 void GenIPut(MIR* mir, int opt_flags, OpSize size,
950 virtual bool GenInlinedReverseBits(CallInfo* info, OpSize size);
951 bool GenInlinedReverseBytes(CallInfo* info, OpSize size);
1152 OpSize size, VolatileKind is_volatile) = 0;
1154 int scale, OpSize size) = 0;
1158 OpSize size, VolatileKind is_volatile) = 0;
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Dmir_to_lir.cc196 OpSize op_size = rl_dest.wide ? k64 : (rl_dest.ref ? kReference : k32); in LoadArgDirect()
213 OpSize size = arg.IsRef() ? kReference : in SpillArg()
225 OpSize size = arg.IsRef() ? kReference : in UnspillArg()
250 OpSize size; in GenSpecialIGet()
322 OpSize size; in GenSpecialIPut()
Ddex_file_method_inliner.cc547 return backend->GenInlinedReverseBytes(info, static_cast<OpSize>(intrinsic.d.data)); in GenIntrinsic()
549 return backend->GenInlinedReverseBits(info, static_cast<OpSize>(intrinsic.d.data)); in GenIntrinsic()
600 return backend->GenInlinedPeek(info, static_cast<OpSize>(intrinsic.d.data)); in GenIntrinsic()
602 return backend->GenInlinedPoke(info, static_cast<OpSize>(intrinsic.d.data)); in GenIntrinsic()
Dgen_loadstore.cc56 OpSize op_size; in LoadValueDirect()
Dgen_common.cc685 void Mir2Lir::GenSput(MIR* mir, RegLocation rl_src, OpSize size) { in GenSput()
762 void Mir2Lir::GenSget(MIR* mir, RegLocation rl_dest, OpSize size, Primitive::Type type) { in GenSget()
862 void Mir2Lir::GenIGet(MIR* mir, int opt_flags, OpSize size, Primitive::Type type, in GenIGet()
941 void Mir2Lir::GenIPut(MIR* mir, int opt_flags, OpSize size, in GenIPut()
2259 bool Mir2Lir::SizeMatchesTypeForEntrypoint(OpSize size, Primitive::Type type) { in SizeMatchesTypeForEntrypoint()
Dgen_invoke.cc1166 bool Mir2Lir::GenInlinedReverseBytes(CallInfo* info, OpSize size) { in GenInlinedReverseBytes()
1269 bool Mir2Lir::GenInlinedReverseBits(CallInfo* info, OpSize size) { in GenInlinedReverseBits()
/art/compiler/dex/
Dcompiler_enums.h380 enum OpSize { enum
392 std::ostream& operator<<(std::ostream& os, const OpSize& kind);
Dmir_graph.cc1285 OpSize type = static_cast<OpSize>(type_size >> 16); in FillTypeSizeString()
/art/compiler/optimizing/
Dintrinsics.cc49 switch (static_cast<OpSize>(data)) { in GetType()