Searched refs:R10 (Results 1 – 10 of 10) sorted by relevance
/art/runtime/arch/x86_64/ |
D | registers_x86_64.h | 40 R10 = 10, enumerator
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D | context_x86_64.cc | 73 gprs_[R10] = nullptr; in SmashCallerSaves()
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/art/runtime/arch/arm/ |
D | registers_arm.h | 37 R10 = 10, enumerator
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D | quick_method_frame_info_arm.h | 32 (1 << art::arm::R10) | (1 << art::arm::R11);
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/art/compiler/jni/quick/arm/ |
D | calling_convention_arm.cc | 231 callee_save_regs_.push_back(ArmManagedRegister::FromCoreRegister(R10)); in ArmJniCallingConvention() 242 result = 1 << R5 | 1 << R6 | 1 << R7 | 1 << R8 | 1 << R10 | 1 << R11 | 1 << LR; in CoreSpillMask()
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/art/compiler/utils/x86_64/ |
D | assembler_x86_64_test.cc | 153 registers_.push_back(new x86_64::CpuRegister(x86_64::R10)); in SetUpHelpers() 170 secondary_register_names_.emplace(x86_64::CpuRegister(x86_64::R10), "r10d"); in SetUpHelpers() 187 tertiary_register_names_.emplace(x86_64::CpuRegister(x86_64::R10), "r10w"); in SetUpHelpers() 204 quaternary_register_names_.emplace(x86_64::CpuRegister(x86_64::R10), "r10b"); in SetUpHelpers() 1104 spill_regs.push_back(ManagedFromCpu(x86_64::R10)); in buildframe_test_fn() 1149 spill_regs.push_back(ManagedFromCpu(x86_64::R10)); in removeframe_test_fn()
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/art/compiler/utils/arm/ |
D | assembler_thumb2_test.cc | 58 new arm::Register(arm::R10), in SetUpHelpers()
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D | assembler_arm32_test.cc | 92 new arm::Register(arm::R10), in SetUpHelpers() 150 shifter_operands_.push_back(arm::ShifterOperand(arm::R10)); in SetUpHelpers()
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/art/compiler/utils/ |
D | assembler_thumb_test.cc | 885 __ mul(R8, R9, R10); in TEST() 894 __ umull(R8, R9, R10, R11); in TEST() 908 __ sdiv(R8, R9, R10); in TEST() 911 __ udiv(R8, R9, R10); in TEST()
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/art/compiler/optimizing/ |
D | code_generator_arm.cc | 48 { R5, R6, R7, R8, R10, R11, PC };
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