Searched refs:R6 (Results 1 – 9 of 9) sorted by relevance
| /art/runtime/arch/arm/ |
| D | registers_arm.h | 33 R6 = 6, enumerator
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| D | quick_method_frame_info_arm.h | 31 (1 << art::arm::R5) | (1 << art::arm::R6) | (1 << art::arm::R7) | (1 << art::arm::R8) |
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| /art/compiler/jni/quick/arm/ |
| D | calling_convention_arm.cc | 228 callee_save_regs_.push_back(ArmManagedRegister::FromCoreRegister(R6)); in ArmJniCallingConvention()
242 result = 1 << R5 | 1 << R6 | 1 << R7 | 1 << R8 | 1 << R10 | 1 << R11 | 1 << LR; in CoreSpillMask()
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| /art/compiler/optimizing/ |
| D | codegen_test.cc | 64 AddAllocatedRegister(Location::RegisterLocation(arm::R6)); in TestCodeGeneratorARM()
71 blocked_core_registers_[arm::R6] = false; in SetupBlockedRegisters()
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| D | code_generator_arm.cc | 48 { R5, R6, R7, R8, R10, R11, PC };
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| /art/compiler/utils/arm/ |
| D | assembler_thumb2_test.cc | 54 new arm::Register(arm::R6), in SetUpHelpers()
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| D | assembler_arm32_test.cc | 88 new arm::Register(arm::R6), in SetUpHelpers()
146 shifter_operands_.push_back(arm::ShifterOperand(arm::R6)); in SetUpHelpers()
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| D | managed_register_arm_test.cc | 283 EXPECT_EQ(R6, reg.AsRegisterPairLow()); in TEST()
285 EXPECT_TRUE(reg.Equals(ArmManagedRegister::FromCoreRegisterPair(R6))); in TEST()
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| D | assembler_thumb2.cc | 2636 tmp_reg = base != R5 ? R5 : R6; in StoreToOffset()
2666 DCHECK(tmp_reg == R5 || tmp_reg == R6); in StoreToOffset()
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