Searched refs:ROR (Results 1 – 6 of 6) sorted by relevance
| /art/compiler/utils/arm/ |
| D | assembler_arm.cc | 96 case arm::Shift::ROR: in encodingArm()
101 shift_type = static_cast<uint32_t>(arm::Shift::ROR); // Same encoding as ROR. in encodingArm()
141 return ROR << 4 | static_cast<uint32_t>(rm_); in encodingThumb()
177 shift = ROR; in encodingArm()
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| D | constants_arm.h | 154 ROR = 3, // Rotate right enumerator
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| D | assembler_arm32.cc | 1192 movs(rd, ShifterOperand(rm, ROR, shift_imm), cond); in Ror()
1194 mov(rd, ShifterOperand(rm, ROR, shift_imm), cond); in Ror()
1200 movs(rd, ShifterOperand(rm, ROR, 0), cond); in Rrx()
1202 mov(rd, ShifterOperand(rm, ROR, 0), cond); in Rrx()
1240 movs(rd, ShifterOperand(rm, ROR, rn), cond); in Ror()
1242 mov(rd, ShifterOperand(rm, ROR, rn), cond); in Ror()
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| D | assembler_thumb2.cc | 744 if (opcode == MOV && so.IsRegister() && so.IsShift() && so.GetShift() == ROR) { in Is32BitDataProcessing()
920 case ROR: in Emit16BitDataProcessing()
1204 if (IsHighRegister(rd) || IsHighRegister(rm) || shift == ROR || shift == RRX) { in EmitShift()
1210 case ROR: opcode = 3U /* 0b11 */; break; in EmitShift()
1254 case ROR: opcode = 3U /* 0b11 */; break; in EmitShift()
2350 EmitShift(rd, rm, ROR, shift_imm, setcc); in Ror()
2384 EmitShift(rd, rm, ROR, rn, setcc); in Ror()
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| D | assembler_arm32_test.cc | 165 arm::Shift::LSL, arm::Shift::LSR, arm::Shift::ASR, arm::Shift::ROR, arm::Shift::RRX in SetUpHelpers()
201 arm::Shift::ROR }; in CreateRegisterShifts()
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| /art/compiler/utils/ |
| D | assembler_thumb_test.cc | 343 __ mov(R3, ShifterOperand(R4, ROR, 7)); in TEST()
344 __ mov(R3, ShifterOperand(R4, ROR)); in TEST()
350 __ mov(R8, ShifterOperand(R4, ROR, 7)); in TEST()
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