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Searched refs:S0 (Results 1 – 22 of 22) sorted by relevance

/art/compiler/utils/arm/
Dmanaged_register_arm_test.cc69 ArmManagedRegister reg = ArmManagedRegister::FromSRegister(S0); in TEST()
76 EXPECT_EQ(S0, reg.AsSRegister()); in TEST()
134 EXPECT_EQ(S0, reg.AsOverlappingDRegisterLow()); in TEST()
136 EXPECT_TRUE(reg.Equals(ArmManagedRegister::FromSRegisterPair(S0))); in TEST()
294 EXPECT_TRUE(!no_reg.Equals(ArmManagedRegister::FromSRegister(S0))); in TEST()
302 EXPECT_TRUE(!reg_R0.Equals(ArmManagedRegister::FromSRegister(S0))); in TEST()
310 EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::FromSRegister(S0))); in TEST()
320 EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::FromSRegister(S0))); in TEST()
326 ArmManagedRegister reg_S0 = ArmManagedRegister::FromSRegister(S0); in TEST()
330 EXPECT_TRUE(reg_S0.Equals(ArmManagedRegister::FromSRegister(S0))); in TEST()
[all …]
Dassembler_arm32.cc349 EmitVFPsss(cond, B23 | B21 | B20 | B6, sd, S0, sm); in vmovs()
366 sd, S0, S0); in vmovs()
461 EmitVFPsss(cond, B23 | B21 | B20 | B7 | B6, sd, S0, sm); in vabss()
471 EmitVFPsss(cond, B23 | B21 | B20 | B16 | B6, sd, S0, sm); in vnegs()
481 EmitVFPsss(cond, B23 | B21 | B20 | B16 | B7 | B6, sd, S0, sm); in vsqrts()
500 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B16 | B7 | B6, sd, S0, sm); in vcvtis()
510 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B7 | B6, sd, S0, sm); in vcvtsi()
520 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B7 | B6, sd, S0, sm); in vcvtus()
530 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B6, sd, S0, sm); in vcvtsu()
540 EmitVFPsss(cond, B23 | B21 | B20 | B18 | B6, sd, S0, sm); in vcmps()
[all …]
Dassembler_thumb2.cc454 sd, S0, S0); in vmovs()
477 EmitVFPsss(cond, B23 | B21 | B20 | B6, sd, S0, sm); in vmovs()
559 EmitVFPsss(cond, B23 | B21 | B20 | B7 | B6, sd, S0, sm); in vabss()
569 EmitVFPsss(cond, B23 | B21 | B20 | B16 | B6, sd, S0, sm); in vnegs()
579 EmitVFPsss(cond, B23 | B21 | B20 | B16 | B7 | B6, sd, S0, sm); in vsqrts()
598 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B16 | B7 | B6, sd, S0, sm); in vcvtis()
608 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B7 | B6, sd, S0, sm); in vcvtsi()
618 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B7 | B6, sd, S0, sm); in vcvtus()
628 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B6, sd, S0, sm); in vcvtsu()
638 EmitVFPsss(cond, B23 | B21 | B20 | B18 | B6, sd, S0, sm); in vcmps()
[all …]
Dassembler_arm.cc49 if (rhs >= S0 && rhs < kNumberOfSRegisters) { in operator <<()
/art/compiler/utils/arm64/
Dmanaged_register_arm64_test.cc169 Arm64ManagedRegister sreg = Arm64ManagedRegister::FromSRegister(S0); in TEST()
177 EXPECT_EQ(S0, reg.AsOverlappingSRegister()); in TEST()
219 Arm64ManagedRegister reg = Arm64ManagedRegister::FromSRegister(S0); in TEST()
227 EXPECT_EQ(S0, reg.AsSRegister()); in TEST()
229 EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromSRegister(S0))); in TEST()
276 EXPECT_TRUE(!no_reg.Equals(Arm64ManagedRegister::FromSRegister(S0))); in TEST()
283 EXPECT_TRUE(!reg_X0.Equals(Arm64ManagedRegister::FromSRegister(S0))); in TEST()
292 EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromSRegister(S0))); in TEST()
299 EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::FromSRegister(S0))); in TEST()
308 EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromSRegister(S0))); in TEST()
[all …]
/art/runtime/arch/arm/
Dregisters_arm.cc38 if (rhs >= S0 && rhs < kNumberOfSRegisters) { in operator <<()
Dregisters_arm.h57 S0 = 0, enumerator
Dcontext_arm.cc81 fprs_[S0] = nullptr; in SmashCallerSaves()
Dquick_method_frame_info_arm.h41 (1 << art::arm::S0) | (1 << art::arm::S1) | (1 << art::arm::S2) | (1 << art::arm::S3) |
/art/runtime/arch/arm64/
Dregisters_arm64.cc66 if (rhs >= S0 && rhs < kNumberOfSRegisters) { in operator <<()
Dregisters_arm64.h154 S0 = 0, enumerator
/art/runtime/arch/mips/
Dregisters_mips.h46 S0 = 16, // Saved values. enumerator
Dquick_method_frame_info_mips.h34 (1 << art::mips::S0) | (1 << art::mips::S1);
/art/runtime/arch/mips64/
Dregisters_mips64.h46 S0 = 16, // Saved values. enumerator
Dquick_method_frame_info_mips64.h37 (1 << art::mips64::S0) | (1 << art::mips64::S1);
/art/compiler/jni/quick/arm64/
Dcalling_convention_arm64.cc38 S0, S1, S2, S3, S4, S5, S6, S7
56 return Arm64ManagedRegister::FromSRegister(S0); in ReturnRegisterForShorty()
/art/compiler/jni/quick/arm/
Dcalling_convention_arm.cc31 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
73 return ArmManagedRegister::FromSRegister(S0); in ReturnRegister()
/art/compiler/optimizing/
Dcode_generator_arm.h40 { S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 };
48 static constexpr SRegister kRuntimeParameterFpuRegisters[] = { S0, S1, S2, S3 };
Dcode_generator_mips64.h59 { S0, S1, S2, S3, S4, S5, S6, S7, GP, S8, RA }; // TODO: review
Dcode_generator_arm.cc551 __ cfi().RelOffsetForMany(DWARFReg(S0), 0, fpu_spill_mask_, kArmWordSize); in GenerateFrameEntry()
694 return Location::FpuRegisterLocation(S0); in GetReturnLocation()
702 return Location::FpuRegisterPairLocation(S0, S1); in GetReturnLocation()
2333 locations->SetOut(Location::FpuRegisterLocation(S0)); in VisitRem()
2343 locations->SetOut(Location::Location::FpuRegisterPairLocation(S0, S1)); in VisitRem()
Dcode_generator_mips64.cc889 blocked_core_registers_[S0] = true; in SetupBlockedRegisters()
/art/compiler/utils/
Dassembler_thumb_test.cc942 __ vadds(S0, S1, S2); in TEST()
943 __ vsubs(S0, S1, S2); in TEST()
944 __ vmuls(S0, S1, S2); in TEST()
945 __ vmlas(S0, S1, S2); in TEST()
946 __ vmlss(S0, S1, S2); in TEST()
947 __ vdivs(S0, S1, S2); in TEST()
948 __ vabss(S0, S1); in TEST()
949 __ vnegs(S0, S1); in TEST()
950 __ vsqrts(S0, S1); in TEST()
999 __ vcmps(S0, S1); in TEST()